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1 6 jdoin
SPI_MASTER_ATLYS
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This is a ISE 13.1 project to test the spi_master.vhd, spi_slave.vhd and grp_debouncer.vhd models in silicon.
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The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies.
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See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested.
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The circuit verifies both master and slave cores, with transmit and receive streams operating full-duplex at 50MHz of SPI clock.
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This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license.
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The files are:
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spi_master.vhd                  vhdl model for the spi_master interface
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grp_debouncer.vhd               vhdl model for the switch debouncer
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spi_master_atlys_top.vhd        vhdl model for the toplevel block to synthesize for the Atlys
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spi_master_atlys.xise           ISE 13.1 project file
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spi_master_atlys.ucf            pin lock constraints for the Atlys board
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spi_master_scope_photos.zip     Tektronix MSO2014 screenshots for the verification tests
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spi_master_envsettings.html     synthesis env settings, with the tools setup used
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ATLYS_01.SET                    Tek MSO2014 settings file with the debug pin names
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spi_master_atlys_top_bit.zip    bitgen file to program the Atlys board
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If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.
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If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
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                http://opencores.org/project,spi_master_slave,bugtracker
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In any case, thank you very much for testing this core.
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Jonny Doin
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jdoin@opencores.org
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