OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_master.vhd] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 jdoin
-----------------------------------------------------------------------------------------------------------------------
2 12 jdoin
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
3 5 jdoin
-- 
4
-- Create Date:     12:18:12 04/25/2011 
5
-- Module Name:     SPI_MASTER - RTL
6
-- Project Name:    SPI MASTER / SLAVE INTERFACE
7
-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
9
-- Description: 
10
--
11
--      This block is the SPI master interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
13
--      a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
14
--      All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
15
--      'sclk_i' clock.
16
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
17
--      clock domains.
18
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
19
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling 
20
--      ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
21
--
22
--      SPI CLOCK GENERATION
23
--      ====================
24
--
25
--      The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference 
26
--      clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the 
27
--      SPI_2X clock, which is 2x the desired SCK frequency. 
28
--      All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
29
--      at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
30
--      by combinatorial clock dividers outputs.
31
--      The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
32
--
33
--      PARALLEL WRITE INTERFACE
34
--      ========================
35
--      The parallel interface has an input port 'di_i' and an output port 'do_o'.
36
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
37
--      that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the 
38
--      next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
39
--      For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
40
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
41
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
42
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
43
--      if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
44
--      enters idle state and deasserts SSEL.
45
--      When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering 
46
--      idle state, if a previously loaded data has already been transferred.
47
--
48
--      PARALLEL WRITE SEQUENCE
49
--      =======================
50
--                         __    __    __    __    __    __    __ 
51
--      pclk_i          __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
52
--                               ___________                        
53
--      di_req_o        ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'pclk_i'
54
--                      ______________ ___________________________...
55
--      di_i            __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
56
--                                                 _______                        
57
--      wren_i          __________________________/       \_______...     -- user strobes 'wren_i' for one cycle of 'pclk_i'
58
--                      
59
--
60
--      PARALLEL READ INTERFACE
61
--      =======================
62
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
63 6 jdoin
--      the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
64
--      The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
65 5 jdoin
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
66
--      When the interface is idle, data at the 'do_o' port holds the last word received.
67
--
68
--      PARALLEL READ SEQUENCE
69
--      ======================
70
--                      ______        ______        ______        ______   
71 7 jdoin
--      spi_clk          bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- internal spi 2x base clock
72 5 jdoin
--                      _    __    __    __    __    __    __    __    __  
73
--      pclk_i           \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock (may be async to sclk_i)
74
--                      _____________ _____________________________________...  -- 1) rx data is transferred to 'do_buffer_reg'
75 6 jdoin
--      do_o            ___old_data__X__________new_data___________________...  --    after last rx bit, at rising 'spi_clk'.
76 5 jdoin
--                                                   ____________               
77
--      do_valid_o      ____________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
78
--                                                                              --    on the 3rd 'pclk_i' rising edge.
79
--
80
--
81
--      The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
82
--      but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
83
--      of the interface, for full duplex operation.
84
--
85
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
86
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
87
--
88
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
89
--                                                                   
90
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
91 6 jdoin
--                                                                   
92 5 jdoin
--      Author(s):      Jonny Doin, jdoin@opencores.org
93 6 jdoin
--                                                                   
94 5 jdoin
--      Copyright (C) 2011 Authors and OPENCORES.ORG
95 6 jdoin
--      --------------------------------------------
96
--                                                                   
97
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
98 5 jdoin
--      removed from the file and that any derivative work contains the original copyright notice and the associated 
99 6 jdoin
--      disclaimer. 
100
--                                                                   
101 5 jdoin
--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
102
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
103 6 jdoin
--      (at your option) any later version.
104
--                                                                   
105
--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
106
--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
107
--      details.
108
--
109 5 jdoin
--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
110 6 jdoin
--      it from http://www.opencores.org/lgpl.shtml
111 5 jdoin
--                                                                   
112
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
113
--
114
-- 2011/04/28   v0.01.0010  [JD]    shifter implemented as a sequential process. timing problems and async issues in synthesis.
115
-- 2011/05/01   v0.01.0030  [JD]    changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
116
-- 2011/05/05   v0.01.0034  [JD]    added an internal buffer register for rx_data, to allow greater liberty in data load/store.
117
-- 2011/05/08   v0.10.0038  [JD]    increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
118
--                                  logic, based on generics, and do_valid_o signal.
119
-- 2011/05/13   v0.20.0045  [JD]    streamlined signal names, added PREFETCH parameter, added assertions.
120
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
121
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
122
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
123
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
124
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
125
--                                  synthesis LUT overhead in Spartan-6 architecture.
126
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
127 12 jdoin
-- 2011/06/12   v0.97.0079  [JD]    streamlined wr_ack for all cases and eliminated unnecessary register resets.
128 5 jdoin
-- 2011/06/14   v0.97.0083  [JD]    (bug CPHA effect) : redesigned SCK output circuit.
129
--                                  (minor bug) : removed fsm registers from (not rst_i) chip enable.
130
-- 2011/06/15   v0.97.0086  [JD]    removed master MISO input register, to relax MISO data setup time (to get higher speed).
131
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
132
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
133
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
134
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
135 6 jdoin
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
136 10 jdoin
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
137 11 jdoin
-- 2011/07/17   v1.11.0080  [JD]    BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
138
--                                  BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
139
-- 2011/07/18   v1.12.0105  [JD]    CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
140
--                                  for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
141 12 jdoin
-- 2011/07/24   v1.13.0125  [JD]    FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
142
--                                  Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
143
-- 2011/07/29   v1.14.0130  [JD]    Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
144
--                                  for each state, to avoid reported inference problems in some synthesis engines.
145
--                                  Streamlined port names and indentation blocks.
146 5 jdoin
--
147
-----------------------------------------------------------------------------------------------------------------------
148
--  TODO
149
--  ====
150
--
151
-----------------------------------------------------------------------------------------------------------------------
152
library ieee;
153
use ieee.std_logic_1164.all;
154
use ieee.numeric_std.all;
155 6 jdoin
use ieee.std_logic_unsigned.all;
156 5 jdoin
 
157
--================================================================================================================
158 10 jdoin
-- SYNTHESIS CONSIDERATIONS
159
-- ========================
160 5 jdoin
-- There are several output ports that are used to simulate and verify the core operation. 
161
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
162
-- circuitry. 
163
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
164
-- synthesis tool will remove the receive logic from the generated circuitry.
165
--================================================================================================================
166
 
167
entity spi_master is
168
    Generic (
169
        N : positive := 32;                                             -- 32bit serial word length is default
170
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
171
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
172
        PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
173
        SPI_2X_CLK_DIV : positive := 5);                                -- for a 100MHz sclk_i, yields a 10MHz SCK
174
    Port (
175
        sclk_i : in std_logic := 'X';                                   -- high-speed serial interface system clock
176
        pclk_i : in std_logic := 'X';                                   -- high-speed parallel interface system clock
177
        rst_i : in std_logic := 'X';                                    -- reset core
178 7 jdoin
        ---- serial interface ----
179 5 jdoin
        spi_ssel_o : out std_logic;                                     -- spi bus slave select line
180
        spi_sck_o : out std_logic;                                      -- spi bus sck
181
        spi_mosi_o : out std_logic;                                     -- spi bus mosi output
182
        spi_miso_i : in std_logic := 'X';                               -- spi bus spi_miso_i input
183 7 jdoin
        ---- parallel interface ----
184 5 jdoin
        di_req_o : out std_logic;                                       -- preload lookahead data request line
185 6 jdoin
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel data in (clocked on rising spi_clk after last bit)
186 5 jdoin
        wren_i : in std_logic := 'X';                                   -- user data write enable, starts transmission when interface is idle
187 12 jdoin
        wr_ack_o : out std_logic;                                       -- write acknowledge
188 6 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid signal, valid during one spi_clk rising edge.
189
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked on rising spi_clk after last bit)
190 7 jdoin
        --- debug ports: can be removed or left unconnected for the application circuit ---
191 12 jdoin
        sck_ena_o : out std_logic;                                      -- debug: internal sck enable signal
192
        sck_ena_ce_o : out std_logic;                                   -- debug: internal sck clock enable signal
193 5 jdoin
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
194
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
195
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
196
        state_dbg_o : out std_logic_vector (5 downto 0);                -- debug: internal state register
197
        core_clk_o : out std_logic;
198
        core_n_clk_o : out std_logic;
199
        core_ce_o : out std_logic;
200
        core_n_ce_o : out std_logic;
201
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
202
    );
203
end spi_master;
204
 
205
--================================================================================================================
206
-- this architecture is a pipelined register-transfer description.
207 6 jdoin
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
208 5 jdoin
--================================================================================================================
209 10 jdoin
architecture RTL of spi_master is
210 6 jdoin
    -- core clocks, generated from 'sclk_i': initialized to differential values
211 11 jdoin
    signal core_clk     : std_logic := '0';     -- continuous core clock, positive logic
212
    signal core_n_clk   : std_logic := '1';     -- continuous core clock, negative logic
213
    signal core_ce      : std_logic := '0';     -- core clock enable, positive logic
214
    signal core_n_ce    : std_logic := '1';     -- core clock enable, negative logic
215 5 jdoin
    -- spi bus clock, generated from the CPOL selected core clock polarity
216 11 jdoin
    signal spi_2x_ce    : std_logic := '1';     -- spi_2x clock enable
217
    signal spi_clk      : std_logic := '0';     -- spi bus output clock
218 12 jdoin
    signal spi_clk_reg  : std_logic;            -- output pipeline delay for spi sck (do NOT global initialize)
219 5 jdoin
    -- core fsm clock enables
220 11 jdoin
    signal fsm_ce       : std_logic := '1';     -- fsm clock enable
221 12 jdoin
    signal sck_ena_ce   : std_logic := '1';     -- SCK clock enable
222 11 jdoin
    signal samp_ce      : std_logic := '1';     -- data sampling clock enable
223 5 jdoin
    --
224
    -- GLOBAL RESET: 
225
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
226
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
227 7 jdoin
    --      especially for the Spartan-6 and newer CLB architectures, where a async reset can
228 5 jdoin
    --      reduce the usability of the slice registers, due to the need to share the control 
229
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
230 7 jdoin
    --      By using GSR for the initialization, and reducing async RESET local init to the bare
231 5 jdoin
    --      essential, the model achieves better LUT/FF packing and CLB usability.
232
    --
233
    -- internal state signals for register and combinatorial stages
234
    signal state_next : natural range N+1 downto 0 := 0;
235
    signal state_reg : natural range N+1 downto 0 := 0;
236
    -- shifter signals for register and combinatorial stages
237
    signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
238
    signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
239
    -- input bit sampled buffer
240
    signal rx_bit_reg : std_logic := '0';
241
    -- buffered di_i data signals for register and combinatorial stages
242
    signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
243
    -- internal wren_i stretcher for fsm combinatorial stage
244
    signal wren : std_logic := '0';
245 12 jdoin
    signal wr_ack_next : std_logic := '0';
246
    signal wr_ack_reg : std_logic := '0';
247 5 jdoin
    -- internal SSEL enable control signals
248 12 jdoin
    signal ssel_ena_next : std_logic := '0';
249
    signal ssel_ena_reg : std_logic := '0';
250 5 jdoin
    -- internal SCK enable control signals
251 12 jdoin
    signal sck_ena_next : std_logic;
252
    signal sck_ena_reg : std_logic;
253 5 jdoin
    -- buffered do_o data signals for register and combinatorial stages
254
    signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
255
    signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
256
    -- internal signal to flag transfer to do_buffer_reg
257
    signal do_transfer_next : std_logic := '0';
258
    signal do_transfer_reg : std_logic := '0';
259
    -- internal input data request signal 
260
    signal di_req_next : std_logic := '0';
261
    signal di_req_reg : std_logic := '0';
262
    -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
263
    signal do_valid_A : std_logic := '0';
264
    signal do_valid_B : std_logic := '0';
265
    signal do_valid_C : std_logic := '0';
266
    signal do_valid_D : std_logic := '0';
267
    signal do_valid_next : std_logic := '0';
268
    signal do_valid_o_reg : std_logic := '0';
269
    -- cross-clock di_req_reg -> di_req_o_reg pipeline
270
    signal di_req_o_A : std_logic := '0';
271
    signal di_req_o_B : std_logic := '0';
272
    signal di_req_o_C : std_logic := '0';
273
    signal di_req_o_D : std_logic := '0';
274
    signal di_req_o_next : std_logic := '1';
275
    signal di_req_o_reg : std_logic := '1';
276
begin
277
    --=============================================================================================
278
    --  GENERICS CONSTRAINTS CHECKING
279
    --=============================================================================================
280
    -- minimum word width is 8 bits
281 6 jdoin
    assert N >= 8
282
    report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
283 5 jdoin
    severity FAILURE;
284
    -- minimum prefetch lookahead check
285 6 jdoin
    assert PREFETCH >= 2
286
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
287 5 jdoin
    severity FAILURE;
288
    -- maximum prefetch lookahead check
289 6 jdoin
    assert PREFETCH <= N-5
290
    report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
291 5 jdoin
    severity FAILURE;
292
    -- SPI_2X_CLK_DIV clock divider value must not be zero
293 6 jdoin
    assert SPI_2X_CLK_DIV > 0
294
    report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
295 5 jdoin
    severity FAILURE;
296
 
297
    --=============================================================================================
298
    --  CLOCK GENERATION
299
    --=============================================================================================
300
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
301
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
302
    -- the spi clock generator and the input sampling clock.
303
    -- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock 
304
    -- for the core clocking.
305
    -- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only 
306 7 jdoin
    -- differential interconnect delay skew.
307 5 jdoin
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
308
    -- enables are used to control clocking of all internal synchronous circuitry. 
309
    -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, 
310
    -- based on the configuration of CPOL and CPHA.
311
    -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
312
    -- modes, by a single high-speed global clock, preserving clock resources.
313
    -----------------------------------------------------------------------------------------------
314 6 jdoin
    -- generate the 2x spi base clock enable from the serial high-speed input clock
315 5 jdoin
    spi_2x_ce_gen_proc: process (sclk_i) is
316
        variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
317
    begin
318
        if sclk_i'event and sclk_i = '1' then
319
            if clk_cnt = SPI_2X_CLK_DIV-1 then
320
                spi_2x_ce <= '1';
321
                clk_cnt := 0;
322
            else
323
                spi_2x_ce <= '0';
324
                clk_cnt := clk_cnt + 1;
325
            end if;
326
        end if;
327
    end process spi_2x_ce_gen_proc;
328
    -----------------------------------------------------------------------------------------------
329 6 jdoin
    -- generate the core antiphase clocks and clock enables from the 2x base CE.
330 5 jdoin
    core_clock_gen_proc : process (sclk_i) is
331
    begin
332
        if sclk_i'event and sclk_i = '1' then
333
            if spi_2x_ce = '1' then
334
                -- generate the 2 antiphase core clocks
335
                core_clk <= core_n_clk;
336
                core_n_clk <= not core_n_clk;
337
                -- generate the 2 phase core clock enables
338
                core_ce <= core_n_clk;
339
                core_n_ce <= not core_n_clk;
340
            else
341
                core_ce <= '0';
342
                core_n_ce <= '0';
343
            end if;
344
        end if;
345
    end process core_clock_gen_proc;
346 12 jdoin
 
347
    --=============================================================================================
348
    --  GENERATE BLOCKS
349
    --=============================================================================================
350 5 jdoin
    -- spi clk generator: generate spi_clk from core_clk depending on CPOL
351 12 jdoin
    spi_sck_cpol_0_proc: if CPOL = '0' generate
352
    begin
353
        spi_clk <= core_clk;            -- for CPOL=0, spi clk has idle LOW
354
    end generate;
355
 
356
    spi_sck_cpol_1_proc: if CPOL = '1' generate
357
    begin
358
        spi_clk <= core_n_clk;          -- for CPOL=1, spi clk has idle HIGH
359
    end generate;
360
 
361 5 jdoin
    -----------------------------------------------------------------------------------------------
362
    -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
363
    -- always sample data at the half-cycle of the fsm update cell
364 12 jdoin
    samp_ce_cpha_0_proc: if CPHA = '0' generate
365
    begin
366
        samp_ce <= core_ce;
367
    end generate;
368
 
369
    samp_ce_cpha_1_proc: if CPHA = '1' generate
370
    begin
371
        samp_ce <= core_n_ce;
372
    end generate;
373 5 jdoin
    -----------------------------------------------------------------------------------------------
374 6 jdoin
    -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
375 12 jdoin
    fsm_ce_cpha_0_proc: if CPHA = '0' generate
376
    begin
377
        fsm_ce <= core_n_ce;            -- for CPHA=0, latch registers at rising edge of negative core clock enable
378
    end generate;
379
 
380
    fsm_ce_cpha_1_proc: if CPHA = '1' generate
381
    begin
382
        fsm_ce <= core_ce;              -- for CPHA=1, latch registers at rising edge of positive core clock enable
383
    end generate;
384 5 jdoin
 
385 12 jdoin
    sck_ena_ce <= core_n_ce;            -- for CPHA=1, SCK is advanced one-half cycle
386 11 jdoin
 
387 5 jdoin
    --=============================================================================================
388
    --  REGISTERED INPUTS
389
    --=============================================================================================
390
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
391
    --
392
    --  ATTENTION:  REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO 
393
    --              REDUCED DEMAND ON MISO SETUP TIME. 
394
    --
395 10 jdoin
    rx_bit_proc : process (sclk_i, spi_miso_i) is
396 5 jdoin
    begin
397 11 jdoin
        if sclk_i'event and sclk_i = '1' then
398
            if samp_ce = '1' then
399 5 jdoin
                rx_bit_reg <= spi_miso_i;
400 11 jdoin
            end if;
401
        end if;
402 5 jdoin
    end process rx_bit_proc;
403
 
404
    --=============================================================================================
405
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
406
    --=============================================================================================
407
    -- do_valid_o and di_req_o strobe output logic
408
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
409
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
410
    out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
411
                                  do_valid_A, do_valid_B, do_valid_D,
412
                                  di_req_o_A, di_req_o_B, di_req_o_D ) is
413
    begin
414
        if pclk_i'event and pclk_i = '1' then               -- clock at parallel port clock
415
            -- do_transfer_reg -> do_valid_o_reg
416
            do_valid_A <= do_transfer_reg;                  -- the input signal must be at least 2 clocks long
417
            do_valid_B <= do_valid_A;                       -- feed it to a ripple chain of FFDs
418
            do_valid_C <= do_valid_B;
419
            do_valid_D <= do_valid_C;
420
            do_valid_o_reg <= do_valid_next;                -- registered output pulse
421
            --------------------------------
422
            -- di_req_reg -> di_req_o_reg
423
            di_req_o_A <= di_req_reg;                       -- the input signal must be at least 2 clocks long
424
            di_req_o_B <= di_req_o_A;                       -- feed it to a ripple chain of FFDs
425
            di_req_o_C <= di_req_o_B;
426
            di_req_o_D <= di_req_o_C;
427
            di_req_o_reg <= di_req_o_next;                  -- registered output pulse
428
        end if;
429
        -- generate a 2-clocks pulse at the 3rd clock cycle
430
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
431
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
432
    end process out_transfer_proc;
433
    -- parallel load input registers: data register and write enable
434 12 jdoin
    in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
435 5 jdoin
    begin
436
        -- registered data input, input register with clock enable
437
        if pclk_i'event and pclk_i = '1' then
438
            if wren_i = '1' then
439
                di_reg <= di_i;                             -- parallel data input buffer register
440
            end if;
441
        end  if;
442
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
443
        if pclk_i'event and pclk_i = '1' then
444
            if wren_i = '1' then                            -- wren_i is the sync preset for wren
445
                wren <= '1';
446 12 jdoin
            elsif wr_ack_reg = '1' then                     -- wr_ack is the sync reset for wren
447 5 jdoin
                wren <= '0';
448
            end if;
449
        end  if;
450
    end process in_transfer_proc;
451
 
452
    --=============================================================================================
453 7 jdoin
    --  RTL REGISTER PROCESSES
454
    --=============================================================================================
455
    -- fsm state and data registers: synchronous to the spi base reference clock
456
    core_reg_proc : process (sclk_i) is
457
    begin
458
        -- FF registers clocked on rising edge and cleared on sync rst_i
459
        if sclk_i'event and sclk_i = '1' then
460
            if rst_i = '1' then                             -- sync reset
461
                state_reg <= 0;                             -- only provide local reset for the state machine
462
            elsif fsm_ce = '1' then                         -- fsm_ce is clock enable for the fsm
463
                state_reg <= state_next;                    -- state register
464
            end if;
465
        end if;
466 11 jdoin
        -- FF registers clocked synchronous to the fsm state
467 7 jdoin
        if sclk_i'event and sclk_i = '1' then
468
            if fsm_ce = '1' then
469
                sh_reg <= sh_next;                          -- shift register
470 12 jdoin
                ssel_ena_reg <= ssel_ena_next;              -- spi select enable
471 7 jdoin
                do_buffer_reg <= do_buffer_next;            -- registered output data buffer 
472
                do_transfer_reg <= do_transfer_next;        -- output data transferred to buffer
473
                di_req_reg <= di_req_next;                  -- input data request
474 12 jdoin
                wr_ack_reg <= wr_ack_next;                  -- write acknowledge for data load synchronization
475 7 jdoin
            end if;
476
        end if;
477 11 jdoin
        -- FF registers clocked one-half cycle earlier than the fsm state
478 12 jdoin
        if sclk_i'event and sclk_i = '1' then
479
            if sck_ena_ce = '1' then
480
                sck_ena_reg <= sck_ena_next;                -- spi clock enable: look ahead logic
481
            end if;
482
        end if;
483 7 jdoin
    end process core_reg_proc;
484
 
485
    --=============================================================================================
486 5 jdoin
    --  RTL combinatorial LOGIC PROCESSES
487
    --=============================================================================================
488
    -- state and datapath combinatorial logic
489 12 jdoin
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
490
                                do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
491 5 jdoin
    begin
492
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
493 12 jdoin
        ssel_ena_next <= ssel_ena_reg;                                  -- controls the slave select line
494
        sck_ena_next <= sck_ena_reg;                                    -- controls the clock enable of spi sck line
495 5 jdoin
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
496
        do_transfer_next <= do_transfer_reg;                            -- output data flag
497 12 jdoin
        wr_ack_next <= wr_ack_reg;                                      -- write acknowledge
498
        di_req_next <= di_req_reg;                                      -- prefetch data request
499
        state_next <= state_reg;                                        -- next state 
500 5 jdoin
        spi_mosi_o <= sh_reg(N-1);                                      -- shift out tx bit from the MSb
501
        case state_reg is
502
            when (N+1) =>                                               -- this state is to enable SSEL before SCK
503 12 jdoin
                ssel_ena_next <= '1';                                   -- tx in progress: will assert SSEL
504
                sck_ena_next <= '1';                                    -- enable SCK on next cycle (stays off on first SSEL clock cycle)
505
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
506
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
507
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
508 5 jdoin
            when (N) =>                                                 -- deassert 'di_rdy'
509 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
510 5 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
511
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
512 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
513
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
514 5 jdoin
            when (N-1) downto (PREFETCH+3) =>                           -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
515 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
516 5 jdoin
                do_transfer_next <= '0';                                -- reset transfer signal
517
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
518
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
519 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
520
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
521 5 jdoin
            when (PREFETCH+2) downto 2 =>                               -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
522
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
523
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
524
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
525 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
526
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
527 5 jdoin
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if wren
528
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
529
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
530
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
531
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
532
                if wren = '1' then                                      -- load tx register if valid data present at di_i
533
                    state_next <= N;                                    -- next state is top bit of new data
534
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
535 12 jdoin
                    sck_ena_next <= '1';                                -- SCK enabled
536
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
537 5 jdoin
                else
538 12 jdoin
                    sck_ena_next <= '0';                                -- SCK disabled: tx empty, no data to send
539
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
540
                    state_next <= state_reg - 1;                        -- update next state at each sck pulse
541 5 jdoin
                end if;
542
            when 0 =>
543
                di_req_next <= '1';                                     -- will request data if shifter empty
544 12 jdoin
                sck_ena_next <= '0';                                    -- SCK disabled: tx empty, no data to send
545 5 jdoin
                if wren = '1' then                                      -- load tx register if valid data present at di_i
546 12 jdoin
                    ssel_ena_next <= '1';                               -- enable interface SSEL
547 5 jdoin
                    state_next <= N+1;                                  -- start from idle: let one cycle for SSEL settling
548
                    spi_mosi_o <= di_reg(N-1);                          -- special case: shift out first tx bit from the MSb (look ahead)
549
                    sh_next <= di_reg;                                  -- load bits from di_reg into shifter
550 12 jdoin
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
551 5 jdoin
                else
552 12 jdoin
                    ssel_ena_next <= '0';                               -- deassert SSEL: interface is idle
553
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
554 5 jdoin
                    state_next <= 0;                                    -- when idle, keep this state
555
                end if;
556
            when others =>
557
                state_next <= 0;                                        -- state 0 is safe state
558
        end case;
559
    end process core_combi_proc;
560
 
561
    --=============================================================================================
562
    --  OUTPUT LOGIC PROCESSES
563
    --=============================================================================================
564
    -- data output processes
565 12 jdoin
    spi_ssel_o_proc:    spi_ssel_o <= not ssel_ena_reg;                 -- active-low slave select line 
566
    do_o_proc:          do_o <= do_buffer_reg;                          -- parallel data out
567
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- data out valid
568
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- input data request for next cycle
569
    wr_ack_o_proc:      wr_ack_o <= wr_ack_reg;                         -- write acknowledge
570 5 jdoin
    -----------------------------------------------------------------------------------------------
571
    -- SCK out logic: pipeline phase compensation for the SCK line
572
    -----------------------------------------------------------------------------------------------
573 12 jdoin
    -- This is a MUX with an output register. 
574
    -- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore 
575
    -- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. 
576
    spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
577 5 jdoin
    begin
578 12 jdoin
        if sclk_i'event and sclk_i = '1' then
579
            if sck_ena_reg = '1' then
580 5 jdoin
                spi_clk_reg <= spi_clk;                                 -- copy the selected clock polarity
581 12 jdoin
            else
582
                spi_clk_reg <= CPOL;                                    -- when clock disabled, set to idle polarity
583 5 jdoin
            end if;
584
        end if;
585
        spi_sck_o <= spi_clk_reg;                                       -- connect register to output
586
    end process spi_sck_o_gen_proc;
587
 
588
    --=============================================================================================
589
    --  DEBUG LOGIC PROCESSES
590
    --=============================================================================================
591
    -- these signals are useful for verification, and can be deleted or commented-out after debug.
592
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
593 12 jdoin
    state_dbg_proc:     state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
594 5 jdoin
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
595
    wren_o_proc:        wren_o <= wren;
596 12 jdoin
    sh_reg_dbg_proc:    sh_reg_dbg_o <= sh_reg;
597 5 jdoin
    core_clk_o_proc:    core_clk_o <= core_clk;
598
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
599
    core_ce_o_proc:     core_ce_o <= core_ce;
600
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
601 12 jdoin
    sck_ena_o_proc:     sck_ena_o <= sck_ena_reg;
602
    sck_ena_ce_o_proc:  sck_ena_ce_o <= sck_ena_ce;
603 5 jdoin
 
604 10 jdoin
end architecture RTL;
605 5 jdoin
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.