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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master.vhd] - Blame information for rev 14

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2 12 jdoin
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
3 5 jdoin
-- 
4
-- Create Date:     12:18:12 04/25/2011 
5
-- Module Name:     SPI_MASTER - RTL
6
-- Project Name:    SPI MASTER / SLAVE INTERFACE
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-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
9
-- Description: 
10
--
11
--      This block is the SPI master interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
13
--      a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
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--      All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
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--      'sclk_i' clock.
16 13 jdoin
--      For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
17 5 jdoin
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
18
--      clock domains.
19
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
20
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling 
21
--      ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
22
--
23
--      SPI CLOCK GENERATION
24
--      ====================
25
--
26
--      The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference 
27
--      clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the 
28
--      SPI_2X clock, which is 2x the desired SCK frequency. 
29
--      All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
30
--      at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
31
--      by combinatorial clock dividers outputs.
32
--      The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
33
--
34
--      PARALLEL WRITE INTERFACE
35
--      ========================
36
--      The parallel interface has an input port 'di_i' and an output port 'do_o'.
37
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
38
--      that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the 
39
--      next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
40
--      For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
41
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
42
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
43
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
44
--      if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
45
--      enters idle state and deasserts SSEL.
46
--      When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering 
47
--      idle state, if a previously loaded data has already been transferred.
48
--
49
--      PARALLEL WRITE SEQUENCE
50
--      =======================
51
--                         __    __    __    __    __    __    __ 
52
--      pclk_i          __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
53
--                               ___________                        
54
--      di_req_o        ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'pclk_i'
55
--                      ______________ ___________________________...
56
--      di_i            __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
57
--                                                 _______                        
58
--      wren_i          __________________________/       \_______...     -- user strobes 'wren_i' for one cycle of 'pclk_i'
59
--                      
60
--
61
--      PARALLEL READ INTERFACE
62
--      =======================
63
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
64 6 jdoin
--      the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
65
--      The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
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--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
67
--      When the interface is idle, data at the 'do_o' port holds the last word received.
68
--
69
--      PARALLEL READ SEQUENCE
70
--      ======================
71
--                      ______        ______        ______        ______   
72 7 jdoin
--      spi_clk          bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- internal spi 2x base clock
73 5 jdoin
--                      _    __    __    __    __    __    __    __    __  
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--      pclk_i           \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock (may be async to sclk_i)
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--                      _____________ _____________________________________...  -- 1) rx data is transferred to 'do_buffer_reg'
76 6 jdoin
--      do_o            ___old_data__X__________new_data___________________...  --    after last rx bit, at rising 'spi_clk'.
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--                                                   ____________               
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--      do_valid_o      ____________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
79
--                                                                              --    on the 3rd 'pclk_i' rising edge.
80
--
81
--
82
--      The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
83
--      but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
84
--      of the interface, for full duplex operation.
85
--
86
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
87
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
88
--
89
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
90
--                                                                   
91
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
92 6 jdoin
--                                                                   
93 5 jdoin
--      Author(s):      Jonny Doin, jdoin@opencores.org
94 6 jdoin
--                                                                   
95 5 jdoin
--      Copyright (C) 2011 Authors and OPENCORES.ORG
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--      --------------------------------------------
97
--                                                                   
98
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--      removed from the file and that any derivative work contains the original copyright notice and the associated 
100 6 jdoin
--      disclaimer. 
101
--                                                                   
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--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
103
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
104 6 jdoin
--      (at your option) any later version.
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--                                                                   
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--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
108
--      details.
109
--
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--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
111 6 jdoin
--      it from http://www.opencores.org/lgpl.shtml
112 5 jdoin
--                                                                   
113
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
114
--
115
-- 2011/04/28   v0.01.0010  [JD]    shifter implemented as a sequential process. timing problems and async issues in synthesis.
116
-- 2011/05/01   v0.01.0030  [JD]    changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
117
-- 2011/05/05   v0.01.0034  [JD]    added an internal buffer register for rx_data, to allow greater liberty in data load/store.
118
-- 2011/05/08   v0.10.0038  [JD]    increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
119
--                                  logic, based on generics, and do_valid_o signal.
120
-- 2011/05/13   v0.20.0045  [JD]    streamlined signal names, added PREFETCH parameter, added assertions.
121
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
122
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
123
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
124
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
125
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
126
--                                  synthesis LUT overhead in Spartan-6 architecture.
127
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
128 12 jdoin
-- 2011/06/12   v0.97.0079  [JD]    streamlined wr_ack for all cases and eliminated unnecessary register resets.
129 5 jdoin
-- 2011/06/14   v0.97.0083  [JD]    (bug CPHA effect) : redesigned SCK output circuit.
130
--                                  (minor bug) : removed fsm registers from (not rst_i) chip enable.
131
-- 2011/06/15   v0.97.0086  [JD]    removed master MISO input register, to relax MISO data setup time (to get higher speed).
132
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
133
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
134
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
135
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
136 6 jdoin
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
137 10 jdoin
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
138 11 jdoin
-- 2011/07/17   v1.11.0080  [JD]    BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
139
--                                  BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
140
-- 2011/07/18   v1.12.0105  [JD]    CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
141
--                                  for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
142 12 jdoin
-- 2011/07/24   v1.13.0125  [JD]    FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
143
--                                  Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
144
-- 2011/07/29   v1.14.0130  [JD]    Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
145
--                                  for each state, to avoid reported inference problems in some synthesis engines.
146
--                                  Streamlined port names and indentation blocks.
147 13 jdoin
-- 2011/08/01   v1.15.0135  [JD]    Fixed latch inference for spi_mosi_o driver at the fsm.
148
--                                  The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
149 5 jdoin
--
150
-----------------------------------------------------------------------------------------------------------------------
151
--  TODO
152
--  ====
153
--
154
-----------------------------------------------------------------------------------------------------------------------
155
library ieee;
156
use ieee.std_logic_1164.all;
157
use ieee.numeric_std.all;
158 6 jdoin
use ieee.std_logic_unsigned.all;
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160
--================================================================================================================
161 10 jdoin
-- SYNTHESIS CONSIDERATIONS
162
-- ========================
163 5 jdoin
-- There are several output ports that are used to simulate and verify the core operation. 
164
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
165
-- circuitry. 
166
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
167
-- synthesis tool will remove the receive logic from the generated circuitry.
168
--================================================================================================================
169
 
170
entity spi_master is
171
    Generic (
172
        N : positive := 32;                                             -- 32bit serial word length is default
173
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
174
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
175
        PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
176
        SPI_2X_CLK_DIV : positive := 5);                                -- for a 100MHz sclk_i, yields a 10MHz SCK
177
    Port (
178
        sclk_i : in std_logic := 'X';                                   -- high-speed serial interface system clock
179
        pclk_i : in std_logic := 'X';                                   -- high-speed parallel interface system clock
180
        rst_i : in std_logic := 'X';                                    -- reset core
181 7 jdoin
        ---- serial interface ----
182 5 jdoin
        spi_ssel_o : out std_logic;                                     -- spi bus slave select line
183
        spi_sck_o : out std_logic;                                      -- spi bus sck
184
        spi_mosi_o : out std_logic;                                     -- spi bus mosi output
185
        spi_miso_i : in std_logic := 'X';                               -- spi bus spi_miso_i input
186 7 jdoin
        ---- parallel interface ----
187 5 jdoin
        di_req_o : out std_logic;                                       -- preload lookahead data request line
188 6 jdoin
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel data in (clocked on rising spi_clk after last bit)
189 5 jdoin
        wren_i : in std_logic := 'X';                                   -- user data write enable, starts transmission when interface is idle
190 12 jdoin
        wr_ack_o : out std_logic;                                       -- write acknowledge
191 6 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid signal, valid during one spi_clk rising edge.
192
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked on rising spi_clk after last bit)
193 7 jdoin
        --- debug ports: can be removed or left unconnected for the application circuit ---
194 12 jdoin
        sck_ena_o : out std_logic;                                      -- debug: internal sck enable signal
195
        sck_ena_ce_o : out std_logic;                                   -- debug: internal sck clock enable signal
196 5 jdoin
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
197
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
198
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
199 13 jdoin
        state_dbg_o : out std_logic_vector (3 downto 0);                -- debug: internal state register
200 5 jdoin
        core_clk_o : out std_logic;
201
        core_n_clk_o : out std_logic;
202
        core_ce_o : out std_logic;
203
        core_n_ce_o : out std_logic;
204
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
205
    );
206
end spi_master;
207
 
208
--================================================================================================================
209
-- this architecture is a pipelined register-transfer description.
210 6 jdoin
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
211 5 jdoin
--================================================================================================================
212 13 jdoin
architecture rtl of spi_master is
213 6 jdoin
    -- core clocks, generated from 'sclk_i': initialized to differential values
214 11 jdoin
    signal core_clk     : std_logic := '0';     -- continuous core clock, positive logic
215
    signal core_n_clk   : std_logic := '1';     -- continuous core clock, negative logic
216
    signal core_ce      : std_logic := '0';     -- core clock enable, positive logic
217
    signal core_n_ce    : std_logic := '1';     -- core clock enable, negative logic
218 5 jdoin
    -- spi bus clock, generated from the CPOL selected core clock polarity
219 11 jdoin
    signal spi_2x_ce    : std_logic := '1';     -- spi_2x clock enable
220
    signal spi_clk      : std_logic := '0';     -- spi bus output clock
221 12 jdoin
    signal spi_clk_reg  : std_logic;            -- output pipeline delay for spi sck (do NOT global initialize)
222 5 jdoin
    -- core fsm clock enables
223 11 jdoin
    signal fsm_ce       : std_logic := '1';     -- fsm clock enable
224 12 jdoin
    signal sck_ena_ce   : std_logic := '1';     -- SCK clock enable
225 11 jdoin
    signal samp_ce      : std_logic := '1';     -- data sampling clock enable
226 5 jdoin
    --
227
    -- GLOBAL RESET: 
228
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
229
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
230 7 jdoin
    --      especially for the Spartan-6 and newer CLB architectures, where a async reset can
231 5 jdoin
    --      reduce the usability of the slice registers, due to the need to share the control 
232
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
233 7 jdoin
    --      By using GSR for the initialization, and reducing async RESET local init to the bare
234 5 jdoin
    --      essential, the model achieves better LUT/FF packing and CLB usability.
235
    --
236
    -- internal state signals for register and combinatorial stages
237
    signal state_next : natural range N+1 downto 0 := 0;
238
    signal state_reg : natural range N+1 downto 0 := 0;
239
    -- shifter signals for register and combinatorial stages
240 13 jdoin
    signal sh_next : std_logic_vector (N-1 downto 0);
241
    signal sh_reg : std_logic_vector (N-1 downto 0);
242 5 jdoin
    -- input bit sampled buffer
243
    signal rx_bit_reg : std_logic := '0';
244
    -- buffered di_i data signals for register and combinatorial stages
245 13 jdoin
    signal di_reg : std_logic_vector (N-1 downto 0);
246 5 jdoin
    -- internal wren_i stretcher for fsm combinatorial stage
247 13 jdoin
    signal wren : std_logic;
248 12 jdoin
    signal wr_ack_next : std_logic := '0';
249
    signal wr_ack_reg : std_logic := '0';
250 5 jdoin
    -- internal SSEL enable control signals
251 12 jdoin
    signal ssel_ena_next : std_logic := '0';
252
    signal ssel_ena_reg : std_logic := '0';
253 5 jdoin
    -- internal SCK enable control signals
254 12 jdoin
    signal sck_ena_next : std_logic;
255
    signal sck_ena_reg : std_logic;
256 5 jdoin
    -- buffered do_o data signals for register and combinatorial stages
257 13 jdoin
    signal do_buffer_next : std_logic_vector (N-1 downto 0);
258
    signal do_buffer_reg : std_logic_vector (N-1 downto 0);
259 5 jdoin
    -- internal signal to flag transfer to do_buffer_reg
260
    signal do_transfer_next : std_logic := '0';
261
    signal do_transfer_reg : std_logic := '0';
262
    -- internal input data request signal 
263
    signal di_req_next : std_logic := '0';
264
    signal di_req_reg : std_logic := '0';
265
    -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
266
    signal do_valid_A : std_logic := '0';
267
    signal do_valid_B : std_logic := '0';
268
    signal do_valid_C : std_logic := '0';
269
    signal do_valid_D : std_logic := '0';
270
    signal do_valid_next : std_logic := '0';
271
    signal do_valid_o_reg : std_logic := '0';
272
    -- cross-clock di_req_reg -> di_req_o_reg pipeline
273
    signal di_req_o_A : std_logic := '0';
274
    signal di_req_o_B : std_logic := '0';
275
    signal di_req_o_C : std_logic := '0';
276
    signal di_req_o_D : std_logic := '0';
277
    signal di_req_o_next : std_logic := '1';
278
    signal di_req_o_reg : std_logic := '1';
279
begin
280
    --=============================================================================================
281
    --  GENERICS CONSTRAINTS CHECKING
282
    --=============================================================================================
283
    -- minimum word width is 8 bits
284 6 jdoin
    assert N >= 8
285
    report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
286 5 jdoin
    severity FAILURE;
287
    -- minimum prefetch lookahead check
288 6 jdoin
    assert PREFETCH >= 2
289
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
290 5 jdoin
    severity FAILURE;
291
    -- maximum prefetch lookahead check
292 6 jdoin
    assert PREFETCH <= N-5
293
    report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
294 5 jdoin
    severity FAILURE;
295
    -- SPI_2X_CLK_DIV clock divider value must not be zero
296 6 jdoin
    assert SPI_2X_CLK_DIV > 0
297
    report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
298 5 jdoin
    severity FAILURE;
299
 
300
    --=============================================================================================
301
    --  CLOCK GENERATION
302
    --=============================================================================================
303
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
304
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
305
    -- the spi clock generator and the input sampling clock.
306
    -- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock 
307
    -- for the core clocking.
308 14 jdoin
    -- The 2 clock phases are generated by separate and synchronous FFs, and should have only 
309 7 jdoin
    -- differential interconnect delay skew.
310 5 jdoin
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
311
    -- enables are used to control clocking of all internal synchronous circuitry. 
312
    -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, 
313
    -- based on the configuration of CPOL and CPHA.
314
    -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
315 13 jdoin
    -- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
316 5 jdoin
    -----------------------------------------------------------------------------------------------
317 6 jdoin
    -- generate the 2x spi base clock enable from the serial high-speed input clock
318 5 jdoin
    spi_2x_ce_gen_proc: process (sclk_i) is
319
        variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
320
    begin
321
        if sclk_i'event and sclk_i = '1' then
322
            if clk_cnt = SPI_2X_CLK_DIV-1 then
323
                spi_2x_ce <= '1';
324
                clk_cnt := 0;
325
            else
326
                spi_2x_ce <= '0';
327
                clk_cnt := clk_cnt + 1;
328
            end if;
329
        end if;
330
    end process spi_2x_ce_gen_proc;
331
    -----------------------------------------------------------------------------------------------
332 6 jdoin
    -- generate the core antiphase clocks and clock enables from the 2x base CE.
333 5 jdoin
    core_clock_gen_proc : process (sclk_i) is
334
    begin
335
        if sclk_i'event and sclk_i = '1' then
336
            if spi_2x_ce = '1' then
337
                -- generate the 2 antiphase core clocks
338
                core_clk <= core_n_clk;
339
                core_n_clk <= not core_n_clk;
340
                -- generate the 2 phase core clock enables
341
                core_ce <= core_n_clk;
342
                core_n_ce <= not core_n_clk;
343
            else
344
                core_ce <= '0';
345
                core_n_ce <= '0';
346
            end if;
347
        end if;
348
    end process core_clock_gen_proc;
349 12 jdoin
 
350
    --=============================================================================================
351
    --  GENERATE BLOCKS
352
    --=============================================================================================
353 5 jdoin
    -- spi clk generator: generate spi_clk from core_clk depending on CPOL
354 12 jdoin
    spi_sck_cpol_0_proc: if CPOL = '0' generate
355
    begin
356
        spi_clk <= core_clk;            -- for CPOL=0, spi clk has idle LOW
357
    end generate;
358
 
359
    spi_sck_cpol_1_proc: if CPOL = '1' generate
360
    begin
361
        spi_clk <= core_n_clk;          -- for CPOL=1, spi clk has idle HIGH
362
    end generate;
363 5 jdoin
    -----------------------------------------------------------------------------------------------
364
    -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
365
    -- always sample data at the half-cycle of the fsm update cell
366 12 jdoin
    samp_ce_cpha_0_proc: if CPHA = '0' generate
367
    begin
368
        samp_ce <= core_ce;
369
    end generate;
370
 
371
    samp_ce_cpha_1_proc: if CPHA = '1' generate
372
    begin
373
        samp_ce <= core_n_ce;
374
    end generate;
375 5 jdoin
    -----------------------------------------------------------------------------------------------
376 6 jdoin
    -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
377 12 jdoin
    fsm_ce_cpha_0_proc: if CPHA = '0' generate
378
    begin
379
        fsm_ce <= core_n_ce;            -- for CPHA=0, latch registers at rising edge of negative core clock enable
380
    end generate;
381
 
382
    fsm_ce_cpha_1_proc: if CPHA = '1' generate
383
    begin
384
        fsm_ce <= core_ce;              -- for CPHA=1, latch registers at rising edge of positive core clock enable
385
    end generate;
386 13 jdoin
    -----------------------------------------------------------------------------------------------
387
    -- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
388 12 jdoin
    sck_ena_ce <= core_n_ce;            -- for CPHA=1, SCK is advanced one-half cycle
389 11 jdoin
 
390 5 jdoin
    --=============================================================================================
391
    --  REGISTERED INPUTS
392
    --=============================================================================================
393
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
394 10 jdoin
    rx_bit_proc : process (sclk_i, spi_miso_i) is
395 5 jdoin
    begin
396 11 jdoin
        if sclk_i'event and sclk_i = '1' then
397
            if samp_ce = '1' then
398 5 jdoin
                rx_bit_reg <= spi_miso_i;
399 11 jdoin
            end if;
400
        end if;
401 5 jdoin
    end process rx_bit_proc;
402
 
403
    --=============================================================================================
404
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
405
    --=============================================================================================
406
    -- do_valid_o and di_req_o strobe output logic
407
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
408
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
409
    out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
410
                                  do_valid_A, do_valid_B, do_valid_D,
411
                                  di_req_o_A, di_req_o_B, di_req_o_D ) is
412
    begin
413
        if pclk_i'event and pclk_i = '1' then               -- clock at parallel port clock
414
            -- do_transfer_reg -> do_valid_o_reg
415
            do_valid_A <= do_transfer_reg;                  -- the input signal must be at least 2 clocks long
416
            do_valid_B <= do_valid_A;                       -- feed it to a ripple chain of FFDs
417
            do_valid_C <= do_valid_B;
418
            do_valid_D <= do_valid_C;
419
            do_valid_o_reg <= do_valid_next;                -- registered output pulse
420
            --------------------------------
421
            -- di_req_reg -> di_req_o_reg
422
            di_req_o_A <= di_req_reg;                       -- the input signal must be at least 2 clocks long
423
            di_req_o_B <= di_req_o_A;                       -- feed it to a ripple chain of FFDs
424
            di_req_o_C <= di_req_o_B;
425
            di_req_o_D <= di_req_o_C;
426
            di_req_o_reg <= di_req_o_next;                  -- registered output pulse
427
        end if;
428
        -- generate a 2-clocks pulse at the 3rd clock cycle
429
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
430
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
431
    end process out_transfer_proc;
432
    -- parallel load input registers: data register and write enable
433 12 jdoin
    in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
434 5 jdoin
    begin
435
        -- registered data input, input register with clock enable
436
        if pclk_i'event and pclk_i = '1' then
437
            if wren_i = '1' then
438
                di_reg <= di_i;                             -- parallel data input buffer register
439
            end if;
440
        end  if;
441
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
442
        if pclk_i'event and pclk_i = '1' then
443
            if wren_i = '1' then                            -- wren_i is the sync preset for wren
444
                wren <= '1';
445 12 jdoin
            elsif wr_ack_reg = '1' then                     -- wr_ack is the sync reset for wren
446 5 jdoin
                wren <= '0';
447
            end if;
448
        end  if;
449
    end process in_transfer_proc;
450
 
451
    --=============================================================================================
452 13 jdoin
    --  REGISTER TRANSFER PROCESSES
453 7 jdoin
    --=============================================================================================
454
    -- fsm state and data registers: synchronous to the spi base reference clock
455
    core_reg_proc : process (sclk_i) is
456
    begin
457
        -- FF registers clocked on rising edge and cleared on sync rst_i
458
        if sclk_i'event and sclk_i = '1' then
459
            if rst_i = '1' then                             -- sync reset
460
                state_reg <= 0;                             -- only provide local reset for the state machine
461
            elsif fsm_ce = '1' then                         -- fsm_ce is clock enable for the fsm
462
                state_reg <= state_next;                    -- state register
463
            end if;
464
        end if;
465 11 jdoin
        -- FF registers clocked synchronous to the fsm state
466 7 jdoin
        if sclk_i'event and sclk_i = '1' then
467
            if fsm_ce = '1' then
468
                sh_reg <= sh_next;                          -- shift register
469 12 jdoin
                ssel_ena_reg <= ssel_ena_next;              -- spi select enable
470 7 jdoin
                do_buffer_reg <= do_buffer_next;            -- registered output data buffer 
471
                do_transfer_reg <= do_transfer_next;        -- output data transferred to buffer
472
                di_req_reg <= di_req_next;                  -- input data request
473 12 jdoin
                wr_ack_reg <= wr_ack_next;                  -- write acknowledge for data load synchronization
474 7 jdoin
            end if;
475
        end if;
476 11 jdoin
        -- FF registers clocked one-half cycle earlier than the fsm state
477 12 jdoin
        if sclk_i'event and sclk_i = '1' then
478
            if sck_ena_ce = '1' then
479
                sck_ena_reg <= sck_ena_next;                -- spi clock enable: look ahead logic
480
            end if;
481
        end if;
482 7 jdoin
    end process core_reg_proc;
483
 
484
    --=============================================================================================
485 13 jdoin
    --  COMBINATORIAL LOGIC PROCESSES
486 5 jdoin
    --=============================================================================================
487
    -- state and datapath combinatorial logic
488 12 jdoin
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
489
                                do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
490 5 jdoin
    begin
491
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
492 12 jdoin
        ssel_ena_next <= ssel_ena_reg;                                  -- controls the slave select line
493
        sck_ena_next <= sck_ena_reg;                                    -- controls the clock enable of spi sck line
494 5 jdoin
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
495
        do_transfer_next <= do_transfer_reg;                            -- output data flag
496 12 jdoin
        wr_ack_next <= wr_ack_reg;                                      -- write acknowledge
497
        di_req_next <= di_req_reg;                                      -- prefetch data request
498 13 jdoin
        spi_mosi_o <= sh_reg(N-1);                                      -- default to avoid latch inference
499 12 jdoin
        state_next <= state_reg;                                        -- next state 
500 5 jdoin
        case state_reg is
501
            when (N+1) =>                                               -- this state is to enable SSEL before SCK
502 13 jdoin
                -- slave select
503
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
504 12 jdoin
                ssel_ena_next <= '1';                                   -- tx in progress: will assert SSEL
505
                sck_ena_next <= '1';                                    -- enable SCK on next cycle (stays off on first SSEL clock cycle)
506
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
507
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
508
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
509 5 jdoin
            when (N) =>                                                 -- deassert 'di_rdy'
510 13 jdoin
                -- stretch do_valid
511
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
512 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
513 5 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
514
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
515 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
516
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
517 5 jdoin
            when (N-1) downto (PREFETCH+3) =>                           -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
518 13 jdoin
                -- send bit out and shif bit in
519
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
520 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
521 5 jdoin
                do_transfer_next <= '0';                                -- reset transfer signal
522
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
523
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
524 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
525
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
526 5 jdoin
            when (PREFETCH+2) downto 2 =>                               -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
527 13 jdoin
                -- raise data prefetch request
528
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
529 5 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
530
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
531
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
532 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
533
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
534 5 jdoin
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if wren
535 13 jdoin
                -- load next word or end transmission
536
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
537 5 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
538
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
539
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
540
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
541
                if wren = '1' then                                      -- load tx register if valid data present at di_i
542
                    state_next <= N;                                    -- next state is top bit of new data
543
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
544 12 jdoin
                    sck_ena_next <= '1';                                -- SCK enabled
545
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
546 5 jdoin
                else
547 12 jdoin
                    sck_ena_next <= '0';                                -- SCK disabled: tx empty, no data to send
548
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
549
                    state_next <= state_reg - 1;                        -- update next state at each sck pulse
550 5 jdoin
                end if;
551
            when 0 =>
552 13 jdoin
                -- idle state: start and end of transmission
553 5 jdoin
                di_req_next <= '1';                                     -- will request data if shifter empty
554 12 jdoin
                sck_ena_next <= '0';                                    -- SCK disabled: tx empty, no data to send
555 5 jdoin
                if wren = '1' then                                      -- load tx register if valid data present at di_i
556 13 jdoin
                    spi_mosi_o <= di_reg(N-1);                          -- special case: shift out first tx bit from the MSb (look ahead)
557 12 jdoin
                    ssel_ena_next <= '1';                               -- enable interface SSEL
558 5 jdoin
                    state_next <= N+1;                                  -- start from idle: let one cycle for SSEL settling
559
                    sh_next <= di_reg;                                  -- load bits from di_reg into shifter
560 12 jdoin
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
561 5 jdoin
                else
562 13 jdoin
                    spi_mosi_o <= sh_reg(N-1);                          -- shift out tx bit from the MSb
563 12 jdoin
                    ssel_ena_next <= '0';                               -- deassert SSEL: interface is idle
564
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
565 5 jdoin
                    state_next <= 0;                                    -- when idle, keep this state
566
                end if;
567
            when others =>
568
                state_next <= 0;                                        -- state 0 is safe state
569
        end case;
570
    end process core_combi_proc;
571
 
572
    --=============================================================================================
573
    --  OUTPUT LOGIC PROCESSES
574
    --=============================================================================================
575
    -- data output processes
576 12 jdoin
    spi_ssel_o_proc:    spi_ssel_o <= not ssel_ena_reg;                 -- active-low slave select line 
577
    do_o_proc:          do_o <= do_buffer_reg;                          -- parallel data out
578
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- data out valid
579
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- input data request for next cycle
580
    wr_ack_o_proc:      wr_ack_o <= wr_ack_reg;                         -- write acknowledge
581 5 jdoin
    -----------------------------------------------------------------------------------------------
582
    -- SCK out logic: pipeline phase compensation for the SCK line
583
    -----------------------------------------------------------------------------------------------
584 12 jdoin
    -- This is a MUX with an output register. 
585
    -- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore 
586
    -- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. 
587
    spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
588 5 jdoin
    begin
589 12 jdoin
        if sclk_i'event and sclk_i = '1' then
590
            if sck_ena_reg = '1' then
591 5 jdoin
                spi_clk_reg <= spi_clk;                                 -- copy the selected clock polarity
592 12 jdoin
            else
593
                spi_clk_reg <= CPOL;                                    -- when clock disabled, set to idle polarity
594 5 jdoin
            end if;
595
        end if;
596
        spi_sck_o <= spi_clk_reg;                                       -- connect register to output
597
    end process spi_sck_o_gen_proc;
598
 
599
    --=============================================================================================
600
    --  DEBUG LOGIC PROCESSES
601
    --=============================================================================================
602 13 jdoin
    -- these signals are useful for verification, and can be deleted after debug.
603 5 jdoin
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
604 13 jdoin
    state_dbg_proc:     state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
605 5 jdoin
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
606
    wren_o_proc:        wren_o <= wren;
607 12 jdoin
    sh_reg_dbg_proc:    sh_reg_dbg_o <= sh_reg;
608 5 jdoin
    core_clk_o_proc:    core_clk_o <= core_clk;
609
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
610
    core_ce_o_proc:     core_ce_o <= core_ce;
611
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
612 12 jdoin
    sck_ena_o_proc:     sck_ena_o <= sck_ena_reg;
613
    sck_ena_ce_o_proc:  sck_ena_ce_o <= sck_ena_ce;
614 5 jdoin
 
615 13 jdoin
end architecture rtl;
616 5 jdoin
 

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