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1 5 jdoin
-----------------------------------------------------------------------------------------------------------------------
2
-- Author:          Jonny Doin, jdoin@opencores.org
3
-- 
4
-- Create Date:     12:18:12 04/25/2011 
5
-- Module Name:     SPI_MASTER - RTL
6
-- Project Name:    SPI MASTER / SLAVE INTERFACE
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-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
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-- Description: 
10
--
11
--      This block is the SPI master interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
13
--      a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
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--      All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
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--      'sclk_i' clock.
16
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
17
--      clock domains.
18
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
19
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling 
20
--      ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
21
--
22
--      SPI CLOCK GENERATION
23
--      ====================
24
--
25
--      The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference 
26
--      clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the 
27
--      SPI_2X clock, which is 2x the desired SCK frequency. 
28
--      All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
29
--      at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
30
--      by combinatorial clock dividers outputs.
31
--      The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
32
--
33
--      PARALLEL WRITE INTERFACE
34
--      ========================
35
--      The parallel interface has an input port 'di_i' and an output port 'do_o'.
36
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
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--      that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the 
38
--      next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
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--      For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
40
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
41
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
42
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
43
--      if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
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--      enters idle state and deasserts SSEL.
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--      When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering 
46
--      idle state, if a previously loaded data has already been transferred.
47
--
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--      PARALLEL WRITE SEQUENCE
49
--      =======================
50
--                         __    __    __    __    __    __    __ 
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--      pclk_i          __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
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--                               ___________                        
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--      di_req_o        ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'pclk_i'
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--                      ______________ ___________________________...
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--      di_i            __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
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--                                                 _______                        
57
--      wren_i          __________________________/       \_______...     -- user strobes 'wren_i' for one cycle of 'pclk_i'
58
--                      
59
--
60
--      PARALLEL READ INTERFACE
61
--      =======================
62
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
63 6 jdoin
--      the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
64
--      The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
65 5 jdoin
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
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--      When the interface is idle, data at the 'do_o' port holds the last word received.
67
--
68
--      PARALLEL READ SEQUENCE
69
--      ======================
70
--                      ______        ______        ______        ______   
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--      spi_clk          bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- internal spi 2x base clock
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--                      _    __    __    __    __    __    __    __    __  
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--      pclk_i           \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock (may be async to sclk_i)
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--                      _____________ _____________________________________...  -- 1) rx data is transferred to 'do_buffer_reg'
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--      do_o            ___old_data__X__________new_data___________________...  --    after last rx bit, at rising 'spi_clk'.
76 5 jdoin
--                                                   ____________               
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--      do_valid_o      ____________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
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--                                                                              --    on the 3rd 'pclk_i' rising edge.
79
--
80
--
81
--      The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
82
--      but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
83
--      of the interface, for full duplex operation.
84
--
85
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
86
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
87
--
88
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
89
--                                                                   
90
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
91 6 jdoin
--                                                                   
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--      Author(s):      Jonny Doin, jdoin@opencores.org
93 6 jdoin
--                                                                   
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--      Copyright (C) 2011 Authors and OPENCORES.ORG
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--      --------------------------------------------
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--                                                                   
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--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--      removed from the file and that any derivative work contains the original copyright notice and the associated 
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--      disclaimer. 
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--                                                                   
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--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
102
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
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--      (at your option) any later version.
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--                                                                   
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--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
107
--      details.
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--
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--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
110 6 jdoin
--      it from http://www.opencores.org/lgpl.shtml
111 5 jdoin
--                                                                   
112
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
113
--
114
-- 2011/04/28   v0.01.0010  [JD]    shifter implemented as a sequential process. timing problems and async issues in synthesis.
115
-- 2011/05/01   v0.01.0030  [JD]    changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
116
-- 2011/05/05   v0.01.0034  [JD]    added an internal buffer register for rx_data, to allow greater liberty in data load/store.
117
-- 2011/05/08   v0.10.0038  [JD]    increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
118
--                                  logic, based on generics, and do_valid_o signal.
119
-- 2011/05/13   v0.20.0045  [JD]    streamlined signal names, added PREFETCH parameter, added assertions.
120
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
121
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
122
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
123
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
124
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
125
--                                  synthesis LUT overhead in Spartan-6 architecture.
126
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
127
-- 2011/06/12   v0.97.0079  [JD]    streamlined wren_ack for all cases and eliminated unnecessary register resets.
128
-- 2011/06/14   v0.97.0083  [JD]    (bug CPHA effect) : redesigned SCK output circuit.
129
--                                  (minor bug) : removed fsm registers from (not rst_i) chip enable.
130
-- 2011/06/15   v0.97.0086  [JD]    removed master MISO input register, to relax MISO data setup time (to get higher speed).
131
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
132
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
133
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
134
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
135 6 jdoin
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
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--
137
-----------------------------------------------------------------------------------------------------------------------
138
--  TODO
139
--  ====
140
--      > verify the receive interface in silicon, and determine the top usable frequency.
141
--
142
-----------------------------------------------------------------------------------------------------------------------
143
library ieee;
144
use ieee.std_logic_1164.all;
145
use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
147 5 jdoin
 
148
--================================================================================================================
149
-- There are several output ports that are used to simulate and verify the core operation. 
150
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
151
-- circuitry. 
152
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
153
-- synthesis tool will remove the receive logic from the generated circuitry.
154
--================================================================================================================
155
 
156
entity spi_master is
157
    Generic (
158
        N : positive := 32;                                             -- 32bit serial word length is default
159
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
160
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
161
        PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
162
        SPI_2X_CLK_DIV : positive := 5);                                -- for a 100MHz sclk_i, yields a 10MHz SCK
163
    Port (
164
        sclk_i : in std_logic := 'X';                                   -- high-speed serial interface system clock
165
        pclk_i : in std_logic := 'X';                                   -- high-speed parallel interface system clock
166
        rst_i : in std_logic := 'X';                                    -- reset core
167 7 jdoin
        ---- serial interface ----
168 5 jdoin
        spi_ssel_o : out std_logic;                                     -- spi bus slave select line
169
        spi_sck_o : out std_logic;                                      -- spi bus sck
170
        spi_mosi_o : out std_logic;                                     -- spi bus mosi output
171
        spi_miso_i : in std_logic := 'X';                               -- spi bus spi_miso_i input
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        ---- parallel interface ----
173 5 jdoin
        di_req_o : out std_logic;                                       -- preload lookahead data request line
174 6 jdoin
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel data in (clocked on rising spi_clk after last bit)
175 5 jdoin
        wren_i : in std_logic := 'X';                                   -- user data write enable, starts transmission when interface is idle
176 6 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid signal, valid during one spi_clk rising edge.
177
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked on rising spi_clk after last bit)
178 7 jdoin
        --- debug ports: can be removed or left unconnected for the application circuit ---
179 5 jdoin
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
180
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
181
        wren_ack_o : out std_logic;                                     -- debug: wren ack from state machine
182
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
183
        state_dbg_o : out std_logic_vector (5 downto 0);                -- debug: internal state register
184
        core_clk_o : out std_logic;
185
        core_n_clk_o : out std_logic;
186
        core_ce_o : out std_logic;
187
        core_n_ce_o : out std_logic;
188
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
189
    );
190
end spi_master;
191
 
192
--================================================================================================================
193
-- this architecture is a pipelined register-transfer description.
194 6 jdoin
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
195 5 jdoin
--================================================================================================================
196
architecture rtl of spi_master is
197 6 jdoin
    -- core clocks, generated from 'sclk_i': initialized to differential values
198 5 jdoin
    signal core_clk : std_logic := '0';     -- continuous core clock, positive logic
199
    signal core_n_clk : std_logic := '1';   -- continuous core clock, negative logic
200
    signal core_ce : std_logic := '0';      -- core clock enable, positive logic
201
    signal core_n_ce : std_logic := '1';    -- core clock enable, negative logic
202
    -- spi bus clock, generated from the CPOL selected core clock polarity
203
    signal spi_2x_ce : std_logic := '1';    -- spi_2x clock enable
204
    signal spi_clk : std_logic := '0';      -- spi bus output clock
205
    signal spi_clk_reg : std_logic := '0';  -- output pipeline delay for spi sck
206
    -- core fsm clock enables
207
    signal fsm_ce : std_logic := '1';       -- fsm clock enable
208
    signal samp_ce : std_logic := '1';      -- data sampling clock enable
209
    --
210
    -- GLOBAL RESET: 
211
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
212
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
213 7 jdoin
    --      especially for the Spartan-6 and newer CLB architectures, where a async reset can
214 5 jdoin
    --      reduce the usability of the slice registers, due to the need to share the control 
215
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
216 7 jdoin
    --      By using GSR for the initialization, and reducing async RESET local init to the bare
217 5 jdoin
    --      essential, the model achieves better LUT/FF packing and CLB usability.
218
    --
219
    -- internal state signals for register and combinatorial stages
220
    signal state_next : natural range N+1 downto 0 := 0;
221
    signal state_reg : natural range N+1 downto 0 := 0;
222
    -- shifter signals for register and combinatorial stages
223
    signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
224
    signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
225
    -- input bit sampled buffer
226
    signal rx_bit_reg : std_logic := '0';
227
    -- buffered di_i data signals for register and combinatorial stages
228
    signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
229
    -- internal wren_i stretcher for fsm combinatorial stage
230
    signal wren : std_logic := '0';
231
    signal wren_ack_next : std_logic := '0';
232
    signal wren_ack_reg : std_logic := '0';
233
    -- internal SSEL enable control signals
234
    signal ena_ssel_next : std_logic := '0';
235
    signal ena_ssel_reg : std_logic := '0';
236
    -- internal SCK enable control signals
237
    signal ena_sck_next : std_logic := '0';
238
    signal ena_sck_reg : std_logic := '0';
239
    -- buffered do_o data signals for register and combinatorial stages
240
    signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
241
    signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
242
    -- internal signal to flag transfer to do_buffer_reg
243
    signal do_transfer_next : std_logic := '0';
244
    signal do_transfer_reg : std_logic := '0';
245
    -- internal input data request signal 
246
    signal di_req_next : std_logic := '0';
247
    signal di_req_reg : std_logic := '0';
248
    -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
249
    signal do_valid_A : std_logic := '0';
250
    signal do_valid_B : std_logic := '0';
251
    signal do_valid_C : std_logic := '0';
252
    signal do_valid_D : std_logic := '0';
253
    signal do_valid_next : std_logic := '0';
254
    signal do_valid_o_reg : std_logic := '0';
255
    -- cross-clock di_req_reg -> di_req_o_reg pipeline
256
    signal di_req_o_A : std_logic := '0';
257
    signal di_req_o_B : std_logic := '0';
258
    signal di_req_o_C : std_logic := '0';
259
    signal di_req_o_D : std_logic := '0';
260
    signal di_req_o_next : std_logic := '1';
261
    signal di_req_o_reg : std_logic := '1';
262
begin
263
    --=============================================================================================
264
    --  GENERICS CONSTRAINTS CHECKING
265
    --=============================================================================================
266
    -- minimum word width is 8 bits
267 6 jdoin
    assert N >= 8
268
    report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
269 5 jdoin
    severity FAILURE;
270
    -- minimum prefetch lookahead check
271 6 jdoin
    assert PREFETCH >= 2
272
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
273 5 jdoin
    severity FAILURE;
274
    -- maximum prefetch lookahead check
275 6 jdoin
    assert PREFETCH <= N-5
276
    report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
277 5 jdoin
    severity FAILURE;
278
    -- SPI_2X_CLK_DIV clock divider value must not be zero
279 6 jdoin
    assert SPI_2X_CLK_DIV > 0
280
    report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
281 5 jdoin
    severity FAILURE;
282
 
283
    --=============================================================================================
284
    --  CLOCK GENERATION
285
    --=============================================================================================
286
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
287
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
288
    -- the spi clock generator and the input sampling clock.
289
    -- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock 
290
    -- for the core clocking.
291
    -- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only 
292 7 jdoin
    -- differential interconnect delay skew.
293 5 jdoin
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
294
    -- enables are used to control clocking of all internal synchronous circuitry. 
295
    -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, 
296
    -- based on the configuration of CPOL and CPHA.
297
    -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
298
    -- modes, by a single high-speed global clock, preserving clock resources.
299
    -----------------------------------------------------------------------------------------------
300 6 jdoin
    -- generate the 2x spi base clock enable from the serial high-speed input clock
301 5 jdoin
    spi_2x_ce_gen_proc: process (sclk_i) is
302
        variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
303
    begin
304
        if sclk_i'event and sclk_i = '1' then
305
            if clk_cnt = SPI_2X_CLK_DIV-1 then
306
                spi_2x_ce <= '1';
307
                clk_cnt := 0;
308
            else
309
                spi_2x_ce <= '0';
310
                clk_cnt := clk_cnt + 1;
311
            end if;
312
        end if;
313
    end process spi_2x_ce_gen_proc;
314
    -----------------------------------------------------------------------------------------------
315 6 jdoin
    -- generate the core antiphase clocks and clock enables from the 2x base CE.
316 5 jdoin
    core_clock_gen_proc : process (sclk_i) is
317
    begin
318
        if sclk_i'event and sclk_i = '1' then
319
            if spi_2x_ce = '1' then
320
                -- generate the 2 antiphase core clocks
321
                core_clk <= core_n_clk;
322
                core_n_clk <= not core_n_clk;
323
                -- generate the 2 phase core clock enables
324
                core_ce <= core_n_clk;
325
                core_n_ce <= not core_n_clk;
326
            else
327
                core_ce <= '0';
328
                core_n_ce <= '0';
329
            end if;
330
        end if;
331
    end process core_clock_gen_proc;
332
    -----------------------------------------------------------------------------------------------
333
    -- spi clk generator: generate spi_clk from core_clk depending on CPOL
334
    spi_sck_cpol_0_proc :
335
        if CPOL = '0' generate
336
        begin
337
            spi_clk <= core_clk;            -- for CPOL=0, spi clk has idle LOW
338
        end generate;
339
    spi_sck_cpol_1_proc :
340
        if CPOL = '1' generate
341
        begin
342
            spi_clk <= core_n_clk;          -- for CPOL=1, spi clk has idle HIGH
343
        end generate;
344
    -----------------------------------------------------------------------------------------------
345
    -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
346
    -- always sample data at the half-cycle of the fsm update cell
347
    samp_ce_cpha_0_proc :
348
        if CPHA = '0' generate
349
        begin
350
            samp_ce <= core_ce;
351
        end generate;
352
    samp_ce_cpha_1_proc :
353
        if CPHA = '1' generate
354
        begin
355
            samp_ce <= core_n_ce;
356
        end generate;
357
    -----------------------------------------------------------------------------------------------
358 6 jdoin
    -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
359 5 jdoin
    fsm_ce_cpha_0_proc :
360
        if CPHA = '0' generate
361
        begin
362
            fsm_ce <= core_n_ce;            -- for CPHA=0, latch registers at rising edge of negative core clock enable
363
        end generate;
364
    fsm_ce_cpha_1_proc :
365
        if CPHA = '1' generate
366
        begin
367
            fsm_ce <= core_ce;              -- for CPHA=1, latch registers at rising edge of positive core clock enable
368
        end generate;
369
 
370
    --=============================================================================================
371
    --  REGISTERED INPUTS
372
    --=============================================================================================
373
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
374
    --
375
    --  ATTENTION:  REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO 
376
    --              REDUCED DEMAND ON MISO SETUP TIME. 
377
    --
378
    rx_bit_proc : process (sclk_i) is
379
    begin
380
        if sclk_i'event and sclk_i = '1' then
381
            if samp_ce = '1' then
382
                rx_bit_reg <= spi_miso_i;
383
            end if;
384
        end if;
385
    end process rx_bit_proc;
386
 
387
    --=============================================================================================
388
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
389
    --=============================================================================================
390
    -- do_valid_o and di_req_o strobe output logic
391
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
392
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
393
    out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
394
                                  do_valid_A, do_valid_B, do_valid_D,
395
                                  di_req_o_A, di_req_o_B, di_req_o_D ) is
396
    begin
397
        if pclk_i'event and pclk_i = '1' then               -- clock at parallel port clock
398
            -- do_transfer_reg -> do_valid_o_reg
399
            do_valid_A <= do_transfer_reg;                  -- the input signal must be at least 2 clocks long
400
            do_valid_B <= do_valid_A;                       -- feed it to a ripple chain of FFDs
401
            do_valid_C <= do_valid_B;
402
            do_valid_D <= do_valid_C;
403
            do_valid_o_reg <= do_valid_next;                -- registered output pulse
404
            --------------------------------
405
            -- di_req_reg -> di_req_o_reg
406
            di_req_o_A <= di_req_reg;                       -- the input signal must be at least 2 clocks long
407
            di_req_o_B <= di_req_o_A;                       -- feed it to a ripple chain of FFDs
408
            di_req_o_C <= di_req_o_B;
409
            di_req_o_D <= di_req_o_C;
410
            di_req_o_reg <= di_req_o_next;                  -- registered output pulse
411
        end if;
412
        -- generate a 2-clocks pulse at the 3rd clock cycle
413
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
414
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
415
    end process out_transfer_proc;
416
    -- parallel load input registers: data register and write enable
417
    in_transfer_proc: process ( pclk_i, wren_i, wren_ack_reg ) is
418
    begin
419
        -- registered data input, input register with clock enable
420
        if pclk_i'event and pclk_i = '1' then
421
            if wren_i = '1' then
422
                di_reg <= di_i;                             -- parallel data input buffer register
423
            end if;
424
        end  if;
425
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
426
        if pclk_i'event and pclk_i = '1' then
427
            if wren_i = '1' then                            -- wren_i is the sync preset for wren
428
                wren <= '1';
429
            elsif wren_ack_reg = '1' then                   -- wren_ack is the sync reset for wren
430
                wren <= '0';
431
            end if;
432
        end  if;
433
    end process in_transfer_proc;
434
 
435
    --=============================================================================================
436 7 jdoin
    --  RTL REGISTER PROCESSES
437
    --=============================================================================================
438
    -- fsm state and data registers: synchronous to the spi base reference clock
439
    core_reg_proc : process (sclk_i) is
440
    begin
441
        -- FF registers clocked on rising edge and cleared on sync rst_i
442
        if sclk_i'event and sclk_i = '1' then
443
            if rst_i = '1' then                             -- sync reset
444
                state_reg <= 0;                             -- only provide local reset for the state machine
445
            elsif fsm_ce = '1' then                         -- fsm_ce is clock enable for the fsm
446
                state_reg <= state_next;                    -- state register
447
            end if;
448
        end if;
449
        -- FF registers clocked on rising edge
450
        if sclk_i'event and sclk_i = '1' then
451
            if fsm_ce = '1' then
452
                sh_reg <= sh_next;                          -- shift register
453
                ena_ssel_reg <= ena_ssel_next;              -- spi select enable
454
                ena_sck_reg <= ena_sck_next;                -- spi clock enable
455
                do_buffer_reg <= do_buffer_next;            -- registered output data buffer 
456
                do_transfer_reg <= do_transfer_next;        -- output data transferred to buffer
457
                di_req_reg <= di_req_next;                  -- input data request
458
                wren_ack_reg <= wren_ack_next;              -- wren ack for data load synchronization
459
            end if;
460
        end if;
461
    end process core_reg_proc;
462
 
463
    --=============================================================================================
464 5 jdoin
    --  RTL combinatorial LOGIC PROCESSES
465
    --=============================================================================================
466
    -- state and datapath combinatorial logic
467
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg,
468
                                do_transfer_reg, di_reg, wren ) is
469
    begin
470
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
471
        ena_ssel_next <= ena_ssel_reg;                                  -- controls the slave select line
472
        ena_sck_next <= ena_sck_reg;                                    -- controls the clock enable of spi sck line
473
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
474
        do_transfer_next <= do_transfer_reg;                            -- output data flag
475
        wren_ack_next <= '0';                                           -- remove data load ack for all but the load stages
476
        di_req_next <= '0';                                             -- prefetch data request: deassert when shifting data
477
        spi_mosi_o <= sh_reg(N-1);                                      -- shift out tx bit from the MSb
478
        state_next <= state_reg - 1;                                    -- update next state at each sck pulse
479
        case state_reg is
480
            when (N+1) =>                                               -- this state is to enable SSEL before SCK
481
                ena_ssel_next <= '1';                                   -- tx in progress: will assert SSEL
482
                ena_sck_next <= '1';                                    -- enable SCK on next cycle (stays off on first SSEL clock cycle)
483
            when (N) =>                                                 -- deassert 'di_rdy'
484
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
485
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
486
            when (N-1) downto (PREFETCH+3) =>                           -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
487
                do_transfer_next <= '0';                                -- reset transfer signal
488
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
489
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
490
            when (PREFETCH+2) downto 2 =>                               -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
491
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
492
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
493
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
494
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if wren
495
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
496
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
497
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
498
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
499
                if wren = '1' then                                      -- load tx register if valid data present at di_i
500
                    state_next <= N;                                    -- next state is top bit of new data
501
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
502
                    ena_sck_next <= '1';                                -- SCK enabled
503
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
504
                else
505
                    ena_sck_next <= '0';                                -- SCK disabled: tx empty, no data to send
506
                end if;
507
            when 0 =>
508
                di_req_next <= '1';                                     -- will request data if shifter empty
509
                ena_sck_next <= '0';                                    -- SCK disabled: tx empty, no data to send
510
                if wren = '1' then                                      -- load tx register if valid data present at di_i
511
                    ena_ssel_next <= '1';                               -- enable interface SSEL
512
                    state_next <= N+1;                                  -- start from idle: let one cycle for SSEL settling
513
                    spi_mosi_o <= di_reg(N-1);                          -- special case: shift out first tx bit from the MSb (look ahead)
514
                    sh_next <= di_reg;                                  -- load bits from di_reg into shifter
515
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
516
                else
517
                    ena_ssel_next <= '0';                               -- deassert SSEL: interface is idle
518
                    state_next <= 0;                                    -- when idle, keep this state
519
                end if;
520
            when others =>
521
                state_next <= 0;                                        -- state 0 is safe state
522
        end case;
523
    end process core_combi_proc;
524
 
525
    --=============================================================================================
526
    --  OUTPUT LOGIC PROCESSES
527
    --=============================================================================================
528
    -- data output processes
529
    spi_ssel_o_proc:    spi_ssel_o <= not ena_ssel_reg;                 -- drive active-low slave select line 
530
    do_o_proc :         do_o <= do_buffer_reg;                          -- do_o always available
531
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- copy registered do_valid_o to output
532
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- copy registered di_req_o to output
533
    -----------------------------------------------------------------------------------------------
534
    -- SCK out logic: pipeline phase compensation for the SCK line
535
    -----------------------------------------------------------------------------------------------
536
    -- This is a MUX with an output register. The register gives us a pipeline delay for the SCK line,
537
    -- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay.
538
    spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is
539
    begin
540
        if sclk_i'event and sclk_i = '1' then
541
            if ena_sck_reg = '1' then
542
                spi_clk_reg <= spi_clk;                                 -- copy the selected clock polarity
543
            else
544
                spi_clk_reg <= CPOL;                                    -- when clock disabled, set to idle polarity
545
            end if;
546
        end if;
547
        spi_sck_o <= spi_clk_reg;                                       -- connect register to output
548
    end process spi_sck_o_gen_proc;
549
 
550
    --=============================================================================================
551
    --  DEBUG LOGIC PROCESSES
552
    --=============================================================================================
553
    -- these signals are useful for verification, and can be deleted or commented-out after debug.
554
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
555
    state_dbg_proc:     state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
556
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
557
    wren_o_proc:        wren_o <= wren;
558
    wren_ack_o_proc:    wren_ack_o <= wren_ack_reg;
559
    sh_reg_dbg_proc:    sh_reg_dbg_o <= sh_reg;                         -- export sh_reg to debug
560
    core_clk_o_proc:    core_clk_o <= core_clk;
561
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
562
    core_ce_o_proc:     core_ce_o <= core_ce;
563
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
564
 
565
end architecture rtl;
566
 

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