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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.par] - Blame information for rev 24

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Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
 
DEVELOP-W7::  Thu Sep 01 13:07:30 2011
 
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
 
 
Constraints file: spi_master_atlys_top.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
   "spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
 
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".
 
Device speed data version:  "PRODUCTION 1.18 2011-04-07".
 
 
 
Device Utilization Summary:
 
Slice Logic Utilization:
  Number of Slice Registers:                   210 out of  54,576    1%
    Number used as Flip Flops:                 210
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        143 out of  27,288    1%
    Number used as logic:                      129 out of  27,288    1%
      Number using O6 output only:              79
      Number using O5 output only:              15
      Number using O5 and O6:                   35
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:     10
      Number with same-slice register load:      8
      Number with same-slice carry load:         2
      Number with other load:                    0
 
Slice Logic Distribution:
  Number of occupied Slices:                    91 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          231
    Number with an unused Flip Flop:            46 out of     231   19%
    Number with an unused LUT:                  88 out of     231   38%
    Number of fully used LUT-FF pairs:          97 out of     231   41%
    Number of slice register sites lost
      to control set restrictions:               0 out of  54,576    0%
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
  Number of bonded IOBs:                        64 out of     218   29%
    Number of LOCed IOBs:                       46 out of      64   71%
 
Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
    Number used as BUFGs:                        3
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
 
 
Overall effort level (-ol):   High
Router effort level (-rl):    High
 
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
 
Starting initial Timing Analysis.  REAL time: 4 secs
Finished initial Timing Analysis.  REAL time: 4 secs
 
Starting Router
 
 
Phase  1  : 923 unrouted;      REAL time: 5 secs
 
Phase  2  : 776 unrouted;      REAL time: 6 secs
 
Phase  3  : 205 unrouted;      REAL time: 7 secs
 
Phase  4  : 205 unrouted; (Par is working to improve performance)     REAL time: 8 secs
 
Updating file: spi_master_atlys_top.ncd with current fully routed design.
 
Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
 
Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
Total REAL time to Router completion: 9 secs
Total CPU time to Router completion: 9 secs
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net pcl | SETUP       |         N/A|     5.916ns|     N/A|           0
  k_i_BUFGP                                 | HOLD        |     0.264ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net Ins | SETUP       |         N/A|     3.959ns|     N/A|           0
  t_spi_master_port/spi_clk_reg_BUFG        | HOLD        |     0.439ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net scl | SETUP       |         N/A|     3.391ns|     N/A|           0
  k_i_BUFGP                                 | HOLD        |     0.513ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
   constraint is not analyzed due to the following: No paths covered by this
   constraint; Other constraints intersect with this constraint; or This
   constraint was disabled by a Path Tracing Control. Please run the Timespec
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 9 secs
Total CPU time to PAR completion: 9 secs
 
Peak Memory Usage:  268 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2
 
Writing design to file spi_master_atlys_top.ncd
 
 
 
PAR done!

Line No.	Rev	Author	Line
1	20	jdoin	`Release 13.1 par O.40d (nt)`
2			`Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.`
3
4	24	jdoin	`DEVELOP-W7:: Thu Sep 01 13:07:30 2011`
5	20	jdoin
6			`par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd`
7			`spi_master_atlys_top.ncd spi_master_atlys_top.pcf`
8
9
10			`Constraints file: spi_master_atlys_top.pcf.`
11			`Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.`
12			`"spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2`
13
14			`Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)`
15			`Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)`
16
17			`INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par`
18			`-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all`
19			`internal clocks in this design. Because there are not defined timing requirements, a timing score will not be`
20			`reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.`
21			`Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".`
22
23			`Device speed data version: "PRODUCTION 1.18 2011-04-07".`
24
25
26
27			`Device Utilization Summary:`
28
29			`Slice Logic Utilization:`
30	24	jdoin	`Number of Slice Registers: 210 out of 54,576 1%`
31			`Number used as Flip Flops: 210`
32	20	jdoin	`Number used as Latches: 0`
33			`Number used as Latch-thrus: 0`
34			`Number used as AND/OR logics: 0`
35	24	jdoin	`Number of Slice LUTs: 143 out of 27,288 1%`
36			`Number used as logic: 129 out of 27,288 1%`
37			`Number using O6 output only: 79`
38			`Number using O5 output only: 15`
39			`Number using O5 and O6: 35`
40	20	jdoin	`Number used as ROM: 0`
41			`Number used as Memory: 4 out of 6,408 1%`
42			`Number used as Dual Port RAM: 0`
43			`Number used as Single Port RAM: 0`
44			`Number used as Shift Register: 4`
45			`Number using O6 output only: 4`
46			`Number using O5 output only: 0`
47			`Number using O5 and O6: 0`
48	24	jdoin	`Number used exclusively as route-thrus: 10`
49			`Number with same-slice register load: 8`
50	20	jdoin	`Number with same-slice carry load: 2`
51			`Number with other load: 0`
52
53			`Slice Logic Distribution:`
54	24	jdoin	`Number of occupied Slices: 91 out of 6,822 1%`
55			`Number of LUT Flip Flop pairs used: 231`
56			`Number with an unused Flip Flop: 46 out of 231 19%`
57			`Number with an unused LUT: 88 out of 231 38%`
58			`Number of fully used LUT-FF pairs: 97 out of 231 41%`
59	20	jdoin	`Number of slice register sites lost`
60			`to control set restrictions: 0 out of 54,576 0%`
61
62			`A LUT Flip Flop pair for this architecture represents one LUT paired with`
63			`one Flip Flop within a slice. A control set is a unique combination of`
64			`clock, reset, set, and enable signals for a registered element.`
65			`The Slice Logic Distribution report is not meaningful if the design is`
66			`over-mapped for a non-slice resource or if Placement fails.`
67
68			`IO Utilization:`
69	24	jdoin	`Number of bonded IOBs: 64 out of 218 29%`
70			`Number of LOCed IOBs: 46 out of 64 71%`
71	20	jdoin
72			`Specific Feature Utilization:`
73			`Number of RAMB16BWERs: 0 out of 116 0%`
74			`Number of RAMB8BWERs: 0 out of 232 0%`
75			`Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%`
76			`Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%`
77	24	jdoin	`Number of BUFG/BUFGMUXs: 3 out of 16 18%`
78			`Number used as BUFGs: 3`
79	20	jdoin	`Number used as BUFGMUX: 0`
80			`Number of DCM/DCM_CLKGENs: 0 out of 8 0%`
81			`Number of ILOGIC2/ISERDES2s: 0 out of 376 0%`
82			`Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%`
83			`Number of OLOGIC2/OSERDES2s: 0 out of 376 0%`
84			`Number of BSCANs: 0 out of 4 0%`
85			`Number of BUFHs: 0 out of 256 0%`
86			`Number of BUFPLLs: 0 out of 8 0%`
87			`Number of BUFPLL_MCBs: 0 out of 4 0%`
88			`Number of DSP48A1s: 0 out of 58 0%`
89			`Number of ICAPs: 0 out of 1 0%`
90			`Number of MCBs: 0 out of 2 0%`
91			`Number of PCILOGICSEs: 0 out of 2 0%`
92			`Number of PLL_ADVs: 0 out of 4 0%`
93			`Number of PMVs: 0 out of 1 0%`
94			`Number of STARTUPs: 0 out of 1 0%`
95			`Number of SUSPEND_SYNCs: 0 out of 1 0%`
96
97
98			`Overall effort level (-ol): High`
99			`Router effort level (-rl): High`
100
101			`WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.`
102
103			`Starting initial Timing Analysis. REAL time: 4 secs`
104			`Finished initial Timing Analysis. REAL time: 4 secs`
105
106			`Starting Router`
107
108
109	24	jdoin	`Phase 1 : 923 unrouted; REAL time: 5 secs`
110	20	jdoin
111	24	jdoin	`Phase 2 : 776 unrouted; REAL time: 6 secs`
112	20	jdoin
113	24	jdoin	`Phase 3 : 205 unrouted; REAL time: 7 secs`
114	20	jdoin
115	24	jdoin	`Phase 4 : 205 unrouted; (Par is working to improve performance) REAL time: 8 secs`
116	20	jdoin
117			`Updating file: spi_master_atlys_top.ncd with current fully routed design.`
118
119			`Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
120
121			`Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
122
123			`Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
124
125			`Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
126
127			`Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
128
129			`Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs`
130			`Total REAL time to Router completion: 9 secs`
131			`Total CPU time to Router completion: 9 secs`
132
133			`Partition Implementation Status`
134			`-------------------------------`
135
136			`No Partitions were found in this design.`
137
138			`-------------------------------`
139
140			`Generating "PAR" statistics.`
141			`INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.`
142			`Timing Score: 0 (Setup: 0, Hold: 0)`
143
144			`Asterisk (*) preceding a constraint indicates it was not met.`
145			`This may be due to a setup or hold violation.`
146
147			`----------------------------------------------------------------------------------------------------------`
148			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
149			`\| \| Slack \| Achievable \| Errors \| Score`
150			`----------------------------------------------------------------------------------------------------------`
151	24	jdoin	`Autotimespec constraint for clock net pcl \| SETUP \| N/A\| 5.916ns\| N/A\| 0`
152			`k_i_BUFGP \| HOLD \| 0.264ns\| \| 0\| 0`
153	20	jdoin	`----------------------------------------------------------------------------------------------------------`
154	24	jdoin	`Autotimespec constraint for clock net Ins \| SETUP \| N/A\| 3.959ns\| N/A\| 0`
155			`t_spi_master_port/spi_clk_reg_BUFG \| HOLD \| 0.439ns\| \| 0\| 0`
156	20	jdoin	`----------------------------------------------------------------------------------------------------------`
157	24	jdoin	`Autotimespec constraint for clock net scl \| SETUP \| N/A\| 3.391ns\| N/A\| 0`
158			`k_i_BUFGP \| HOLD \| 0.513ns\| \| 0\| 0`
159			`----------------------------------------------------------------------------------------------------------`
160	20	jdoin
161
162			`All constraints were met.`
163			`INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the`
164			`constraint is not analyzed due to the following: No paths covered by this`
165			`constraint; Other constraints intersect with this constraint; or This`
166			`constraint was disabled by a Path Tracing Control. Please run the Timespec`
167			`Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.`
168
169
170			`Generating Pad Report.`
171
172			`All signals are completely routed.`
173
174	24	jdoin	`Total REAL time to PAR completion: 9 secs`
175			`Total CPU time to PAR completion: 9 secs`
176	20	jdoin
177	24	jdoin	`Peak Memory Usage: 268 MB`
178	20	jdoin
179			`Placer: Placement generated during map.`
180			`Routing: Completed - No errors found.`
181
182			`Number of error messages: 0`
183			`Number of warning messages: 1`
184			`Number of info messages: 2`
185
186			`Writing design to file spi_master_atlys_top.ncd`
187
188
189
190			`PAR done!`

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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.par] - Blame information for rev 24