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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.par] - Blame information for rev 24

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1 20 jdoin
Release 13.1 par O.40d (nt)
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Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
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4 24 jdoin
DEVELOP-W7::  Thu Sep 01 13:07:30 2011
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par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
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spi_master_atlys_top.ncd spi_master_atlys_top.pcf
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Constraints file: spi_master_atlys_top.pcf.
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Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
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   "spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".
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Device speed data version:  "PRODUCTION 1.18 2011-04-07".
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Device Utilization Summary:
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Slice Logic Utilization:
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  Number of Slice Registers:                   210 out of  54,576    1%
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    Number used as Flip Flops:                 210
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    Number used as Latches:                      0
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    Number used as Latch-thrus:                  0
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    Number used as AND/OR logics:                0
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  Number of Slice LUTs:                        143 out of  27,288    1%
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    Number used as logic:                      129 out of  27,288    1%
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      Number using O6 output only:              79
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      Number using O5 output only:              15
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      Number using O5 and O6:                   35
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      Number used as ROM:                        0
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    Number used as Memory:                       4 out of   6,408    1%
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      Number used as Dual Port RAM:              0
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      Number used as Single Port RAM:            0
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      Number used as Shift Register:             4
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        Number using O6 output only:             4
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        Number using O5 output only:             0
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        Number using O5 and O6:                  0
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    Number used exclusively as route-thrus:     10
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      Number with same-slice register load:      8
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      Number with same-slice carry load:         2
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      Number with other load:                    0
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Slice Logic Distribution:
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  Number of occupied Slices:                    91 out of   6,822    1%
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  Number of LUT Flip Flop pairs used:          231
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    Number with an unused Flip Flop:            46 out of     231   19%
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    Number with an unused LUT:                  88 out of     231   38%
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    Number of fully used LUT-FF pairs:          97 out of     231   41%
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    Number of slice register sites lost
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      to control set restrictions:               0 out of  54,576    0%
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  A LUT Flip Flop pair for this architecture represents one LUT paired with
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  one Flip Flop within a slice.  A control set is a unique combination of
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  clock, reset, set, and enable signals for a registered element.
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  The Slice Logic Distribution report is not meaningful if the design is
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  over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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  Number of bonded IOBs:                        64 out of     218   29%
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    Number of LOCed IOBs:                       46 out of      64   71%
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Specific Feature Utilization:
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  Number of RAMB16BWERs:                         0 out of     116    0%
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  Number of RAMB8BWERs:                          0 out of     232    0%
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  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
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  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
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  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
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    Number used as BUFGs:                        3
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    Number used as BUFGMUX:                      0
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  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
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  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
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  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
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  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
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  Number of BSCANs:                              0 out of       4    0%
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  Number of BUFHs:                               0 out of     256    0%
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  Number of BUFPLLs:                             0 out of       8    0%
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  Number of BUFPLL_MCBs:                         0 out of       4    0%
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  Number of DSP48A1s:                            0 out of      58    0%
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  Number of ICAPs:                               0 out of       1    0%
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  Number of MCBs:                                0 out of       2    0%
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  Number of PCILOGICSEs:                         0 out of       2    0%
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  Number of PLL_ADVs:                            0 out of       4    0%
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  Number of PMVs:                                0 out of       1    0%
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  Number of STARTUPs:                            0 out of       1    0%
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  Number of SUSPEND_SYNCs:                       0 out of       1    0%
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Overall effort level (-ol):   High
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Router effort level (-rl):    High
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WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
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Starting initial Timing Analysis.  REAL time: 4 secs
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Finished initial Timing Analysis.  REAL time: 4 secs
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Starting Router
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109 24 jdoin
Phase  1  : 923 unrouted;      REAL time: 5 secs
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111 24 jdoin
Phase  2  : 776 unrouted;      REAL time: 6 secs
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113 24 jdoin
Phase  3  : 205 unrouted;      REAL time: 7 secs
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Phase  4  : 205 unrouted; (Par is working to improve performance)     REAL time: 8 secs
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Updating file: spi_master_atlys_top.ncd with current fully routed design.
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Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 9 secs
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Total REAL time to Router completion: 9 secs
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Total CPU time to Router completion: 9 secs
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Partition Implementation Status
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-------------------------------
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  No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
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Timing Score: 0 (Setup: 0, Hold: 0)
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Asterisk (*) preceding a constraint indicates it was not met.
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   This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
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                                            |             |    Slack   | Achievable | Errors |    Score
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----------------------------------------------------------------------------------------------------------
151 24 jdoin
  Autotimespec constraint for clock net pcl | SETUP       |         N/A|     5.916ns|     N/A|           0
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  k_i_BUFGP                                 | HOLD        |     0.264ns|            |       0|           0
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----------------------------------------------------------------------------------------------------------
154 24 jdoin
  Autotimespec constraint for clock net Ins | SETUP       |         N/A|     3.959ns|     N/A|           0
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  t_spi_master_port/spi_clk_reg_BUFG        | HOLD        |     0.439ns|            |       0|           0
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----------------------------------------------------------------------------------------------------------
157 24 jdoin
  Autotimespec constraint for clock net scl | SETUP       |         N/A|     3.391ns|     N/A|           0
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  k_i_BUFGP                                 | HOLD        |     0.513ns|            |       0|           0
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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   constraint is not analyzed due to the following: No paths covered by this
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   constraint; Other constraints intersect with this constraint; or This
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   constraint was disabled by a Path Tracing Control. Please run the Timespec
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   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
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Generating Pad Report.
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All signals are completely routed.
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174 24 jdoin
Total REAL time to PAR completion: 9 secs
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Total CPU time to PAR completion: 9 secs
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177 24 jdoin
Peak Memory Usage:  268 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 1
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Number of info messages: 2
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Writing design to file spi_master_atlys_top.ncd
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PAR done!

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