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URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.syr] - Blame information for rev 20

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Line No. Rev Author Line
1 20 jdoin
Release 13.1 - xst O.40d (nt)
2
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.09 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.09 secs
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--> Reading design: spi_master_atlys_top.prj
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17
TABLE OF CONTENTS
18
  1) Synthesis Options Summary
19
  2) HDL Parsing
20
  3) HDL Elaboration
21
  4) HDL Synthesis
22
       4.1) HDL Synthesis Report
23
  5) Advanced HDL Synthesis
24
       5.1) Advanced HDL Synthesis Report
25
  6) Low Level Synthesis
26
  7) Partition Report
27
  8) Design Summary
28
       8.1) Primitive and Black Box Usage
29
       8.2) Device utilization summary
30
       8.3) Partition Resource Summary
31
       8.4) Timing Report
32
            8.4.1) Clock Information
33
            8.4.2) Asynchronous Control Signals Information
34
            8.4.3) Timing Summary
35
            8.4.4) Timing Details
36
            8.4.5) Cross Clock Domains Report
37
 
38
 
39
=========================================================================
40
*                      Synthesis Options Summary                        *
41
=========================================================================
42
---- Source Parameters
43
Input File Name                    : "spi_master_atlys_top.prj"
44
Input Format                       : mixed
45
Ignore Synthesis Constraint File   : NO
46
 
47
---- Target Parameters
48
Output File Name                   : "spi_master_atlys_top"
49
Output Format                      : NGC
50
Target Device                      : xc6slx45-2-csg324
51
 
52
---- Source Options
53
Top Module Name                    : spi_master_atlys_top
54
Automatic FSM Extraction           : YES
55
FSM Encoding Algorithm             : Gray
56
Safe Implementation                : No
57
FSM Style                          : LUT
58
RAM Extraction                     : No
59
ROM Extraction                     : No
60
Shift Register Extraction          : NO
61
Resource Sharing                   : YES
62
Asynchronous To Synchronous        : NO
63
Shift Register Minimum Size        : 2
64
Use DSP Block                      : Auto
65
Automatic Register Balancing       : No
66
 
67
---- Target Options
68
LUT Combining                      : Area
69
Reduce Control Sets                : Auto
70
Add IO Buffers                     : YES
71
Global Maximum Fanout              : 100000
72
Add Generic Clock Buffer(BUFG)     : 16
73
Register Duplication               : YES
74
Optimize Instantiated Primitives   : NO
75
Use Clock Enable                   : Auto
76
Use Synchronous Set                : Auto
77
Use Synchronous Reset              : Auto
78
Pack IO Registers into IOBs        : Auto
79
Equivalent register Removal        : YES
80
 
81
---- General Options
82
Optimization Goal                  : Speed
83
Optimization Effort                : 2
84
Power Reduction                    : NO
85
Keep Hierarchy                     : No
86
Netlist Hierarchy                  : As_Optimized
87
RTL Output                         : Yes
88
Global Optimization                : AllClockNets
89
Read Cores                         : YES
90
Write Timing Constraints           : NO
91
Cross Clock Analysis               : NO
92
Hierarchy Separator                : /
93
Bus Delimiter                      : <>
94
Case Specifier                     : Maintain
95
Slice Utilization Ratio            : 100
96
BRAM Utilization Ratio             : 100
97
DSP48 Utilization Ratio            : 100
98
Auto BRAM Packing                  : NO
99
Slice Utilization Ratio Delta      : 5
100
 
101
=========================================================================
102
 
103
 
104
=========================================================================
105
*                          HDL Parsing                                  *
106
=========================================================================
107
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
108
Parsing entity .
109
Parsing architecture  of entity .
110
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 347: Case choice must be a locally static expression
111
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 355: Case choice must be a locally static expression
112
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 364: Case choice must be a locally static expression
113
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
114
Parsing entity .
115
Parsing architecture  of entity .
116
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 503: Case choice must be a locally static expression
117
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 511: Case choice must be a locally static expression
118
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 519: Case choice must be a locally static expression
119
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 528: Case choice must be a locally static expression
120
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
121
Parsing entity .
122
Parsing architecture  of entity .
123
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
124
Parsing entity .
125
Parsing architecture  of entity .
126
 
127
=========================================================================
128
*                            HDL Elaboration                            *
129
=========================================================================
130
 
131
Elaborating entity  (architecture ) from library .
132
 
133
Elaborating entity  (architecture ) with generics from library .
134
 
135
Elaborating entity  (architecture ) with generics from library .
136
 
137
Elaborating entity  (architecture ) with generics from library .
138
 
139
Elaborating entity  (architecture ) with generics from library .
140
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 456. Case statement is complete. others clause is never selected
141
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 517. Case statement is complete. others clause is never selected
142
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 567. Case statement is complete. others clause is never selected
143
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 174: Net  does not have a driver.
144
 
145
=========================================================================
146
*                           HDL Synthesis                               *
147
=========================================================================
148
 
149
Synthesizing Unit .
150
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
151
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
152
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
153
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
154
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
155
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
156
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
157
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
158
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
159
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
160
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port  of the instance  is unconnected or connected to loadless signal.
161
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port  of the instance  is unconnected or connected to loadless signal.
162
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port  of the instance  is unconnected or connected to loadless signal.
163
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port  of the instance  is unconnected or connected to loadless signal.
164
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port  of the instance  is unconnected or connected to loadless signal.
165
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 221: Output port  of the instance  is unconnected or connected to loadless signal.
166
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 230: Output port  of the instance  is unconnected or connected to loadless signal.
167
WARNING:Xst:2935 - Signal 'dbg<3:0>', unconnected in block 'spi_master_atlys_top', is tied to its initial value (0000).
168
    Found 1-bit register for signal .
169
    Found 1-bit register for signal .
170
    Found 1-bit register for signal .
171
    Found 1-bit register for signal .
172
    Found 8-bit register for signal .
173
    Found 4-bit register for signal .
174
    Found 3-bit register for signal .
175
    Found 3-bit register for signal .
176
    Found 1-bit register for signal .
177
    Found 8-bit register for signal .
178
    Found 1-bit register for signal .
179
    Found 1-bit register for signal .
180
    Found 8-bit register for signal .
181
    Found 6-bit register for signal .
182
    Found 1-bit register for signal .
183
    Found 8-bit register for signal .
184
    Found 8-bit register for signal .
185
    Found 8-bit register for signal .
186
    Found 8-bit register for signal .
187
    Found 1-bit register for signal .
188
    Found finite state machine  for signal .
189
    -----------------------------------------------------------------------
190
    | States             | 7                                              |
191
    | Transitions        | 20                                             |
192
    | Inputs             | 2                                              |
193
    | Outputs            | 3                                              |
194
    | Clock              | gclk_i (rising_edge)                           |
195
    | Reset              | spi_ssel_o (positive)                          |
196
    | Reset type         | synchronous                                    |
197
    | Reset State        | st_reset                                       |
198
    | Power Up State     | st_reset                                       |
199
    | Encoding           | Gray                                           |
200
    | Implementation     | LUT                                            |
201
    -----------------------------------------------------------------------
202
    Found finite state machine  for signal .
203
    -----------------------------------------------------------------------
204
    | States             | 11                                             |
205
    | Transitions        | 36                                             |
206
    | Inputs             | 11                                             |
207
    | Outputs            | 10                                             |
208
    | Clock              | gclk_i (rising_edge)                           |
209
    | Reset              | clear (positive)                               |
210
    | Reset type         | synchronous                                    |
211
    | Reset State        | st_reset                                       |
212
    | Power Up State     | st_reset                                       |
213
    | Encoding           | Gray                                           |
214
    | Implementation     | LUT                                            |
215
    -----------------------------------------------------------------------
216
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM .
217
    Found finite state machine  for signal .
218
    -----------------------------------------------------------------------
219
    | States             | 8                                              |
220
    | Transitions        | 20                                             |
221
    | Inputs             | 5                                              |
222
    | Outputs            | 9                                              |
223
    | Clock              | gclk_i (rising_edge)                           |
224
    | Reset              | spi_ssel_o (positive)                          |
225
    | Reset type         | synchronous                                    |
226
    | Reset State        | st_reset                                       |
227
    | Power Up State     | st_reset                                       |
228
    | Encoding           | Gray                                           |
229
    | Implementation     | LUT                                            |
230
    -----------------------------------------------------------------------
231
    Found 1-bit adder for signal > created at line 273.
232
    Found 1-bit adder for signal > created at line 287.
233
    Found 8-bit comparator equal for signal <_n0380> created at line 359
234
    Found 6-bit comparator equal for signal <_n0400> created at line 362
235
    Summary:
236
        inferred   2 Adder/Subtractor(s).
237
        inferred  71 D-type flip-flop(s).
238
        inferred   2 Comparator(s).
239
        inferred   5 Multiplexer(s).
240
        inferred   3 Finite State Machine(s).
241
Unit  synthesized.
242
 
243
Synthesizing Unit .
244
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
245
        N = 8
246
        CPOL = '0'
247
        CPHA = '0'
248
        PREFETCH = 3
249
        SPI_2X_CLK_DIV = 1
250
    Found 1-bit register for signal .
251
    Found 1-bit register for signal .
252
    Found 1-bit register for signal .
253
    Found 1-bit register for signal .
254
    Found 1-bit register for signal .
255
    Found 1-bit register for signal .
256
    Found 1-bit register for signal .
257
    Found 1-bit register for signal .
258
    Found 1-bit register for signal .
259
    Found 1-bit register for signal .
260
    Found 1-bit register for signal .
261
    Found 1-bit register for signal .
262
    Found 1-bit register for signal .
263
    Found 1-bit register for signal .
264
    Found 1-bit register for signal .
265
    Found 1-bit register for signal .
266
    Found 8-bit register for signal .
267
    Found 1-bit register for signal .
268
    Found 4-bit register for signal .
269
    Found 8-bit register for signal .
270
    Found 1-bit register for signal .
271
    Found 8-bit register for signal .
272
    Found 1-bit register for signal .
273
    Found 1-bit register for signal .
274
    Found 1-bit register for signal .
275
    Found 1-bit register for signal .
276
    Found 1-bit register for signal .
277
    Found 1-bit register for signal .
278
    Found 1-bit adder for signal > created at line 328.
279
    Found 4-bit subtractor for signal > created at line 526.
280
    Found 4-bit comparator greater for signal  created at line 519
281
    Found 4-bit comparator greater for signal  created at line 519
282
    Found 4-bit comparator greater for signal  created at line 528
283
    Found 4-bit comparator greater for signal  created at line 528
284
    Summary:
285
        inferred   2 Adder/Subtractor(s).
286
        inferred  52 D-type flip-flop(s).
287
        inferred   4 Comparator(s).
288
        inferred  13 Multiplexer(s).
289
Unit  synthesized.
290
 
291
Synthesizing Unit .
292
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
293
        N = 8
294
        CPOL = '0'
295
        CPHA = '0'
296
        PREFETCH = 3
297
    Found 4-bit register for signal .
298
    Found 1-bit register for signal .
299
    Found 1-bit register for signal .
300
    Found 1-bit register for signal .
301
    Found 1-bit register for signal .
302
    Found 1-bit register for signal .
303
    Found 1-bit register for signal .
304
    Found 1-bit register for signal .
305
    Found 1-bit register for signal .
306
    Found 1-bit register for signal .
307
    Found 8-bit register for signal .
308
    Found 1-bit register for signal .
309
    Found 8-bit register for signal .
310
    Found 8-bit register for signal .
311
    Found 1-bit register for signal .
312
    Found 1-bit register for signal .
313
    Found 1-bit register for signal .
314
    Found 1-bit register for signal .
315
    Found 1-bit register for signal .
316
    Found 4-bit subtractor for signal > created at line 362.
317
    Found 4-bit comparator greater for signal  created at line 355
318
    Found 4-bit comparator greater for signal  created at line 355
319
    Found 4-bit comparator greater for signal  created at line 364
320
    Found 4-bit comparator greater for signal  created at line 364
321
    Summary:
322
        inferred   1 Adder/Subtractor(s).
323
        inferred  43 D-type flip-flop(s).
324
        inferred   4 Comparator(s).
325
        inferred  22 Multiplexer(s).
326
Unit  synthesized.
327
 
328
Synthesizing Unit .
329
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
330
        N = 8
331
        CNT_VAL = 200
332
    Found 8-bit register for signal .
333
    Found 8-bit register for signal .
334
    Found 8-bit register for signal .
335
    Found 8-bit register for signal .
336
    Found 9-bit adder for signal  created at line 162.
337
    Found 8-bit comparator not equal for signal  created at line 184
338
    Found 8-bit comparator not equal for signal  created at line 190
339
    Summary:
340
        inferred   1 Adder/Subtractor(s).
341
        inferred  32 D-type flip-flop(s).
342
        inferred   2 Comparator(s).
343
Unit  synthesized.
344
 
345
Synthesizing Unit .
346
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
347
        N = 6
348
        CNT_VAL = 200
349
    Found 6-bit register for signal .
350
    Found 6-bit register for signal .
351
    Found 6-bit register for signal .
352
    Found 8-bit register for signal .
353
    Found 9-bit adder for signal  created at line 162.
354
    Found 6-bit comparator not equal for signal  created at line 184
355
    Found 6-bit comparator not equal for signal  created at line 190
356
    Summary:
357
        inferred   1 Adder/Subtractor(s).
358
        inferred  26 D-type flip-flop(s).
359
        inferred   2 Comparator(s).
360
Unit  synthesized.
361
 
362
=========================================================================
363
HDL Synthesis Report
364
 
365
Macro Statistics
366
# Adders/Subtractors                                   : 7
367
 1-bit adder                                           : 3
368
 4-bit subtractor                                      : 2
369
 9-bit adder                                           : 2
370
# Registers                                            : 72
371
 1-bit register                                        : 48
372
 4-bit register                                        : 2
373
 6-bit register                                        : 4
374
 8-bit register                                        : 18
375
# Comparators                                          : 14
376
 4-bit comparator greater                              : 8
377
 6-bit comparator equal                                : 1
378
 6-bit comparator not equal                            : 2
379
 8-bit comparator equal                                : 1
380
 8-bit comparator not equal                            : 2
381
# Multiplexers                                         : 40
382
 1-bit 2-to-1 multiplexer                              : 13
383
 4-bit 2-to-1 multiplexer                              : 12
384
 8-bit 2-to-1 multiplexer                              : 15
385
# FSMs                                                 : 3
386
 
387
=========================================================================
388
 
389
=========================================================================
390
*                       Advanced HDL Synthesis                          *
391
=========================================================================
392
 
393
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
394
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
395
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
396
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
397
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
398
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
399
 
400
Synthesizing (advanced) Unit .
401
The following registers are absorbed into counter : 1 register on signal .
402
Unit  synthesized (advanced).
403
 
404
Synthesizing (advanced) Unit .
405
The following registers are absorbed into counter : 1 register on signal .
406
Unit  synthesized (advanced).
407
 
408
Synthesizing (advanced) Unit .
409
The following registers are absorbed into counter : 1 register on signal .
410
Unit  synthesized (advanced).
411
 
412
Synthesizing (advanced) Unit .
413
The following registers are absorbed into counter : 1 register on signal .
414
The following registers are absorbed into counter : 1 register on signal .
415
Unit  synthesized (advanced).
416
 
417
=========================================================================
418
Advanced HDL Synthesis Report
419
 
420
Macro Statistics
421
# Adders/Subtractors                                   : 2
422
 4-bit subtractor                                      : 2
423
# Counters                                             : 5
424
 1-bit up counter                                      : 3
425
 8-bit up counter                                      : 2
426
# Registers                                            : 205
427
 Flip-Flops                                            : 205
428
# Comparators                                          : 14
429
 4-bit comparator greater                              : 8
430
 6-bit comparator equal                                : 1
431
 6-bit comparator not equal                            : 2
432
 8-bit comparator equal                                : 1
433
 8-bit comparator not equal                            : 2
434
# Multiplexers                                         : 46
435
 1-bit 2-to-1 multiplexer                              : 20
436
 4-bit 2-to-1 multiplexer                              : 12
437
 8-bit 2-to-1 multiplexer                              : 14
438
# FSMs                                                 : 3
439
 
440
=========================================================================
441
 
442
=========================================================================
443
*                         Low Level Synthesis                           *
444
=========================================================================
445
WARNING:Xst:1293 - FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
446
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
447
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
448
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
449
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
450
Optimizing FSM  on signal  with Gray encoding.
451
--------------------------------------
452
 State                    | Encoding
453
--------------------------------------
454
 st_reset                 | 000
455
 st_wait_spi_do_valid_1   | 001
456
 st_wait_spi_n_do_valid_1 | 011
457
 st_wait_spi_do_valid_2   | 010
458
 st_wait_spi_n_do_valid_2 | 110
459
 st_wait_spi_do_valid_3   | 111
460
 st_wait_spi_n_do_valid_3 | 101
461
--------------------------------------
462
Optimizing FSM  on signal  with Gray encoding.
463
----------------------------------
464
 State                | Encoding
465
----------------------------------
466
 st_reset             | 0000
467
 st_wait_spi_idle     | 0001
468
 st_wait_new_switch   | 0011
469
 st_send_spi_data_sw  | 0110
470
 st_wait_spi_ack_sw   | 0111
471
 st_send_spi_data_1   | 0010
472
 st_wait_spi_ack_1    | 0100
473
 st_wait_spi_di_req_2 | 0101
474
 st_wait_spi_ack_2    | 1100
475
 st_wait_spi_di_req_3 | 1101
476
 st_wait_spi_ack_3    | 1111
477
----------------------------------
478
Optimizing FSM  on signal  with Gray encoding.
479
------------------------------------
480
 State                  | Encoding
481
------------------------------------
482
 st_reset               | 000
483
 st_wait_spi_start      | 001
484
 st_wait_spi_di_req_2   | 011
485
 st_wait_spi_ack_2      | unreached
486
 st_wait_spi_do_valid_1 | 010
487
 st_wait_spi_di_req_3   | 110
488
 st_wait_spi_ack_3      | 111
489
 st_wait_spi_end        | 101
490
------------------------------------
491
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
492
   You should achieve better results by setting this init to 1.
493
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
494
   You should achieve better results by setting this init to 1.
495
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
496
   You should achieve better results by setting this init to 1.
497
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_7 hinder the constant cleaning in the block spi_master_atlys_top.
498
   You should achieve better results by setting this init to 1.
499
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 3 FFs/Latches, which will be removed :   
500
 
501
Optimizing unit  ...
502
 
503
Optimizing unit  ...
504
 
505
Optimizing unit  ...
506
 
507
Optimizing unit  ...
508
 
509
Optimizing unit  ...
510
WARNING:Xst:1293 - FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
511
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
512
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
513
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
514
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
515
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
516
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 3 FFs/Latches, which will be removed :   
517
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
518
INFO:Xst:3203 - The FF/Latch  in Unit  is the opposite to the following 2 FFs/Latches, which will be removed :  
519
 
520
Mapping all equations...
521
Building and optimizing final netlist ...
522
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
523
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
524
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
525
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)
526
 
527
Final Macro Processing ...
528
 
529
=========================================================================
530
Final Register Report
531
 
532
Macro Statistics
533
# Registers                                            : 217
534
 Flip-Flops                                            : 217
535
 
536
=========================================================================
537
 
538
=========================================================================
539
*                           Partition Report                            *
540
=========================================================================
541
 
542
Partition Implementation Status
543
-------------------------------
544
 
545
  No Partitions were found in this design.
546
 
547
-------------------------------
548
 
549
=========================================================================
550
*                            Design Summary                             *
551
=========================================================================
552
 
553
Top Level Output File Name         : spi_master_atlys_top.ngc
554
 
555
Primitive and Black Box Usage:
556
------------------------------
557
# BELS                             : 205
558
#      GND                         : 1
559
#      INV                         : 4
560
#      LUT1                        : 14
561
#      LUT2                        : 4
562
#      LUT3                        : 28
563
#      LUT4                        : 17
564
#      LUT5                        : 55
565
#      LUT6                        : 47
566
#      MUXCY                       : 14
567
#      MUXF7                       : 4
568
#      VCC                         : 1
569
#      XORCY                       : 16
570
# FlipFlops/Latches                : 217
571
#      FD                          : 83
572
#      FD_1                        : 1
573
#      FDC                         : 8
574
#      FDE                         : 111
575
#      FDR                         : 10
576
#      FDRE                        : 4
577
# Clock Buffers                    : 2
578
#      BUFG                        : 1
579
#      BUFGP                       : 1
580
# IO Buffers                       : 62
581
#      IBUF                        : 14
582
#      OBUF                        : 48
583
 
584
Device utilization summary:
585
---------------------------
586
 
587
Selected Device : 6slx45csg324-2
588
 
589
 
590
Slice Logic Utilization:
591
 Number of Slice Registers:             217  out of  54576     0%
592
 Number of Slice LUTs:                  169  out of  27288     0%
593
    Number used as Logic:               169  out of  27288     0%
594
 
595
Slice Logic Distribution:
596
 Number of LUT Flip Flop pairs used:    274
597
   Number with an unused Flip Flop:      57  out of    274    20%
598
   Number with an unused LUT:           105  out of    274    38%
599
   Number of fully used LUT-FF pairs:   112  out of    274    40%
600
   Number of unique control sets:        23
601
 
602
IO Utilization:
603
 Number of IOs:                          63
604
 Number of bonded IOBs:                  63  out of    218    28%
605
 
606
Specific Feature Utilization:
607
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%
608
 
609
---------------------------
610
Partition Resource Summary:
611
---------------------------
612
 
613
  No Partitions were found in this design.
614
 
615
---------------------------
616
 
617
 
618
=========================================================================
619
Timing Report
620
 
621
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
622
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
623
      GENERATED AFTER PLACE-and-ROUTE.
624
 
625
Clock Information:
626
------------------
627
-----------------------------------+------------------------+-------+
628
Clock Signal                       | Clock buffer(FF name)  | Load  |
629
-----------------------------------+------------------------+-------+
630
gclk_i                             | BUFGP                  | 189   |
631
Inst_spi_master_port/spi_clk_reg   | BUFG                   | 28    |
632
-----------------------------------+------------------------+-------+
633
 
634
Asynchronous Control Signals Information:
635
----------------------------------------
636
No asynchronous control signals found in this design
637
 
638
Timing Summary:
639
---------------
640
Speed Grade: -2
641
 
642
   Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
643
   Minimum input arrival time before clock: 2.083ns
644
   Maximum output required time after clock: 7.830ns
645
   Maximum combinational path delay: No path found
646
 
647
Timing Details:
648
---------------
649
All values displayed in nanoseconds (ns)
650
 
651
=========================================================================
652
Timing constraint: Default period analysis for Clock 'gclk_i'
653
  Clock period: 5.283ns (frequency: 189.286MHz)
654
  Total number of paths / destination ports: 1727 / 266
655
-------------------------------------------------------------------------
656
Delay:               5.283ns (Levels of Logic = 4)
657
  Source:            sw_reg_5 (FF)
658
  Destination:       btn_reg_0 (FF)
659
  Source Clock:      gclk_i rising
660
  Destination Clock: gclk_i rising
661
 
662
  Data Path: sw_reg_5 to btn_reg_0
663
                                Gate     Net
664
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
665
    ----------------------------------------  ------------
666
     FDE:C->Q              3   0.525   1.196  sw_reg_5 (sw_reg_5)
667
     LUT6:I1->O            2   0.254   0.834  _n038082 (_n038081)
668
     LUT6:I4->O            3   0.250   0.766  _n038083 (_n0380)
669
     LUT5:I4->O            6   0.254   0.876  _n0418_inv1_rstpot (_n0418_inv1_rstpot)
670
     LUT3:I2->O            1   0.254   0.000  btn_reg_0_dpot (btn_reg_0_dpot)
671
     FDE:D                     0.074          btn_reg_0
672
    ----------------------------------------
673
    Total                      5.283ns (1.611ns logic, 3.672ns route)
674
                                       (30.5% logic, 69.5% route)
675
 
676
=========================================================================
677
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
678
  Clock period: 4.344ns (frequency: 230.203MHz)
679
  Total number of paths / destination ports: 214 / 36
680
-------------------------------------------------------------------------
681
Delay:               2.172ns (Levels of Logic = 2)
682
  Source:            Inst_spi_slave_port/state_reg_1_1 (FF)
683
  Destination:       Inst_spi_slave_port/tx_bit_reg (FF)
684
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
685
  Destination Clock: Inst_spi_master_port/spi_clk_reg falling
686
 
687
  Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
688
                                Gate     Net
689
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
690
    ----------------------------------------  ------------
691
     FDC:C->Q              2   0.525   1.156  Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
692
     LUT6:I1->O            1   0.254   0.000  Inst_spi_slave_port/tx_bit_next3_F (N14)
693
     MUXF7:I0->O           1   0.163   0.000  Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
694
     FD_1:D                    0.074          Inst_spi_slave_port/tx_bit_reg
695
    ----------------------------------------
696
    Total                      2.172ns (1.016ns logic, 1.156ns route)
697
                                       (46.8% logic, 53.2% route)
698
 
699
=========================================================================
700
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
701
  Total number of paths / destination ports: 14 / 14
702
-------------------------------------------------------------------------
703
Offset:              2.083ns (Levels of Logic = 1)
704
  Source:            sw_i<7> (PAD)
705
  Destination:       Inst_sw_debouncer/reg_A_7 (FF)
706
  Destination Clock: gclk_i rising
707
 
708
  Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
709
                                Gate     Net
710
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
711
    ----------------------------------------  ------------
712
     IBUF:I->O             1   1.328   0.681  sw_i_7_IBUF (sw_i_7_IBUF)
713
     FD:D                      0.074          Inst_sw_debouncer/reg_A_7
714
    ----------------------------------------
715
    Total                      2.083ns (1.402ns logic, 0.681ns route)
716
                                       (67.3% logic, 32.7% route)
717
 
718
=========================================================================
719
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
720
  Total number of paths / destination ports: 41 / 31
721
-------------------------------------------------------------------------
722
Offset:              7.663ns (Levels of Logic = 4)
723
  Source:            Inst_spi_master_port/ssel_ena_reg (FF)
724
  Destination:       spi_miso_o (PAD)
725
  Source Clock:      gclk_i rising
726
 
727
  Data Path: Inst_spi_master_port/ssel_ena_reg to spi_miso_o
728
                                Gate     Net
729
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
730
    ----------------------------------------  ------------
731
     FDE:C->Q              5   0.525   1.271  Inst_spi_master_port/ssel_ena_reg (Inst_spi_master_port/ssel_ena_reg)
732
     LUT5:I0->O            1   0.254   0.682  Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
733
     LUT6:I5->O            2   0.254   0.834  Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
734
     LUT3:I1->O            1   0.250   0.681  Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
735
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
736
    ----------------------------------------
737
    Total                      7.663ns (4.195ns logic, 3.468ns route)
738
                                       (54.7% logic, 45.3% route)
739
 
740
=========================================================================
741
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
742
  Total number of paths / destination ports: 25 / 14
743
-------------------------------------------------------------------------
744
Offset:              7.830ns (Levels of Logic = 4)
745
  Source:            Inst_spi_slave_port/state_reg_0 (FF)
746
  Destination:       spi_miso_o (PAD)
747
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
748
 
749
  Data Path: Inst_spi_slave_port/state_reg_0 to spi_miso_o
750
                                Gate     Net
751
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
752
    ----------------------------------------  ------------
753
     FDC:C->Q             22   0.525   1.442  Inst_spi_slave_port/state_reg_0 (Inst_spi_slave_port/state_reg_0)
754
     LUT5:I3->O            1   0.250   0.682  Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
755
     LUT6:I5->O            2   0.254   0.834  Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
756
     LUT3:I1->O            1   0.250   0.681  Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
757
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
758
    ----------------------------------------
759
    Total                      7.830ns (4.191ns logic, 3.639ns route)
760
                                       (53.5% logic, 46.5% route)
761
 
762
=========================================================================
763
 
764
Cross Clock Domains Report:
765
--------------------------
766
 
767
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
768
--------------------------------+---------+---------+---------+---------+
769
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
770
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
771
--------------------------------+---------+---------+---------+---------+
772
Inst_spi_master_port/spi_clk_reg|    3.706|         |    2.262|         |
773
gclk_i                          |    4.633|         |    2.169|         |
774
--------------------------------+---------+---------+---------+---------+
775
 
776
Clock to Setup on destination clock gclk_i
777
--------------------------------+---------+---------+---------+---------+
778
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
779
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
780
--------------------------------+---------+---------+---------+---------+
781
Inst_spi_master_port/spi_clk_reg|    4.416|    3.782|         |         |
782
gclk_i                          |    5.283|         |         |         |
783
--------------------------------+---------+---------+---------+---------+
784
 
785
=========================================================================
786
 
787
 
788
Total REAL time to Xst completion: 8.00 secs
789
Total CPU time to Xst completion: 7.33 secs
790
 
791
-->
792
 
793
Total memory usage is 178696 kilobytes
794
 
795
Number of errors   :    0 (   0 filtered)
796
Number of warnings :   29 (   0 filtered)
797
Number of infos    :   22 (   0 filtered)
798
 

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