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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.vhd] - Blame information for rev 10

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1 5 jdoin
----------------------------------------------------------------------------------
2
-- Engineer: Jonny Doin
3
-- 
4
-- Create Date:     01:21:32 06/30/2011 
5
-- Design Name: 
6
-- Module Name:     spi_master_atlys_top
7
-- Project Name:    spi_master_slave
8
-- Target Devices:  Spartan-6 LX45
9
-- Tool versions:   ISE 13.1
10
-- Description: 
11 10 jdoin
--          This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
12 5 jdoin
--          It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
13
--
14 10 jdoin
--          See the "spi_master_atlys.ucf" file for pin assignments.
15 5 jdoin
--          The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
16
--          with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
17
--          digital pod port.
18 10 jdoin
--          The board switches are used to set the SPI_MASTER transmit data, and the SPI_SLAVE receive data drives the switch LEDs.
19
--          The pushbuttons drive the slave transmit data, and the master received data drives the parallel debug port.
20 5 jdoin
--
21
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
22
--
23
-- 2011/07/02   v0.01.0010  [JD]    implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
24
-- 2011/07/03   v0.01.0020  [JD]    added clock input, and a simple LED blinker for each LED. 
25
-- 2011/07/03   v0.01.0030  [JD]    added clear input, and instantiated a SPI_MASTER from my OpenCores project. 
26
-- 2011/07/04   v0.01.0040  [JD]    changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
27
--                                  this change made the design go up to 288MHz, after synthesis.
28
-- 2011/07/07   v0.03.0050  [JD]    implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
29
--                                  external monitoring pins to the VHDCI ports.
30
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, 
31
--                                  6.25MHz, 1MHz and 500kHz 
32
--
33
--
34
----------------------------------------------------------------------------------
35
library ieee;
36
use ieee.std_logic_1164.all;
37 10 jdoin
use ieee.std_logic_arith.all;
38 5 jdoin
 
39
entity spi_master_atlys_top is
40
    Port (
41
        gclk_i : in std_logic := 'X';               -- board clock input 100MHz
42
        clear_i : in std_logic := '0';              -- btn used as clear signal
43
        --- SPI interface ---
44
        spi_ssel_o : out std_logic;                 -- spi port SSEL
45
        spi_sck_o : out std_logic;                  -- spi port SCK
46
        spi_mosi_o : out std_logic;                 -- spi port MOSI
47 10 jdoin
        spi_miso_o : out std_logic;                 -- spi port MISO
48 5 jdoin
        --- input slide switches ---
49
        sw_i : in std_logic_vector (7 downto 0);    -- 8 input slide switches
50
        --- input buttons ---
51
        btn_i : in std_logic_vector (5 downto 0);   -- 6 input push buttons
52
        --- output LEDs ----
53
        led_o : out std_logic_vector (7 downto 0);  -- output leds
54
        --- debug outputs ---
55 10 jdoin
        dbg_o : out std_logic_vector (7 downto 0);  -- 10 generic debug pins
56 5 jdoin
        --- spi debug pins ---
57 10 jdoin
        spi_rx_bit_m_o : out std_logic;             -- master rx bit feedback
58
        spi_rx_bit_s_o : out std_logic;             -- slave rx bit feedback
59
        spi_do_valid_o : out std_logic;             -- spi data valid
60 5 jdoin
        spi_di_req_o : out std_logic;               -- spi data request
61
        spi_wren_o : out std_logic;                 -- spi write enable
62
        spi_wren_ack_o : out std_logic              -- spi write enable ack
63
    );
64
end spi_master_atlys_top;
65
 
66
architecture behavioral of spi_master_atlys_top is
67
 
68
    --=============================================================================================
69
    -- Constants
70
    --=============================================================================================
71
    -- clock divider count values from gclk_i (100MHz board clock)
72
    -- these constants shall not be zero
73 10 jdoin
    constant FSM_CE_DIV         : integer := 1;     -- fsm operates at 100MHz
74 5 jdoin
    constant SPI_2X_CLK_DIV     : integer := 1;     -- 50MHz SPI clock
75 10 jdoin
    constant SAMP_CE_DIV        : integer := 1;     -- board signals sampled at 100MHz
76 5 jdoin
    -- spi port generics
77
    constant N : integer := 8;                      -- 8 bits
78
 
79
    -- button definitions
80
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
81
    constant btUP       : integer := 1;
82
    constant btLEFT     : integer := 2;
83
    constant btDOWN     : integer := 3;
84
    constant btRIGHT    : integer := 4;
85
    constant btCENTER   : integer := 5;
86
 
87
    --=============================================================================================
88
    -- Type definitions
89
    --=============================================================================================
90
    type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch,
91 10 jdoin
                            st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish );
92 5 jdoin
 
93
    --=============================================================================================
94
    -- Signals for state machine control
95
    --=============================================================================================
96 10 jdoin
    signal state_reg        : fsm_state_type := st_reset;
97
    signal state_next       : fsm_state_type := st_reset;
98 5 jdoin
 
99
    --=============================================================================================
100
    -- Signals for internal operation
101
    --=============================================================================================
102 10 jdoin
    --- clock enable signals ---
103
    signal samp_ce          : std_logic := '1';         -- clock enable for sample inputs
104
    signal fsm_ce           : std_logic := '1';         -- clock enable for fsm logic
105
    --- switch debouncer signals ---
106
    signal sw_data          : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
107
    signal sw_reg           : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data 
108
    signal sw_next          : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
109
    signal new_switch       : std_logic := '0';                                 -- detector for new switch data
110
    --- pushbutton debouncer signals ---
111
    signal btn_data         : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
112
    signal btn_reg          : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data 
113
    signal btn_next         : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
114
    signal new_button       : std_logic := '0';                                 -- detector for new button data
115
    --- spi port signals ---
116
    -- spi bus wires
117
    signal spi_ssel         : std_logic;
118
    signal spi_sck          : std_logic;
119
    signal spi_mosi         : std_logic;
120
    signal spi_miso         : std_logic;
121
    -- spi master port control signals
122
    signal spi_rst_reg      : std_logic := '1';
123
    signal spi_rst_next     : std_logic := '1';
124
    signal spi_ssel_reg     : std_logic;
125
    signal spi_wren_reg_m   : std_logic := '0';
126
    signal spi_wren_next_m  : std_logic := '0';
127
    -- spi master port flow control flags
128
    signal spi_di_req_m     : std_logic;
129
    signal spi_do_valid_m   : std_logic;
130
    -- spi master port parallel data bus
131
    signal spi_di_reg_m     : std_logic_vector (N-1 downto 0) := (others => '0');
132
    signal spi_di_next_m    : std_logic_vector (N-1 downto 0) := (others => '0');
133
    signal spi_do_m         : std_logic_vector (N-1 downto 0);
134
    -- spi master port debug flags
135
    signal spi_rx_bit_m     : std_logic;
136
    signal spi_wr_ack_m     : std_logic;
137
    -- spi slave port control signals
138
    signal spi_wren_reg_s   : std_logic := '1';
139
    signal spi_wren_next_s  : std_logic := '0';
140
    -- spi slave port flow control flags
141
    signal spi_di_req_s     : std_logic;
142
    signal spi_do_valid_s   : std_logic;
143
    -- spi slave port parallel data bus
144
    signal spi_di_reg_s     : std_logic_vector (N-1 downto 0) := (7 => '1', 6 => '0', 5 => '1', others => '0');
145
    signal spi_di_next_s    : std_logic_vector (N-1 downto 0) := (others => '0');
146
    signal spi_do_s         : std_logic_vector (N-1 downto 0);
147
    -- spi slave port debug flags
148
    signal spi_rx_bit_s     : std_logic;
149
    signal spi_wr_ack_s     : std_logic;
150 5 jdoin
    -- other signals
151 10 jdoin
    signal clear            : std_logic := '0';
152
    -- debug output signals
153
    signal leds_reg         : std_logic_vector (7 downto 0) := (others => '0');
154
    signal dbg              : std_logic_vector (7 downto 0) := (others => '0');
155 5 jdoin
begin
156
 
157
    --=============================================================================================
158 10 jdoin
    -- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
159 5 jdoin
    --=============================================================================================
160 10 jdoin
    -- spi master port: 
161
    --      receives parallel data from the slide switches, transmits to slave port.
162
    --      receives serial data from slave port, sends to 8bit parallel debug port.
163
    Inst_spi_master_port: entity work.spi_master(rtl)
164 5 jdoin
        generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
165
        port map(
166 10 jdoin
            sclk_i => gclk_i,                   -- system clock is used for serial and parallel ports
167
            pclk_i => gclk_i,
168 5 jdoin
            rst_i => spi_rst_reg,
169
            spi_ssel_o => spi_ssel,
170
            spi_sck_o => spi_sck,
171
            spi_mosi_o => spi_mosi,
172 10 jdoin
            spi_miso_i => spi_miso,
173
            di_req_o => spi_di_req_m,
174
            di_i => spi_di_reg_m,
175
            do_valid_o => spi_do_valid_m,
176
            do_o => spi_do_m,
177
            rx_bit_reg_o => spi_rx_bit_m,
178
            wren_i => spi_wren_reg_m,
179 5 jdoin
            wren_o => spi_wren_o,
180 10 jdoin
            wren_ack_o => spi_wr_ack_m          -- monitor wren ack from inside spi port
181 5 jdoin
        );
182
 
183 10 jdoin
    dbg(7 downto 0) <= spi_do_m(7 downto 0);    -- connect master received data to 8bit debug port
184
    spi_rx_bit_m_o  <= spi_rx_bit_m;            -- connect rx_bit monitor for master port
185
 
186
    -- spi slave port
187
    --      receives parallel data from the pushbuttons, transmits to master port.
188
    --      receives serial data from master port, sends to the 8 LEDs.
189
    Inst_spi_slave_port: entity work.spi_slave(rtl)
190
        generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3)
191
        port map(
192
            clk_i => gclk_i,
193
            spi_ssel_i => spi_ssel,             -- generated by the spi master
194
            spi_sck_i => spi_sck,               -- generated by the spi master
195
            spi_mosi_i => spi_mosi,
196
            spi_miso_o => spi_miso,
197
            di_req_o => spi_di_req_s,
198
            di_i => spi_di_reg_s,
199
            wren_i => spi_wren_reg_s,
200
            rx_bit_reg_o => spi_rx_bit_s,
201
            do_valid_o => spi_do_valid_s,
202
            do_o => spi_do_s
203
        );
204
 
205
    spi_di_reg_s(7 downto 5) <= B"101";                 -- get the slave transmit data from pushbuttons
206
    spi_di_reg_s(4 downto 0) <= btn_data(5 downto 1);
207
    spi_wren_reg_s <= '1';                              -- fix wren to '1', for continuous load of transmit data
208
    spi_rx_bit_s_o <= spi_rx_bit_s;                     -- connect rx_bit monitor for slave port
209
 
210 5 jdoin
    -- debounce for the input switches, with new data strobe output
211
    Inst_sw_debouncer: entity work.grp_debouncer(rtl)
212
        generic map (N => 8, CNT_VAL => 10000)  -- debounce 8 inputs with 100 us settling time
213
        port map(
214 10 jdoin
            clk_i => gclk_i,                    -- system clock
215 5 jdoin
            data_i => sw_i,                     -- noisy input data
216 10 jdoin
            data_o => sw_data                   -- registered stable output data
217
--            strb_o => dbg(0)                    -- monitor the debounced data strobe
218 5 jdoin
        );
219
 
220
    -- debounce for the input pushbuttons, with new data strobe output
221
    Inst_btn_debouncer: entity work.grp_debouncer(rtl)
222
        generic map (N => 6, CNT_VAL => 50000)  -- debounce 6 inputs with 500 us settling time
223
        port map(
224 10 jdoin
            clk_i => gclk_i,                    -- system clock
225 5 jdoin
            data_i => btn_i,                    -- noisy input data
226 10 jdoin
            data_o => btn_data                  -- registered stable output data
227
--            strb_o => dbg(3)                    -- monitor the debounced data strobe
228 5 jdoin
        );
229
 
230
    --=============================================================================================
231
    --  CONSTANTS CONSTRAINTS CHECKING
232
    --=============================================================================================
233
    -- clock dividers shall not be zero
234 10 jdoin
    assert FSM_CE_DIV > 0
235
    report "Constant 'FSM_CE_DIV' should not be zero"
236 5 jdoin
    severity FAILURE;
237
    -- minimum prefetch lookahead check
238 10 jdoin
    assert SPI_2X_CLK_DIV > 0
239
    report "Constant 'SPI_2X_CLK_DIV' should not be zero"
240 5 jdoin
    severity FAILURE;
241
    -- maximum prefetch lookahead check
242 10 jdoin
    assert SAMP_CE_DIV > 0
243
    report "Constant 'SAMP_CE_DIV' should not be zero"
244 5 jdoin
    severity FAILURE;
245
 
246
    --=============================================================================================
247
    --  CLOCK GENERATION
248
    --=============================================================================================
249
    -- The clock generation block derives 3 internal clocks, divided down from the 100MHz input clock 
250
    --      core clock, 
251
    --      spi 2x base clock,
252
    --      fsm clock,
253
    -----------------------------------------------------------------------------------------------
254
    -- generate the sampling clock enable from the 100MHz board input clock 
255
    samp_ce_gen_proc: process (gclk_i) is
256
        variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
257
    begin
258
        if gclk_i'event and gclk_i = '1' then
259
            if clk_cnt = SAMP_CE_DIV-1 then
260
                samp_ce <= '1';
261
                clk_cnt := 0;
262
            else
263
                samp_ce <= '0';
264
                clk_cnt := clk_cnt + 1;
265
            end if;
266
        end if;
267
    end process samp_ce_gen_proc;
268
    -- generate the fsm clock enable from the 100MHz board input clock 
269
    fsm_ce_gen_proc: process (gclk_i) is
270
        variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
271
    begin
272
        if gclk_i'event and gclk_i = '1' then
273
            if clk_cnt = FSM_CE_DIV-1 then
274
                fsm_ce <= '1';
275
                clk_cnt := 0;
276
            else
277
                fsm_ce <= '0';
278
                clk_cnt := clk_cnt + 1;
279
            end if;
280
        end if;
281
    end process fsm_ce_gen_proc;
282
 
283
    --=============================================================================================
284
    -- INPUTS LOGIC
285
    --=============================================================================================
286
    -- registered inputs
287 10 jdoin
    samp_inputs_proc: process (gclk_i) is
288 5 jdoin
    begin
289 10 jdoin
        if gclk_i'event and gclk_i = '1' then
290 5 jdoin
            if samp_ce = '1' then
291 10 jdoin
                clear <= btn_data(btUP);        -- clear is button UP
292
                leds_reg <= spi_do_s;           -- update LEDs with spi_slave received data
293 5 jdoin
            end if;
294
        end if;
295
    end process samp_inputs_proc;
296
 
297
    --=============================================================================================
298 10 jdoin
    --  REGISTER TRANSFER PROCESSES
299 5 jdoin
    --=============================================================================================
300
    -- fsm state and data registers: synchronous to the spi base reference clock
301 10 jdoin
    fsm_reg_proc : process (gclk_i) is
302 5 jdoin
    begin
303
        -- FFD registers clocked on rising edge and cleared on sync 'clear'
304 10 jdoin
        if gclk_i'event and gclk_i = '1' then
305 5 jdoin
            if clear = '1' then                 -- sync reset
306
                state_reg <= st_reset;          -- only provide local reset for the state register
307
            else
308
                if fsm_ce = '1' then
309
                    state_reg <= state_next;    -- state register
310
                end if;
311
            end if;
312
        end if;
313
        -- FFD registers clocked on rising edge, with no reset
314 10 jdoin
        if gclk_i'event and gclk_i = '1' then
315 5 jdoin
            if fsm_ce = '1' then
316 10 jdoin
                spi_wren_reg_m <= spi_wren_next_m;
317
                spi_di_reg_m <= spi_di_next_m;
318
--                spi_wren_reg_s <= spi_wren_next_s;
319
--                spi_di_reg_s <= spi_di_next_s;
320 5 jdoin
                spi_rst_reg <= spi_rst_next;
321
                spi_ssel_reg <= spi_ssel;
322
                sw_reg <= sw_next;
323
                btn_reg <= btn_next;
324
            end if;
325
        end if;
326
    end process fsm_reg_proc;
327
 
328
    --=============================================================================================
329 10 jdoin
    --  COMBINATORIAL NEXT-STATE LOGIC PROCESSES
330 5 jdoin
    --=============================================================================================
331
    -- edge detector for new switch data
332 10 jdoin
    new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0';     -- '1' for difference
333 5 jdoin
    -- edge detector for new button data
334 10 jdoin
    new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0';   -- '1' for difference
335 5 jdoin
    -- fsm state and combinatorial logic
336
    -- the sequencer will wait for a new switch combination, and send the switch data to the spi port
337 10 jdoin
    fsm_combi_proc: process (   state_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, -- spi_di_reg_s, 
338
                                spi_wren_reg_s, spi_ssel_reg, spi_rst_reg, sw_data,
339
                                sw_reg, new_switch, btn_data, btn_reg, new_button) is
340 5 jdoin
    begin
341
        spi_rst_next <= spi_rst_reg;
342 10 jdoin
        spi_di_next_m <= spi_di_reg_m;
343
        spi_wren_next_m <= spi_wren_reg_m;
344
--        spi_di_next_s <= spi_di_reg_s;
345
--        spi_wren_next_s <= spi_wren_reg_s;
346 5 jdoin
        sw_next <= sw_reg;
347
        btn_next <= btn_reg;
348
        state_next <= state_reg;
349
        case state_reg is
350
            when st_reset =>
351
                spi_rst_next <= '1';                        -- place spi interface on reset
352 10 jdoin
                spi_di_next_m <= (others => '0');           -- clear spi data port
353
                spi_di_next_s <= (others => '0');           -- clear spi data port
354
                spi_wren_next_m <= '0';                     -- deassert write enable
355
                spi_wren_next_s <= '0';                     -- deassert write enable
356 5 jdoin
                state_next <= st_wait_spi_idle;
357
 
358
            when st_wait_spi_idle =>
359
                if spi_ssel_reg = '1' then
360
                    spi_rst_next <= '0';                    -- remove reset when interface is idle
361
                    state_next <= st_wait_new_switch;
362
                end if;
363
 
364
            when st_wait_new_switch =>
365
                if new_switch = '1' then                    -- wait for new stable switch data
366
                    sw_next <= sw_data;                     -- load new switch data (end the mismatch condition)
367
                    state_next <= st_send_spi_data;
368
                elsif new_button = '1' then
369
                    btn_next <= btn_data;                   -- load new button data (end the mismatch condition)
370 10 jdoin
                    if btn_data /= B"000001" then
371 5 jdoin
                        state_next <= st_send_spi_data;
372
                    end if;
373
                end if;
374
 
375
            when st_send_spi_data =>
376 10 jdoin
                spi_di_next_m <= sw_reg;                    -- load switch register to the spi port
377
                spi_wren_next_m <= '1';                     -- write data on next clock
378 5 jdoin
                state_next <= st_wait_spi_ack;
379
 
380
            when st_wait_spi_ack =>                         -- the actual write happens on this state
381 10 jdoin
                spi_di_next_m <= sw_reg;                    -- load switch register to the spi port
382
                if spi_wr_ack_m = '1' then                  -- wait acknowledge
383
                    spi_wren_next_m <= '0';                 -- remove write strobe on next clock
384 5 jdoin
                    state_next <= st_wait_spi_finish;
385
                end if;
386
 
387
            when st_wait_spi_finish =>
388
                if spi_ssel_reg = '1' then
389
                    state_next <= st_wait_new_switch;
390
                end if;
391
 
392
            when others =>
393
                state_next <= st_reset;                     -- state st_reset is safe state
394
        end case;
395
    end process fsm_combi_proc;
396
 
397
    --=============================================================================================
398
    --  OUTPUT LOGIC PROCESSES
399
    --=============================================================================================
400
    -- connect the spi output wires
401 10 jdoin
    spi_ssel_o_proc:        spi_ssel_o      <= spi_ssel;
402
    spi_sck_o_proc:         spi_sck_o       <= spi_sck;
403
    spi_mosi_o_proc:        spi_mosi_o      <= spi_mosi;
404
    spi_miso_o_proc:        spi_miso_o      <= spi_miso;
405
    spi_do_valid_o_proc:    spi_do_valid_o  <= spi_do_valid_m;
406
    spi_di_req_o_proc:      spi_di_req_o    <= spi_di_req_m;
407
    spi_wren_ack_o_proc:    spi_wren_ack_o  <= spi_wr_ack_m;
408
    led_o_proc:             led_o           <= leds_reg;        -- connect leds_reg signal to LED outputs
409 5 jdoin
 
410
    --=============================================================================================
411
    --  DEBUG LOGIC PROCESSES
412
    --=============================================================================================
413
    -- connect the debug vector outputs
414 10 jdoin
    dbg_o_proc:             dbg_o <= dbg;
415
 
416 5 jdoin
end behavioral;
417
 

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