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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.vhd] - Blame information for rev 22

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1 5 jdoin
----------------------------------------------------------------------------------
2 12 jdoin
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
3 5 jdoin
-- 
4
-- Create Date:     01:21:32 06/30/2011 
5
-- Design Name: 
6
-- Module Name:     spi_master_atlys_top
7
-- Project Name:    spi_master_slave
8
-- Target Devices:  Spartan-6 LX45
9
-- Tool versions:   ISE 13.1
10
-- Description: 
11 10 jdoin
--          This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
12 5 jdoin
--          It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
13
--
14 10 jdoin
--          See the "spi_master_atlys.ucf" file for pin assignments.
15 5 jdoin
--          The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
16
--          with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
17
--          digital pod port.
18
--
19
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
20
--
21
-- 2011/07/02   v0.01.0010  [JD]    implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
22
-- 2011/07/03   v0.01.0020  [JD]    added clock input, and a simple LED blinker for each LED. 
23
-- 2011/07/03   v0.01.0030  [JD]    added clear input, and instantiated a SPI_MASTER from my OpenCores project. 
24
-- 2011/07/04   v0.01.0040  [JD]    changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
25
--                                  this change made the design go up to 288MHz, after synthesis.
26
-- 2011/07/07   v0.03.0050  [JD]    implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
27
--                                  external monitoring pins to the VHDCI ports.
28
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, 
29
--                                  6.25MHz, 1MHz and 500kHz 
30 12 jdoin
-- 2011/07/29   v1.12.0105  [JD]    spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
31 13 jdoin
-- 2011/08/02   v1.13.0110  [JD]    testbed for continuous transfer in FPGA hardware.
32 5 jdoin
--
33
--
34
----------------------------------------------------------------------------------
35
library ieee;
36
use ieee.std_logic_1164.all;
37 11 jdoin
use ieee.std_logic_arith.all;
38 5 jdoin
 
39
entity spi_master_atlys_top is
40 22 jdoin
    Generic (
41
        N : positive := 8;                              -- 8bit serial word length is default
42
        CPOL : std_logic := '0';                        -- SPI mode selection (mode 0 default)
43
        CPHA : std_logic := '0';                        -- CPOL = clock polarity, CPHA = clock phase.
44
        PREFETCH : positive := 3;                       -- prefetch lookahead cycles
45
        CLK_PERIOD : time := 10 ns;                     -- clock period for gclk_i (default 100MHz)
46
        DEBOUNCE_TIME : time := 200 us);                -- switch debounce time (use 200 us for silicon, 2 us for simulation)
47 5 jdoin
    Port (
48 22 jdoin
        gclk_i : in std_logic := 'X';                   -- board clock input 100MHz
49 12 jdoin
        --- SPI interface ---           
50 22 jdoin
        spi_ssel_o : out std_logic;                     -- spi port SSEL
51
        spi_sck_o : out std_logic;                      -- spi port SCK
52
        spi_mosi_o : out std_logic;                     -- spi port MOSI
53
        spi_miso_o : out std_logic;                     -- spi port MISO
54 12 jdoin
        --- input slide switches ---            
55 22 jdoin
        sw_i : in std_logic_vector (7 downto 0);        -- 8 input slide switches
56 12 jdoin
        --- input buttons ---           
57 22 jdoin
        btn_i : in std_logic_vector (5 downto 0);       -- 6 input push buttons
58 12 jdoin
        --- output LEDs ----            
59 22 jdoin
        led_o : out std_logic_vector (7 downto 0);      -- output leds
60 5 jdoin
        --- debug outputs ---
61 20 jdoin
        s_do_o : out std_logic_vector (7 downto 0);
62
        m_do_o : out std_logic_vector (7 downto 0);
63 22 jdoin
        m_state_o : out std_logic_vector (3 downto 0);  -- master spi fsm state
64
        s_state_o : out std_logic_vector (3 downto 0);  -- slave spi fsm state
65
        dbg_o : out std_logic_vector (11 downto 0)      -- 12 generic debug pins
66 5 jdoin
    );
67
end spi_master_atlys_top;
68
 
69 22 jdoin
architecture rtl of spi_master_atlys_top is
70 5 jdoin
 
71
    --=============================================================================================
72
    -- Constants
73
    --=============================================================================================
74
    -- clock divider count values from gclk_i (100MHz board clock)
75
    -- these constants shall not be zero
76 10 jdoin
    constant FSM_CE_DIV         : integer := 1;     -- fsm operates at 100MHz
77 5 jdoin
    constant SPI_2X_CLK_DIV     : integer := 1;     -- 50MHz SPI clock
78 10 jdoin
    constant SAMP_CE_DIV        : integer := 1;     -- board signals sampled at 100MHz
79 5 jdoin
 
80
    -- button definitions
81
    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
82
    constant btUP       : integer := 1;
83
    constant btLEFT     : integer := 2;
84
    constant btDOWN     : integer := 3;
85
    constant btRIGHT    : integer := 4;
86
    constant btCENTER   : integer := 5;
87
 
88
    --=============================================================================================
89
    -- Type definitions
90
    --=============================================================================================
91 13 jdoin
    type fsm_master_write_state_type is
92
            (st_reset, st_wait_spi_idle, st_wait_new_switch, st_send_spi_data_sw, st_wait_spi_ack_sw,
93
            st_send_spi_data_1, st_wait_spi_ack_1, st_wait_spi_di_req_2, st_wait_spi_ack_2,
94
            st_wait_spi_di_req_3, st_wait_spi_ack_3);
95 5 jdoin
 
96 13 jdoin
    type fsm_slave_write_state_type is
97 20 jdoin
            (st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, st_wait_spi_do_valid_1,
98 13 jdoin
            st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end);
99
 
100
    type fsm_slave_read_state_type is
101
            (st_reset, st_wait_spi_do_valid_1, st_wait_spi_n_do_valid_1, st_wait_spi_do_valid_2,
102
            st_wait_spi_n_do_valid_2, st_wait_spi_do_valid_3, st_wait_spi_n_do_valid_3);
103
 
104 5 jdoin
    --=============================================================================================
105
    -- Signals for state machine control
106
    --=============================================================================================
107 13 jdoin
    signal m_wr_st_reg  : fsm_master_write_state_type := st_reset;
108
    signal m_wr_st_next : fsm_master_write_state_type := st_reset;
109
    signal s_wr_st_reg  : fsm_slave_write_state_type := st_reset;
110
    signal s_wr_st_next : fsm_slave_write_state_type := st_reset;
111
    signal s_rd_st_reg  : fsm_slave_read_state_type := st_reset;
112
    signal s_rd_st_next : fsm_slave_read_state_type := st_reset;
113 5 jdoin
 
114
    --=============================================================================================
115
    -- Signals for internal operation
116
    --=============================================================================================
117 10 jdoin
    --- clock enable signals ---
118
    signal samp_ce          : std_logic := '1';         -- clock enable for sample inputs
119
    signal fsm_ce           : std_logic := '1';         -- clock enable for fsm logic
120
    --- switch debouncer signals ---
121
    signal sw_data          : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
122
    signal sw_reg           : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data 
123
    signal sw_next          : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
124
    signal new_switch       : std_logic := '0';                                 -- detector for new switch data
125
    --- pushbutton debouncer signals ---
126
    signal btn_data         : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
127
    signal btn_reg          : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data 
128
    signal btn_next         : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
129
    signal new_button       : std_logic := '0';                                 -- detector for new button data
130
    --- spi port signals ---
131
    -- spi bus wires
132
    signal spi_ssel         : std_logic;
133
    signal spi_sck          : std_logic;
134
    signal spi_mosi         : std_logic;
135
    signal spi_miso         : std_logic;
136
    -- spi master port control signals
137
    signal spi_rst_reg      : std_logic := '1';
138
    signal spi_rst_next     : std_logic := '1';
139
    signal spi_ssel_reg     : std_logic;
140
    signal spi_wren_reg_m   : std_logic := '0';
141
    signal spi_wren_next_m  : std_logic := '0';
142
    -- spi master port flow control flags
143
    signal spi_di_req_m     : std_logic;
144
    signal spi_do_valid_m   : std_logic;
145
    -- spi master port parallel data bus
146
    signal spi_di_reg_m     : std_logic_vector (N-1 downto 0) := (others => '0');
147
    signal spi_di_next_m    : std_logic_vector (N-1 downto 0) := (others => '0');
148
    signal spi_do_m         : std_logic_vector (N-1 downto 0);
149
    signal spi_wr_ack_m     : std_logic;
150
    -- spi slave port control signals
151
    signal spi_wren_reg_s   : std_logic := '1';
152 12 jdoin
    signal spi_wren_next_s  : std_logic := '1';
153 10 jdoin
    -- spi slave port flow control flags
154
    signal spi_di_req_s     : std_logic;
155
    signal spi_do_valid_s   : std_logic;
156
    -- spi slave port parallel data bus
157 12 jdoin
    signal spi_di_reg_s     : std_logic_vector (N-1 downto 0) := (others => '0');
158 10 jdoin
    signal spi_di_next_s    : std_logic_vector (N-1 downto 0) := (others => '0');
159
    signal spi_do_s         : std_logic_vector (N-1 downto 0);
160 13 jdoin
    signal spi_wr_ack_s     : std_logic;
161 10 jdoin
    signal spi_rx_bit_s     : std_logic;
162 20 jdoin
    -- spi debug data --
163
    signal spi_state_m      : std_logic_vector (3 downto 0);
164
    signal spi_state_s      : std_logic_vector (3 downto 0);
165 13 jdoin
    -- slave data output regs --
166
    signal s_do_1_reg       : std_logic_vector (N-1 downto 0) := (others => '0');
167
    signal s_do_1_next      : std_logic_vector (N-1 downto 0) := (others => '0');
168
    signal s_do_2_reg       : std_logic_vector (N-1 downto 0) := (others => '0');
169
    signal s_do_2_next      : std_logic_vector (N-1 downto 0) := (others => '0');
170
    signal s_do_3_reg       : std_logic_vector (N-1 downto 0) := (others => '0');
171
    signal s_do_3_next      : std_logic_vector (N-1 downto 0) := (others => '0');
172 5 jdoin
    -- other signals
173 10 jdoin
    signal clear            : std_logic := '0';
174
    -- debug output signals
175 13 jdoin
    signal leds_reg         : std_logic_vector (7 downto 0);
176
    signal leds_next        : std_logic_vector (7 downto 0) := (others => '0');
177 12 jdoin
    signal dbg              : std_logic_vector (11 downto 0) := (others => '0');
178 5 jdoin
begin
179
 
180
    --=============================================================================================
181 10 jdoin
    -- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
182 5 jdoin
    --=============================================================================================
183 13 jdoin
    -- spi master port: data and control signals driven by the master fsm
184 10 jdoin
    Inst_spi_master_port: entity work.spi_master(rtl)
185 22 jdoin
        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
186 5 jdoin
        port map(
187 10 jdoin
            sclk_i => gclk_i,                   -- system clock is used for serial and parallel ports
188
            pclk_i => gclk_i,
189 5 jdoin
            rst_i => spi_rst_reg,
190
            spi_ssel_o => spi_ssel,
191
            spi_sck_o => spi_sck,
192
            spi_mosi_o => spi_mosi,
193 13 jdoin
            spi_miso_i => spi_miso,             -- driven by the spi slave 
194 10 jdoin
            di_req_o => spi_di_req_m,
195
            di_i => spi_di_reg_m,
196 12 jdoin
            wren_i => spi_wren_reg_m,
197 13 jdoin
            wr_ack_o => spi_wr_ack_m,
198 10 jdoin
            do_valid_o => spi_do_valid_m,
199 20 jdoin
            do_o => spi_do_m,
200 12 jdoin
            ------------ debug pins ------------
201 20 jdoin
            state_dbg_o => spi_state_m          -- debug: internal state register
202 5 jdoin
        );
203
 
204 13 jdoin
    -- spi slave port: data and control signals driven by the slave fsm
205 10 jdoin
    Inst_spi_slave_port: entity work.spi_slave(rtl)
206 22 jdoin
        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
207 10 jdoin
        port map(
208
            clk_i => gclk_i,
209 13 jdoin
            spi_ssel_i => spi_ssel,             -- driven by the spi master
210
            spi_sck_i => spi_sck,               -- driven by the spi master
211
            spi_mosi_i => spi_mosi,             -- driven by the spi master
212 10 jdoin
            spi_miso_o => spi_miso,
213
            di_req_o => spi_di_req_s,
214
            di_i => spi_di_reg_s,
215
            wren_i => spi_wren_reg_s,
216 13 jdoin
            wr_ack_o => spi_wr_ack_s,
217 10 jdoin
            do_valid_o => spi_do_valid_s,
218 20 jdoin
            do_o => spi_do_s,
219 12 jdoin
            ------------ debug pins ------------
220 20 jdoin
            state_dbg_o => spi_state_s          -- debug: internal state register
221 10 jdoin
        );
222
 
223 5 jdoin
    -- debounce for the input switches, with new data strobe output
224
    Inst_sw_debouncer: entity work.grp_debouncer(rtl)
225 22 jdoin
        generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
226 5 jdoin
        port map(
227 10 jdoin
            clk_i => gclk_i,                    -- system clock
228 5 jdoin
            data_i => sw_i,                     -- noisy input data
229 10 jdoin
            data_o => sw_data                   -- registered stable output data
230 12 jdoin
        );
231 5 jdoin
 
232
    -- debounce for the input pushbuttons, with new data strobe output
233
    Inst_btn_debouncer: entity work.grp_debouncer(rtl)
234 22 jdoin
        generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
235 5 jdoin
        port map(
236 10 jdoin
            clk_i => gclk_i,                    -- system clock
237 5 jdoin
            data_i => btn_i,                    -- noisy input data
238 10 jdoin
            data_o => btn_data                  -- registered stable output data
239 12 jdoin
        );
240 5 jdoin
 
241
    --=============================================================================================
242
    --  CONSTANTS CONSTRAINTS CHECKING
243
    --=============================================================================================
244
    -- clock dividers shall not be zero
245 11 jdoin
    assert FSM_CE_DIV > 0
246
    report "Constant 'FSM_CE_DIV' should not be zero"
247 5 jdoin
    severity FAILURE;
248
    -- minimum prefetch lookahead check
249 11 jdoin
    assert SPI_2X_CLK_DIV > 0
250
    report "Constant 'SPI_2X_CLK_DIV' should not be zero"
251 5 jdoin
    severity FAILURE;
252
    -- maximum prefetch lookahead check
253 11 jdoin
    assert SAMP_CE_DIV > 0
254
    report "Constant 'SAMP_CE_DIV' should not be zero"
255 5 jdoin
    severity FAILURE;
256
 
257
    --=============================================================================================
258
    --  CLOCK GENERATION
259
    --=============================================================================================
260 13 jdoin
    -- All registers are clocked directly from the 100MHz system clock.
261
    -- The clock generation block derives 2 clock enable signals, divided down from the 100MHz input 
262
    -- clock. 
263
    --      input sample clock enable, 
264
    --      fsm clock enable,
265 5 jdoin
    -----------------------------------------------------------------------------------------------
266
    -- generate the sampling clock enable from the 100MHz board input clock 
267
    samp_ce_gen_proc: process (gclk_i) is
268
        variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
269
    begin
270
        if gclk_i'event and gclk_i = '1' then
271
            if clk_cnt = SAMP_CE_DIV-1 then
272 13 jdoin
                samp_ce <= '1';                 -- generate a single pulse every SAMP_CE_DIV clocks
273 5 jdoin
                clk_cnt := 0;
274
            else
275
                samp_ce <= '0';
276
                clk_cnt := clk_cnt + 1;
277
            end if;
278
        end if;
279
    end process samp_ce_gen_proc;
280
    -- generate the fsm clock enable from the 100MHz board input clock 
281
    fsm_ce_gen_proc: process (gclk_i) is
282
        variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
283
    begin
284
        if gclk_i'event and gclk_i = '1' then
285
            if clk_cnt = FSM_CE_DIV-1 then
286 13 jdoin
                fsm_ce <= '1';                  -- generate a single pulse every FSM_CE_DIV clocks
287 5 jdoin
                clk_cnt := 0;
288
            else
289
                fsm_ce <= '0';
290
                clk_cnt := clk_cnt + 1;
291
            end if;
292
        end if;
293
    end process fsm_ce_gen_proc;
294
 
295
    --=============================================================================================
296
    -- INPUTS LOGIC
297
    --=============================================================================================
298
    -- registered inputs
299 10 jdoin
    samp_inputs_proc: process (gclk_i) is
300 5 jdoin
    begin
301 10 jdoin
        if gclk_i'event and gclk_i = '1' then
302 5 jdoin
            if samp_ce = '1' then
303 10 jdoin
                clear <= btn_data(btUP);        -- clear is button UP
304 13 jdoin
                leds_reg <= leds_next;          -- update LEDs with spi_slave received data
305 5 jdoin
            end if;
306
        end if;
307
    end process samp_inputs_proc;
308
 
309
    --=============================================================================================
310 10 jdoin
    --  REGISTER TRANSFER PROCESSES
311 5 jdoin
    --=============================================================================================
312 13 jdoin
    -- fsm state and data registers: synchronous to the system clock
313 10 jdoin
    fsm_reg_proc : process (gclk_i) is
314 5 jdoin
    begin
315
        -- FFD registers clocked on rising edge and cleared on sync 'clear'
316 10 jdoin
        if gclk_i'event and gclk_i = '1' then
317 13 jdoin
            if clear = '1' then                     -- sync reset
318
                m_wr_st_reg <= st_reset;            -- only provide local reset for the state registers
319 5 jdoin
            else
320
                if fsm_ce = '1' then
321 13 jdoin
                    m_wr_st_reg <= m_wr_st_next;    -- master write state register update
322 5 jdoin
                end if;
323
            end if;
324
        end if;
325 13 jdoin
        -- FFD registers clocked on rising edge and cleared on ssel = '1'
326
        if gclk_i'event and gclk_i = '1' then
327
            if spi_ssel = '1' then                  -- sync reset
328
                s_wr_st_reg <= st_reset;            -- only provide local reset for the state registers
329
                s_rd_st_reg <= st_reset;
330
            else
331
                if fsm_ce = '1' then
332
                    s_wr_st_reg <= s_wr_st_next;    -- slave write state register update
333
                    s_rd_st_reg <= s_rd_st_next;    -- slave read state register update
334
                end if;
335
            end if;
336
        end if;
337 5 jdoin
        -- FFD registers clocked on rising edge, with no reset
338 10 jdoin
        if gclk_i'event and gclk_i = '1' then
339 5 jdoin
            if fsm_ce = '1' then
340 13 jdoin
                --------- master write fsm signals -----------
341 10 jdoin
                spi_wren_reg_m <= spi_wren_next_m;
342
                spi_di_reg_m <= spi_di_next_m;
343 5 jdoin
                spi_rst_reg <= spi_rst_next;
344
                spi_ssel_reg <= spi_ssel;
345
                sw_reg <= sw_next;
346
                btn_reg <= btn_next;
347 13 jdoin
                --------- slave write fsm signals -----------
348
                spi_wren_reg_s <= spi_wren_next_s;
349
                spi_di_reg_s <= spi_di_next_s;
350
                --------- slave read fsm signals -----------
351
                s_do_1_reg <= s_do_1_next;
352
                s_do_2_reg <= s_do_2_next;
353
                s_do_3_reg <= s_do_3_next;
354 5 jdoin
            end if;
355
        end if;
356
    end process fsm_reg_proc;
357
 
358
    --=============================================================================================
359 10 jdoin
    --  COMBINATORIAL NEXT-STATE LOGIC PROCESSES
360 5 jdoin
    --=============================================================================================
361
    -- edge detector for new switch data
362 22 jdoin
    new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0';     -- '1' for change edge
363 13 jdoin
 
364 5 jdoin
    -- edge detector for new button data
365 22 jdoin
    new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0';   -- '1' for change edge
366 13 jdoin
 
367 22 jdoin
    -- master port write fsmd logic
368 13 jdoin
    fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
369
                                spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
370 20 jdoin
                                new_button, clear) is
371 5 jdoin
    begin
372
        spi_rst_next <= spi_rst_reg;
373 10 jdoin
        spi_di_next_m <= spi_di_reg_m;
374
        spi_wren_next_m <= spi_wren_reg_m;
375 5 jdoin
        sw_next <= sw_reg;
376
        btn_next <= btn_reg;
377 13 jdoin
        m_wr_st_next <= m_wr_st_reg;
378
        case m_wr_st_reg is
379 5 jdoin
            when st_reset =>
380
                spi_rst_next <= '1';                        -- place spi interface on reset
381 10 jdoin
                spi_di_next_m <= (others => '0');           -- clear spi data port
382
                spi_wren_next_m <= '0';                     -- deassert write enable
383 13 jdoin
                m_wr_st_next <= st_wait_spi_idle;
384 5 jdoin
 
385
            when st_wait_spi_idle =>
386 12 jdoin
                spi_wren_next_m <= '0';                     -- remove write strobe on next clock
387 5 jdoin
                if spi_ssel_reg = '1' then
388
                    spi_rst_next <= '0';                    -- remove reset when interface is idle
389 13 jdoin
                    m_wr_st_next <= st_wait_new_switch;
390 5 jdoin
                end if;
391
 
392
            when st_wait_new_switch =>
393
                if new_switch = '1' then                    -- wait for new stable switch data
394
                    sw_next <= sw_data;                     -- load new switch data (end the mismatch condition)
395 13 jdoin
                    m_wr_st_next <= st_send_spi_data_sw;
396 5 jdoin
                elsif new_button = '1' then
397
                    btn_next <= btn_data;                   -- load new button data (end the mismatch condition)
398 20 jdoin
                    if clear = '0' then
399 13 jdoin
                        if btn_data(btDOWN) = '1' then
400
                            m_wr_st_next <= st_send_spi_data_sw;
401
                        elsif btn_data(btLEFT) = '1' then
402
                            m_wr_st_next <= st_send_spi_data_1;
403
                        elsif btn_data(btCENTER) = '1' then
404
                            m_wr_st_next <= st_send_spi_data_1;
405
                        elsif btn_data(btRIGHT) = '1' then
406
                            m_wr_st_next <= st_send_spi_data_1;
407
                        end if;
408 5 jdoin
                    end if;
409
                end if;
410
 
411 13 jdoin
            when st_send_spi_data_sw =>
412 10 jdoin
                spi_di_next_m <= sw_reg;                    -- load switch register to the spi port
413
                spi_wren_next_m <= '1';                     -- write data on next clock
414 13 jdoin
                m_wr_st_next <= st_wait_spi_ack_sw;
415 5 jdoin
 
416 13 jdoin
            when st_wait_spi_ack_sw =>                      -- the actual write happens on this state
417
                if spi_wr_ack_m = '1' then
418
                    spi_wren_next_m <= '0';                 -- remove write strobe on next clock
419
                    m_wr_st_next <= st_wait_spi_di_req_2;
420
                end if;
421
 
422
            when st_send_spi_data_1 =>
423
                spi_di_next_m <= X"A1";                     -- load switch register to the spi port
424
                spi_wren_next_m <= '1';                     -- write data on next clock
425
                m_wr_st_next <= st_wait_spi_ack_1;
426
 
427
            when st_wait_spi_ack_1 =>                       -- the actual write happens on this state
428
                if spi_wr_ack_m = '1' then
429
                    spi_wren_next_m <= '0';                 -- remove write strobe on next clock
430
                    m_wr_st_next <= st_wait_spi_di_req_2;
431
                end if;
432
 
433
            when st_wait_spi_di_req_2 =>
434
                if spi_di_req_m = '1' then
435
                    spi_di_next_m <= X"A2";
436
                    spi_wren_next_m <= '1';
437
                    m_wr_st_next <= st_wait_spi_ack_2;
438
                end if;
439 5 jdoin
 
440 13 jdoin
            when st_wait_spi_ack_2 =>                       -- the actual write happens on this state
441
                if spi_wr_ack_m = '1' then
442
                    spi_wren_next_m <= '0';                 -- remove write strobe on next clock
443
                    m_wr_st_next <= st_wait_spi_di_req_3;
444
                end if;
445
 
446
            when st_wait_spi_di_req_3 =>
447
                if spi_di_req_m = '1' then
448
                    spi_di_next_m <= X"A3";
449
                    spi_wren_next_m <= '1';
450
                    m_wr_st_next <= st_wait_spi_ack_3;
451
                end if;
452
 
453
            when st_wait_spi_ack_3 =>                       -- the actual write happens on this state
454
                if spi_wr_ack_m = '1' then
455
                    spi_wren_next_m <= '0';                 -- remove write strobe on next clock
456
                    m_wr_st_next <= st_wait_spi_idle;       -- wait transmission end
457
                end if;
458
 
459 5 jdoin
            when others =>
460 13 jdoin
                m_wr_st_next <= st_reset;                   -- state st_reset is safe state
461
 
462 5 jdoin
        end case;
463 13 jdoin
    end process fsm_m_wr_combi_proc;
464 5 jdoin
 
465 22 jdoin
    -- slave port write fsmd logic
466 20 jdoin
    fsm_s_wr_combi_proc: process (  s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s,
467 13 jdoin
                                    spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
468
    begin
469
        spi_wren_next_s <= spi_wren_reg_s;
470
        spi_di_next_s <= spi_di_reg_s;
471
        s_wr_st_next <= s_wr_st_reg;
472
        case s_wr_st_reg is
473
            when st_reset =>
474 22 jdoin
                spi_di_next_s <= X"51";                     -- write first data word
475 13 jdoin
                spi_wren_next_s <= '1';                     -- set write enable
476
                s_wr_st_next <= st_wait_spi_start;
477
 
478
            when st_wait_spi_start =>
479
                if spi_ssel_reg = '0' then                  -- wait for slave select
480
                    spi_wren_next_s <= '0';                 -- remove write enable
481
                    s_wr_st_next <= st_wait_spi_di_req_2;
482
                end if;
483
 
484
            when st_wait_spi_di_req_2 =>
485
                if spi_di_req_s = '1' then
486 20 jdoin
--                    spi_di_next_s <= X"D2";               -- do not write on this cycle (cycle miss)
487
--                    spi_wren_next_s <= '1';
488 22 jdoin
--                    s_wr_st_next <= st_wait_spi_ack_2;
489 20 jdoin
                    s_wr_st_next <= st_wait_spi_do_valid_1;
490 13 jdoin
                end if;
491
 
492
            when st_wait_spi_ack_2 =>                       -- the actual write happens on this state
493
                if spi_wr_ack_s = '1' then
494
                    spi_wren_next_s <= '0';                 -- remove write strobe on next clock
495
                    s_wr_st_next <= st_wait_spi_di_req_3;
496
                end if;
497
 
498 20 jdoin
            when st_wait_spi_do_valid_1 =>
499
                if spi_do_valid_s = '1' then
500
                    s_wr_st_next <= st_wait_spi_di_req_3;
501
                end if;
502
 
503 13 jdoin
            when st_wait_spi_di_req_3 =>
504
                if spi_di_req_s = '1' then
505
                    spi_di_next_s <= X"D3";
506
                    spi_wren_next_s <= '1';
507
                    s_wr_st_next <= st_wait_spi_ack_3;
508
                end if;
509
 
510
            when st_wait_spi_ack_3 =>                       -- the actual write happens on this state
511
                if spi_wr_ack_s = '1' then
512
                    spi_wren_next_s <= '0';                 -- remove write strobe on next clock
513
                    s_wr_st_next <= st_wait_spi_end;        -- wait transmission end
514
                end if;
515
 
516
            when st_wait_spi_end =>                         -- wait interface to be deselected
517
                if spi_ssel_reg = '1' then
518
                    s_wr_st_next <= st_reset;               -- wait transmission start
519
                end if;
520
 
521
            when others =>
522
                s_wr_st_next <= st_reset;                   -- state st_reset is safe state
523
 
524
        end case;
525
    end process fsm_s_wr_combi_proc;
526
 
527 22 jdoin
    -- slave port read fsmd logic
528 13 jdoin
    fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
529
    begin
530
        s_do_1_next <= s_do_1_reg;
531
        s_do_2_next <= s_do_2_reg;
532
        s_do_3_next <= s_do_3_reg;
533
        s_rd_st_next <= s_rd_st_reg;
534
        case s_rd_st_reg is
535
            when st_reset =>
536
                s_rd_st_next <= st_wait_spi_do_valid_1;
537
 
538
            when st_wait_spi_do_valid_1 =>
539
                if spi_do_valid_s = '1' then                -- wait for receive data ready
540
                    s_do_1_next <= spi_do_s;                -- read data from output port
541
                    s_rd_st_next <= st_wait_spi_n_do_valid_1;
542
                end if;
543
 
544
            when st_wait_spi_n_do_valid_1 =>
545
                if spi_do_valid_s = '0' then
546
                    s_rd_st_next <= st_wait_spi_do_valid_2;
547
                end if;
548
 
549
            when st_wait_spi_do_valid_2 =>
550
                if spi_do_valid_s = '1' then                -- wait for receive data ready
551
                    s_do_2_next <= spi_do_s;                -- read data from output port
552
                    s_rd_st_next <= st_wait_spi_n_do_valid_2;
553
                end if;
554
 
555
            when st_wait_spi_n_do_valid_2 =>
556
                if spi_do_valid_s = '0' then
557
                    s_rd_st_next <= st_wait_spi_do_valid_3;
558
                end if;
559
 
560
            when st_wait_spi_do_valid_3 =>
561
                if spi_do_valid_s = '1' then                -- wait for receive data ready
562
                    s_do_3_next <= spi_do_s;                -- read data from output port
563
                    s_rd_st_next <= st_wait_spi_n_do_valid_3;
564
                end if;
565
 
566
            when st_wait_spi_n_do_valid_3 =>
567
                if spi_do_valid_s = '0' then
568
                    s_rd_st_next <= st_reset;
569
                end if;
570
 
571
            when others =>
572
                s_rd_st_next <= st_reset;                   -- state st_reset is safe state
573
 
574
        end case;
575
    end process fsm_s_rd_combi_proc;
576
 
577
    leds_combi_proc: process (btn_data, leds_reg, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
578
    begin
579
        leds_next <= leds_reg;
580
        if btn_data(btRIGHT) = '1' then
581
            leds_next <= s_do_3_reg;
582
        elsif btn_data(btCENTER) = '1' then
583
            leds_next <= s_do_2_reg;
584
        elsif btn_data(btLEFT) = '1' then
585
            leds_next <= s_do_1_reg;
586
        elsif btn_data(btDOWN) = '1' then
587
            leds_next <= s_do_1_reg;
588
        end if;
589
    end process leds_combi_proc;
590
 
591 5 jdoin
    --=============================================================================================
592
    --  OUTPUT LOGIC PROCESSES
593
    --=============================================================================================
594
    -- connect the spi output wires
595 10 jdoin
    spi_ssel_o_proc:        spi_ssel_o      <= spi_ssel;
596
    spi_sck_o_proc:         spi_sck_o       <= spi_sck;
597
    spi_mosi_o_proc:        spi_mosi_o      <= spi_mosi;
598
    spi_miso_o_proc:        spi_miso_o      <= spi_miso;
599 12 jdoin
    -- connect leds_reg signal to LED outputs
600 13 jdoin
    led_o_proc:             led_o           <= leds_reg;
601 5 jdoin
 
602
    --=============================================================================================
603
    --  DEBUG LOGIC PROCESSES
604
    --=============================================================================================
605
    -- connect the debug vector outputs
606 10 jdoin
    dbg_o_proc:             dbg_o <= dbg;
607 13 jdoin
 
608
    -- connect debug port pins to spi ports instances interface signals
609
    -- master signals mapped on dbg
610
    dbg(11) <= spi_wren_reg_m;
611
    dbg(10) <= spi_wr_ack_m;
612
    dbg(9)  <= spi_di_req_m;
613
    dbg(8)  <= spi_do_valid_m;
614
    -- slave signals mapped on dbg
615
    dbg(7)  <= spi_wren_reg_s;
616
    dbg(6)  <= spi_wr_ack_s;
617
    dbg(5)  <= spi_di_req_s;
618
    dbg(4)  <= spi_do_valid_s;
619 22 jdoin
    dbg(3 downto 0) <= spi_state_s;
620 20 jdoin
    -- specific ports to test on testbench
621
    s_do_o <= spi_do_s;
622
    m_do_o <= spi_do_m;
623
    m_state_o <= spi_state_m;  -- master spi fsm state
624
    s_state_o <= spi_state_s;  -- slave spi fsm state
625 10 jdoin
 
626 22 jdoin
end rtl;
627 5 jdoin
 

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