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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.mrp] - Blame information for rev 22

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1 20 jdoin
Release 13.1 Map O.40d (nt)
2
Xilinx Mapping Report File for Design 'spi_master_atlys_top'
3
 
4
Design Information
5
------------------
6
Command Line   : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
7
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
8
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
9
off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
10
spi_master_atlys_top.pcf
11
Target Device  : xc6slx45
12
Target Package : csg324
13
Target Speed   : -2
14
Mapper Version : spartan6 -- $Revision: 1.55 $
15 22 jdoin
Mapped Date    : Mon Aug 29 00:08:18 2011
16 20 jdoin
 
17
Design Summary
18
--------------
19
Number of errors:      0
20
Number of warnings:    0
21
Slice Logic Utilization:
22 22 jdoin
  Number of Slice Registers:                   224 out of  54,576    1%
23
    Number used as Flip Flops:                 224
24 20 jdoin
    Number used as Latches:                      0
25
    Number used as Latch-thrus:                  0
26
    Number used as AND/OR logics:                0
27 22 jdoin
  Number of Slice LUTs:                        177 out of  27,288    1%
28
    Number used as logic:                      167 out of  27,288    1%
29
      Number using O6 output only:             112
30
      Number using O5 output only:              28
31
      Number using O5 and O6:                   27
32 20 jdoin
      Number used as ROM:                        0
33
    Number used as Memory:                       4 out of   6,408    1%
34
      Number used as Dual Port RAM:              0
35
      Number used as Single Port RAM:            0
36
      Number used as Shift Register:             4
37
        Number using O6 output only:             4
38
        Number using O5 output only:             0
39
        Number using O5 and O6:                  0
40 22 jdoin
    Number used exclusively as route-thrus:      6
41
      Number with same-slice register load:      4
42 20 jdoin
      Number with same-slice carry load:         2
43
      Number with other load:                    0
44
 
45
Slice Logic Distribution:
46 22 jdoin
  Number of occupied Slices:                   102 out of   6,822    1%
47
  Number of LUT Flip Flop pairs used:          272
48
    Number with an unused Flip Flop:            64 out of     272   23%
49
    Number with an unused LUT:                  95 out of     272   34%
50
    Number of fully used LUT-FF pairs:         113 out of     272   41%
51
    Number of unique control sets:              26
52 20 jdoin
    Number of slice register sites lost
53 22 jdoin
      to control set restrictions:              68 out of  54,576    1%
54 20 jdoin
 
55
  A LUT Flip Flop pair for this architecture represents one LUT paired with
56
  one Flip Flop within a slice.  A control set is a unique combination of
57
  clock, reset, set, and enable signals for a registered element.
58
  The Slice Logic Distribution report is not meaningful if the design is
59
  over-mapped for a non-slice resource or if Placement fails.
60
 
61
IO Utilization:
62
  Number of bonded IOBs:                        63 out of     218   28%
63 22 jdoin
    Number of LOCed IOBs:                       47 out of      63   74%
64 20 jdoin
 
65
Specific Feature Utilization:
66
  Number of RAMB16BWERs:                         0 out of     116    0%
67
  Number of RAMB8BWERs:                          0 out of     232    0%
68
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
69
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
70
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
71
    Number used as BUFGs:                        2
72
    Number used as BUFGMUX:                      0
73
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
74
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
75
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
76
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
77
  Number of BSCANs:                              0 out of       4    0%
78
  Number of BUFHs:                               0 out of     256    0%
79
  Number of BUFPLLs:                             0 out of       8    0%
80
  Number of BUFPLL_MCBs:                         0 out of       4    0%
81
  Number of DSP48A1s:                            0 out of      58    0%
82
  Number of ICAPs:                               0 out of       1    0%
83
  Number of MCBs:                                0 out of       2    0%
84
  Number of PCILOGICSEs:                         0 out of       2    0%
85
  Number of PLL_ADVs:                            0 out of       4    0%
86
  Number of PMVs:                                0 out of       1    0%
87
  Number of STARTUPs:                            0 out of       1    0%
88
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
89
 
90 22 jdoin
Average Fanout of Non-Clock Nets:                3.18
91 20 jdoin
 
92 22 jdoin
Peak Memory Usage:  298 MB
93
Total REAL time to MAP completion:  17 secs
94 20 jdoin
Total CPU time to MAP completion (all processors):   17 secs
95
 
96
Table of Contents
97
-----------------
98
Section 1 - Errors
99
Section 2 - Warnings
100
Section 3 - Informational
101
Section 4 - Removed Logic Summary
102
Section 5 - Removed Logic
103
Section 6 - IOB Properties
104
Section 7 - RPMs
105
Section 8 - Guide Report
106
Section 9 - Area Group and Partition Summary
107
Section 10 - Timing Report
108
Section 11 - Configuration String Information
109
Section 12 - Control Set Information
110
Section 13 - Utilization by Hierarchy
111
 
112
Section 1 - Errors
113
------------------
114
 
115
Section 2 - Warnings
116
--------------------
117
 
118
Section 3 - Informational
119
-------------------------
120
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
121
   supports the use of up to 2 processors. Based on the the user options and
122
   machine load, Map will use 2 processors during this run.
123
INFO:Xst:2261 - The FF/Latch  in Unit
124
    is equivalent to the following FF/Latch, which will be
125
   removed : 
126
INFO:Xst:2261 - The FF/Latch  in Unit
127
    is equivalent to the following FF/Latch, which will be
128
   removed : 
129
INFO:Xst:2261 - The FF/Latch  in Unit
130
    is equivalent to the following 2 FFs/Latches, which
131
   will be removed : 
132
   
133
INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
134
INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
135
INFO:MapLib:562 - No environment variables are currently set.
136
INFO:LIT:244 - All of the single ended outputs in this design are using slew
137
   rate limited output drivers. The delay on speed critical single ended outputs
138
   can be dramatically reduced by designating them as fast outputs.
139
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
140
   0.000 to 85.000 Celsius)
141
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
142
   1.260 Volts)
143
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
144
   (.mrp).
145 22 jdoin
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
146
   and 16 are not locked. If you would like to print the names of these IOs,
147 20 jdoin
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
148
INFO:Pack:1650 - Map created a placed design.
149
 
150
Section 4 - Removed Logic Summary
151
---------------------------------
152
   2 block(s) removed
153
   2 block(s) optimized away
154
   2 signal(s) removed
155 22 jdoin
  87 Block(s) redundant
156 20 jdoin
 
157
Section 5 - Removed Logic
158
-------------------------
159
 
160
The trimmed logic report below shows the logic removed from your design due to
161
sourceless or loadless signals, and VCC or ground connections.  If the removal
162
of a signal or symbol results in the subsequent removal of an additional signal
163
or symbol, the message explaining that second removal will be indented.  This
164
indentation will be repeated as a chain of related logic is removed.
165
 
166
To quickly locate the original cause for the removal of a chain of logic, look
167
above the place where that logic is listed in the trimming report, then locate
168
the lines that are least indented (begin at the leftmost edge).
169
 
170
The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
171
The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
172
Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
173
Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
174
 
175
Optimized Block(s):
176
TYPE            BLOCK
177
GND             XST_GND
178
VCC             XST_VCC
179
 
180
Redundant Block(s):
181
TYPE            BLOCK
182 22 jdoin
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<13>_rt
183
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<12>_rt
184
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
185
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
186
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
187
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
188
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
189 20 jdoin
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
190
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
191
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
192
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
193
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
194
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
195 22 jdoin
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<13>_rt
196
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<12>_rt
197
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<11>_rt
198
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<10>_rt
199
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<9>_rt
200
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<8>_rt
201
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<7>_rt
202 20 jdoin
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
203
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
204
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
205
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
206
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
207
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
208 22 jdoin
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_xor<14>_rt
209
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_xor<14>_rt
210
INV             ][1211_3_INV_0
211
INV             ][1212_5_INV_0
212
INV             ][335_42_INV_0
213
INV             ][339_50_INV_0
214
INV             ][343_55_INV_0
215
INV             ][347_60_INV_0
216
INV             ][351_65_INV_0
217
INV             ][355_70_INV_0
218
INV             ][359_75_INV_0
219
INV             ][363_80_INV_0
220
INV             ][395_115_INV_0
221
INV             ][495_170_INV_0
222
INV             ][496_174_INV_0
223
INV             ][499_176_INV_0
224
INV             ][515_193_INV_0
225
INV             ][523_202_INV_0
226
INV             ][527_207_INV_0
227
INV             ][528_211_INV_0
228
INV             ][531_213_INV_0
229
INV             ][535_218_INV_0
230
INV             ][539_223_INV_0
231
INV             ][543_228_INV_0
232
INV             ][547_233_INV_0
233
INV             ][551_238_INV_0
234
INV             ][555_243_INV_0
235
INV             ][563_253_INV_0
236
INV             ][567_257_INV_0
237
INV             ][575_264_INV_0
238
INV             ][579_268_INV_0
239
INV             ][583_272_INV_0
240
INV             ][587_276_INV_0
241
INV             ][591_280_INV_0
242
INV             ][595_284_INV_0
243
INV             ][771_395_INV_0
244
INV             ][775_400_INV_0
245
INV             ][779_404_INV_0
246
INV             ][783_408_INV_0
247
INV             ][787_412_INV_0
248
INV             ][791_416_INV_0
249
INV             ][795_420_INV_0
250
INV             ][799_424_INV_0
251
INV             ][820_439_INV_0
252
INV             ][825_443_INV_0
253
INV             ][855_466_INV_0
254
INV             ][859_471_INV_0
255
INV             ][909_508_INV_0
256
INV             ][917_517_INV_0
257
INV             ][921_521_INV_0
258
INV             ][925_527_INV_0
259
INV             ][933_533_INV_0
260
INV             ][966_562_INV_0
261
INV             ][971_565_INV_0
262
INV             ][1008_588_INV_0
263
INV             ][1011_592_INV_0
264
INV             ][1014_596_INV_0
265
INV             ][1042_616_INV_0
266
INV             ][1051_628_INV_0
267
INV             ][1054_632_INV_0
268
INV             ][1057_636_INV_0
269 20 jdoin
 
270
Section 6 - IOB Properties
271
--------------------------
272
 
273
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
274
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
275
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
276
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
277
| btn_i<0>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
278
| btn_i<1>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
279
| btn_i<2>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
280
| btn_i<3>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
281
| btn_i<4>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
282
| btn_i<5>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
283
| dbg_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
284
| dbg_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
285
| dbg_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
286
| dbg_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
287
| dbg_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
288
| dbg_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
289
| dbg_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
290
| dbg_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
291
| dbg_o<8>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
292
| dbg_o<9>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
293
| dbg_o<10>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
294
| dbg_o<11>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
295
| gclk_i                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
296
| led_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
297
| led_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
298
| led_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
299
| led_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
300
| led_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
301
| led_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
302
| led_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
303
| led_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
304
| m_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
305
| m_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
306
| m_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
307
| m_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
308
| m_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
309
| m_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
310
| m_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
311
| m_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
312
| m_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
313
| m_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
314
| m_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
315
| m_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
316
| s_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
317
| s_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
318
| s_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
319
| s_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
320
| s_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
321
| s_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
322
| s_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
323
| s_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
324
| s_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
325
| s_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
326
| s_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
327
| s_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
328
| spi_miso_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
329
| spi_mosi_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
330
| spi_sck_o                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
331
| spi_ssel_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
332
| sw_i<0>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
333
| sw_i<1>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
334
| sw_i<2>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
335
| sw_i<3>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
336
| sw_i<4>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
337
| sw_i<5>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
338
| sw_i<6>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
339
| sw_i<7>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
340
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
341
 
342
Section 7 - RPMs
343
----------------
344
 
345
Section 8 - Guide Report
346
------------------------
347
Guide not run on this design.
348
 
349
Section 9 - Area Group and Partition Summary
350
--------------------------------------------
351
 
352
Partition Implementation Status
353
-------------------------------
354
 
355
  No Partitions were found in this design.
356
 
357
-------------------------------
358
 
359
Area Group Information
360
----------------------
361
 
362
  No area groups were found in this design.
363
 
364
----------------------
365
 
366
Section 10 - Timing Report
367
--------------------------
368
A logic-level (pre-route) timing report can be generated by using Xilinx static
369
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
370
mapped NCD and PCF files. Please note that this timing report will be generated
371
using estimated delay information. For accurate numbers, please generate a
372
timing report with the post Place and Route NCD file.
373
 
374
For more information about the Timing Analyzer, consult the Xilinx Timing
375
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
376
Command Line Tools User Guide "TRACE" chapter.
377
 
378
Section 11 - Configuration String Details
379
-----------------------------------------
380
 
381
Section 12 - Control Set Information
382
------------------------------------
383
+-----------------------------------------------------------------------------------------------------------------------------------+
384
| Clock Signal                           | Reset Signal           | Set Signal | Enable Signal  | Slice Load Count | Bel Load Count |
385
+-----------------------------------------------------------------------------------------------------------------------------------+
386
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            |                | 6                | 11             |
387 22 jdoin
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            | lut1117_506    | 3                | 8              |
388
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][1209_0               |            |                | 2                | 2              |
389
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][IN_virtPIBox_574_736 |            |                | 1                | 2              |
390 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
391 22 jdoin
| gclk_i_BUFGP                           |                        |            |                | 36               | 85             |
392 20 jdoin
| gclk_i_BUFGP                           |                        |            | GLOBAL_LOGIC1  | 1                | 4              |
393 22 jdoin
| gclk_i_BUFGP                           |                        |            | ][336_48       | 2                | 8              |
394
| gclk_i_BUFGP                           |                        |            | ][496_174      | 2                | 8              |
395
| gclk_i_BUFGP                           |                        |            | ][528_211      | 2                | 8              |
396
| gclk_i_BUFGP                           |                        |            | ][817_437      | 3                | 4              |
397
| gclk_i_BUFGP                           |                        |            | lut263_47      | 2                | 6              |
398
| gclk_i_BUFGP                           |                        |            | lut350_113     | 1                | 2              |
399
| gclk_i_BUFGP                           |                        |            | lut362_120     | 2                | 8              |
400
| gclk_i_BUFGP                           |                        |            | lut403_137     | 2                | 8              |
401
| gclk_i_BUFGP                           |                        |            | lut444_154     | 2                | 8              |
402
| gclk_i_BUFGP                           |                        |            | lut649_291     | 2                | 8              |
403
| gclk_i_BUFGP                           |                        |            | lut772_342     | 2                | 6              |
404
| gclk_i_BUFGP                           |                        |            | lut863_379     | 2                | 8              |
405
| gclk_i_BUFGP                           |                        |            | lut905_398     | 3                | 8              |
406
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_m | 2                | 8              |
407 20 jdoin
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_s | 1                | 2              |
408 22 jdoin
| gclk_i_BUFGP                           | ][1209_0               |            |                | 2                | 6              |
409 20 jdoin
| gclk_i_BUFGP                           | clear                  |            |                | 2                | 4              |
410 22 jdoin
| gclk_i_BUFGP                           | spi_rst_reg            |            | ][817_437      | 1                | 4              |
411 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
412
| ~Inst_spi_master_port/spi_clk_reg_BUFG |                        |            |                | 1                | 1              |
413 22 jdoin
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0               |            |                | 1                | 1              |
414 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
415
 
416
Section 13 - Utilization by Hierarchy
417
-------------------------------------
418
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
419
| Module                | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name                     |
420
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
421 22 jdoin
| spi_master_atlys_top/ |           | 68/139        | 71/224        | 135/145       | 0/4           | 0/0       | 0/0     | 1/2   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top                       |
422
| +Inst_btn_debouncer   |           | 14/14         | 33/33         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_btn_debouncer    |
423
| +Inst_spi_master_port |           | 21/21         | 45/45         | 2/2           | 2/2           | 0/0       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_master_port  |
424
| +Inst_spi_slave_port  |           | 23/23         | 36/36         | 6/6           | 2/2           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_slave_port   |
425
| +Inst_sw_debouncer    |           | 13/13         | 39/39         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_sw_debouncer     |
426 20 jdoin
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
427
 
428
* Slices can be packed with basic elements from multiple hierarchies.
429
  Therefore, a slice will be counted in every hierarchical module
430
  that each of its packed basic elements belong to.
431
** For each column, there are two numbers reported /.
432
    is the number of elements that belong to that specific hierarchical module.
433
    is the total number of elements from that hierarchical module and any lower level
434
   hierarchical modules below.
435
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

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