OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_summary.html] - Blame information for rev 20

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1 20 jdoin
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status (08/10/2011 - 22:59:24)</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8
<TD>spi_ms_atlys.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10
<TD> No Errors </TD>
11
</TR>
12
<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14
<TD>spi_master_atlys_top</TD>
15
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16
<TD>Programming File Generated</TD>
17
</TR>
18
<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20
<TD>xc6slx45-2csg324</TD>
21
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22
<TD>
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No Errors</TD>
24
</TR>
25
<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
27
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
28
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/*.xmsgs?&DataKey=Warning'>30 Warnings (30 new)</A></TD>
29
</TR>
30
<TR ALIGN=LEFT>
31
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
32
<TD>Balanced</TD>
33
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
34
<TD>
35
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
36
</TR>
37
<TR ALIGN=LEFT>
38
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
39
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
40
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
41
<TD>
42
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
43
</TR>
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<TR ALIGN=LEFT>
45
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
46
<TD>
47
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_envsettings.html'>
48
System Settings</A>
49
</TD>
50
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
51
<TD>0 &nbsp;<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
52
</TR>
53
</TABLE>
54
 
55
 
56
 
57
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
58
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
59
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
61
</TR>
62
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
63
<TD ALIGN=RIGHT>209</TD>
64
<TD ALIGN=RIGHT>54,576</TD>
65
<TD ALIGN=RIGHT>1%</TD>
66
<TD COLSPAN='2'>&nbsp;</TD>
67
</TR>
68
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
69
<TD ALIGN=RIGHT>209</TD>
70
<TD>&nbsp;</TD>
71
<TD>&nbsp;</TD>
72
<TD COLSPAN='2'>&nbsp;</TD>
73
</TR>
74
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
75
<TD ALIGN=RIGHT>0</TD>
76
<TD>&nbsp;</TD>
77
<TD>&nbsp;</TD>
78
<TD COLSPAN='2'>&nbsp;</TD>
79
</TR>
80
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
81
<TD ALIGN=RIGHT>0</TD>
82
<TD>&nbsp;</TD>
83
<TD>&nbsp;</TD>
84
<TD COLSPAN='2'>&nbsp;</TD>
85
</TR>
86
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
87
<TD ALIGN=RIGHT>0</TD>
88
<TD>&nbsp;</TD>
89
<TD>&nbsp;</TD>
90
<TD COLSPAN='2'>&nbsp;</TD>
91
</TR>
92
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
93
<TD ALIGN=RIGHT>145</TD>
94
<TD ALIGN=RIGHT>27,288</TD>
95
<TD ALIGN=RIGHT>1%</TD>
96
<TD COLSPAN='2'>&nbsp;</TD>
97
</TR>
98
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
99
<TD ALIGN=RIGHT>127</TD>
100
<TD ALIGN=RIGHT>27,288</TD>
101
<TD ALIGN=RIGHT>1%</TD>
102
<TD COLSPAN='2'>&nbsp;</TD>
103
</TR>
104
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
105
<TD ALIGN=RIGHT>75</TD>
106
<TD>&nbsp;</TD>
107
<TD>&nbsp;</TD>
108
<TD COLSPAN='2'>&nbsp;</TD>
109
</TR>
110
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
111
<TD ALIGN=RIGHT>13</TD>
112
<TD>&nbsp;</TD>
113
<TD>&nbsp;</TD>
114
<TD COLSPAN='2'>&nbsp;</TD>
115
</TR>
116
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
117
<TD ALIGN=RIGHT>39</TD>
118
<TD>&nbsp;</TD>
119
<TD>&nbsp;</TD>
120
<TD COLSPAN='2'>&nbsp;</TD>
121
</TR>
122
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
123
<TD ALIGN=RIGHT>0</TD>
124
<TD>&nbsp;</TD>
125
<TD>&nbsp;</TD>
126
<TD COLSPAN='2'>&nbsp;</TD>
127
</TR>
128
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
129
<TD ALIGN=RIGHT>4</TD>
130
<TD ALIGN=RIGHT>6,408</TD>
131
<TD ALIGN=RIGHT>1%</TD>
132
<TD COLSPAN='2'>&nbsp;</TD>
133
</TR>
134
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
135
<TD ALIGN=RIGHT>0</TD>
136
<TD>&nbsp;</TD>
137
<TD>&nbsp;</TD>
138
<TD COLSPAN='2'>&nbsp;</TD>
139
</TR>
140
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
141
<TD ALIGN=RIGHT>0</TD>
142
<TD>&nbsp;</TD>
143
<TD>&nbsp;</TD>
144
<TD COLSPAN='2'>&nbsp;</TD>
145
</TR>
146
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
147
<TD ALIGN=RIGHT>4</TD>
148
<TD>&nbsp;</TD>
149
<TD>&nbsp;</TD>
150
<TD COLSPAN='2'>&nbsp;</TD>
151
</TR>
152
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
153
<TD ALIGN=RIGHT>4</TD>
154
<TD>&nbsp;</TD>
155
<TD>&nbsp;</TD>
156
<TD COLSPAN='2'>&nbsp;</TD>
157
</TR>
158
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
159
<TD ALIGN=RIGHT>0</TD>
160
<TD>&nbsp;</TD>
161
<TD>&nbsp;</TD>
162
<TD COLSPAN='2'>&nbsp;</TD>
163
</TR>
164
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
165
<TD ALIGN=RIGHT>0</TD>
166
<TD>&nbsp;</TD>
167
<TD>&nbsp;</TD>
168
<TD COLSPAN='2'>&nbsp;</TD>
169
</TR>
170
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
171
<TD ALIGN=RIGHT>14</TD>
172
<TD>&nbsp;</TD>
173
<TD>&nbsp;</TD>
174
<TD COLSPAN='2'>&nbsp;</TD>
175
</TR>
176
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
177
<TD ALIGN=RIGHT>12</TD>
178
<TD>&nbsp;</TD>
179
<TD>&nbsp;</TD>
180
<TD COLSPAN='2'>&nbsp;</TD>
181
</TR>
182
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
183
<TD ALIGN=RIGHT>2</TD>
184
<TD>&nbsp;</TD>
185
<TD>&nbsp;</TD>
186
<TD COLSPAN='2'>&nbsp;</TD>
187
</TR>
188
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
189
<TD ALIGN=RIGHT>0</TD>
190
<TD>&nbsp;</TD>
191
<TD>&nbsp;</TD>
192
<TD COLSPAN='2'>&nbsp;</TD>
193
</TR>
194
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
195
<TD ALIGN=RIGHT>91</TD>
196
<TD ALIGN=RIGHT>6,822</TD>
197
<TD ALIGN=RIGHT>1%</TD>
198
<TD COLSPAN='2'>&nbsp;</TD>
199
</TR>
200
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
201
<TD ALIGN=RIGHT>225</TD>
202
<TD>&nbsp;</TD>
203
<TD>&nbsp;</TD>
204
<TD COLSPAN='2'>&nbsp;</TD>
205
</TR>
206
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
207
<TD ALIGN=RIGHT>49</TD>
208
<TD ALIGN=RIGHT>225</TD>
209
<TD ALIGN=RIGHT>21%</TD>
210
<TD COLSPAN='2'>&nbsp;</TD>
211
</TR>
212
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
213
<TD ALIGN=RIGHT>80</TD>
214
<TD ALIGN=RIGHT>225</TD>
215
<TD ALIGN=RIGHT>35%</TD>
216
<TD COLSPAN='2'>&nbsp;</TD>
217
</TR>
218
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
219
<TD ALIGN=RIGHT>96</TD>
220
<TD ALIGN=RIGHT>225</TD>
221
<TD ALIGN=RIGHT>42%</TD>
222
<TD COLSPAN='2'>&nbsp;</TD>
223
</TR>
224
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
225
<TD ALIGN=RIGHT>25</TD>
226
<TD>&nbsp;</TD>
227
<TD>&nbsp;</TD>
228
<TD COLSPAN='2'>&nbsp;</TD>
229
</TR>
230
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
231
<TD ALIGN=RIGHT>59</TD>
232
<TD ALIGN=RIGHT>54,576</TD>
233
<TD ALIGN=RIGHT>1%</TD>
234
<TD COLSPAN='2'>&nbsp;</TD>
235
</TR>
236
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
237
<TD ALIGN=RIGHT>63</TD>
238
<TD ALIGN=RIGHT>218</TD>
239
<TD ALIGN=RIGHT>28%</TD>
240
<TD COLSPAN='2'>&nbsp;</TD>
241
</TR>
242
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
243
<TD ALIGN=RIGHT>43</TD>
244
<TD ALIGN=RIGHT>63</TD>
245
<TD ALIGN=RIGHT>68%</TD>
246
<TD COLSPAN='2'>&nbsp;</TD>
247
</TR>
248
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
249
<TD ALIGN=RIGHT>0</TD>
250
<TD ALIGN=RIGHT>116</TD>
251
<TD ALIGN=RIGHT>0%</TD>
252
<TD COLSPAN='2'>&nbsp;</TD>
253
</TR>
254
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
255
<TD ALIGN=RIGHT>0</TD>
256
<TD ALIGN=RIGHT>232</TD>
257
<TD ALIGN=RIGHT>0%</TD>
258
<TD COLSPAN='2'>&nbsp;</TD>
259
</TR>
260
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
261
<TD ALIGN=RIGHT>0</TD>
262
<TD ALIGN=RIGHT>32</TD>
263
<TD ALIGN=RIGHT>0%</TD>
264
<TD COLSPAN='2'>&nbsp;</TD>
265
</TR>
266
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
267
<TD ALIGN=RIGHT>0</TD>
268
<TD ALIGN=RIGHT>32</TD>
269
<TD ALIGN=RIGHT>0%</TD>
270
<TD COLSPAN='2'>&nbsp;</TD>
271
</TR>
272
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
273
<TD ALIGN=RIGHT>2</TD>
274
<TD ALIGN=RIGHT>16</TD>
275
<TD ALIGN=RIGHT>12%</TD>
276
<TD COLSPAN='2'>&nbsp;</TD>
277
</TR>
278
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
279
<TD ALIGN=RIGHT>2</TD>
280
<TD>&nbsp;</TD>
281
<TD>&nbsp;</TD>
282
<TD COLSPAN='2'>&nbsp;</TD>
283
</TR>
284
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
285
<TD ALIGN=RIGHT>0</TD>
286
<TD>&nbsp;</TD>
287
<TD>&nbsp;</TD>
288
<TD COLSPAN='2'>&nbsp;</TD>
289
</TR>
290
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
291
<TD ALIGN=RIGHT>0</TD>
292
<TD ALIGN=RIGHT>8</TD>
293
<TD ALIGN=RIGHT>0%</TD>
294
<TD COLSPAN='2'>&nbsp;</TD>
295
</TR>
296
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
297
<TD ALIGN=RIGHT>0</TD>
298
<TD ALIGN=RIGHT>376</TD>
299
<TD ALIGN=RIGHT>0%</TD>
300
<TD COLSPAN='2'>&nbsp;</TD>
301
</TR>
302
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
303
<TD ALIGN=RIGHT>0</TD>
304
<TD ALIGN=RIGHT>376</TD>
305
<TD ALIGN=RIGHT>0%</TD>
306
<TD COLSPAN='2'>&nbsp;</TD>
307
</TR>
308
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
309
<TD ALIGN=RIGHT>0</TD>
310
<TD ALIGN=RIGHT>376</TD>
311
<TD ALIGN=RIGHT>0%</TD>
312
<TD COLSPAN='2'>&nbsp;</TD>
313
</TR>
314
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
315
<TD ALIGN=RIGHT>0</TD>
316
<TD ALIGN=RIGHT>4</TD>
317
<TD ALIGN=RIGHT>0%</TD>
318
<TD COLSPAN='2'>&nbsp;</TD>
319
</TR>
320
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
321
<TD ALIGN=RIGHT>0</TD>
322
<TD ALIGN=RIGHT>256</TD>
323
<TD ALIGN=RIGHT>0%</TD>
324
<TD COLSPAN='2'>&nbsp;</TD>
325
</TR>
326
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
327
<TD ALIGN=RIGHT>0</TD>
328
<TD ALIGN=RIGHT>8</TD>
329
<TD ALIGN=RIGHT>0%</TD>
330
<TD COLSPAN='2'>&nbsp;</TD>
331
</TR>
332
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
333
<TD ALIGN=RIGHT>0</TD>
334
<TD ALIGN=RIGHT>4</TD>
335
<TD ALIGN=RIGHT>0%</TD>
336
<TD COLSPAN='2'>&nbsp;</TD>
337
</TR>
338
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
339
<TD ALIGN=RIGHT>0</TD>
340
<TD ALIGN=RIGHT>58</TD>
341
<TD ALIGN=RIGHT>0%</TD>
342
<TD COLSPAN='2'>&nbsp;</TD>
343
</TR>
344
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
345
<TD ALIGN=RIGHT>0</TD>
346
<TD ALIGN=RIGHT>1</TD>
347
<TD ALIGN=RIGHT>0%</TD>
348
<TD COLSPAN='2'>&nbsp;</TD>
349
</TR>
350
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
351
<TD ALIGN=RIGHT>0</TD>
352
<TD ALIGN=RIGHT>2</TD>
353
<TD ALIGN=RIGHT>0%</TD>
354
<TD COLSPAN='2'>&nbsp;</TD>
355
</TR>
356
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
357
<TD ALIGN=RIGHT>0</TD>
358
<TD ALIGN=RIGHT>2</TD>
359
<TD ALIGN=RIGHT>0%</TD>
360
<TD COLSPAN='2'>&nbsp;</TD>
361
</TR>
362
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
363
<TD ALIGN=RIGHT>0</TD>
364
<TD ALIGN=RIGHT>4</TD>
365
<TD ALIGN=RIGHT>0%</TD>
366
<TD COLSPAN='2'>&nbsp;</TD>
367
</TR>
368
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
369
<TD ALIGN=RIGHT>0</TD>
370
<TD ALIGN=RIGHT>1</TD>
371
<TD ALIGN=RIGHT>0%</TD>
372
<TD COLSPAN='2'>&nbsp;</TD>
373
</TR>
374
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
375
<TD ALIGN=RIGHT>0</TD>
376
<TD ALIGN=RIGHT>1</TD>
377
<TD ALIGN=RIGHT>0%</TD>
378
<TD COLSPAN='2'>&nbsp;</TD>
379
</TR>
380
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
381
<TD ALIGN=RIGHT>0</TD>
382
<TD ALIGN=RIGHT>1</TD>
383
<TD ALIGN=RIGHT>0%</TD>
384
<TD COLSPAN='2'>&nbsp;</TD>
385
</TR>
386
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
387
<TD ALIGN=RIGHT>2.81</TD>
388
<TD>&nbsp;</TD>
389
<TD>&nbsp;</TD>
390
<TD COLSPAN='2'>&nbsp;</TD>
391
</TR>
392
</TABLE>
393
 
394
 
395
 
396
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
397
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
398
<TR ALIGN=LEFT>
399
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
400
<TD>0 (Setup: 0, Hold: 0)</TD>
401
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
402
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
403
</TR>
404
<TR ALIGN=LEFT>
405
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
406
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
407
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
408
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
409
</TR>
410
<TR ALIGN=LEFT>
411
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
412
<TD>
413
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
414
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
415
<TD COLSPAN='2'>&nbsp;</TD>
416
</TABLE>
417
 
418
 
419
 
420
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
421
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
422
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
423
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
424
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:21 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Warning'>29 Warnings (29 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Info'>22 Infos (22 new)</A></TD></TR>
425
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:26 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
426
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:49 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/map.xmsgs?&DataKey=Info'>13 Infos (13 new)</A></TD></TR>
427
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:57:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
428
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
429
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:57:08 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
430
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:59:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
431
</TABLE>
432
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
433
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
434
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
435
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:56:49 2011</TD></TR>
436
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:59:16 2011</TD></TR>
437
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:59:24 2011</TD></TR>
438
</TABLE>
439
 
440
 
441
<br><center><b>Date Generated:</b> 08/10/2011 - 22:59:24</center>
442
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