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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_summary.html] - Blame information for rev 22

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1 20 jdoin
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status (08/28/2011 - 23:35:14)</B></TD></TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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<TD>spi_ms_atlys.xise</TD>
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<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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<TD> No Errors </TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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<TD>spi_master_atlys_top</TD>
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<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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<TD>Synthesized</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
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<TD>xc6slx45-2csg324</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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<TD>
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No Errors</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/*.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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<TD>Balanced</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
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<TD>
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&nbsp;</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
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<TD>&nbsp;</TD>
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</TR>
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<TR ALIGN=LEFT>
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<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
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<TD>
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<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_envsettings.html'>
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System Settings</A>
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</TD>
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<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
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<TD>&nbsp;&nbsp;</TD>
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</TR>
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</TABLE>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
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<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
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<TD ALIGN=RIGHT>218</TD>
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<TD ALIGN=RIGHT>54576</TD>
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<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
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<TD ALIGN=RIGHT>166</TD>
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<TD ALIGN=RIGHT>27288</TD>
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<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
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<TD ALIGN=RIGHT>112</TD>
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<TD ALIGN=RIGHT>272</TD>
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<TD ALIGN=RIGHT COLSPAN='2'>41%</TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
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<TD ALIGN=RIGHT>63</TD>
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<TD ALIGN=RIGHT>218</TD>
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<TD ALIGN=RIGHT COLSPAN='2'>28%</TD>
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</TR>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
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<TD ALIGN=RIGHT>2</TD>
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<TD ALIGN=RIGHT>16</TD>
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<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
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</TR>
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</TABLE>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
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<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Aug 28 23:35:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Info'>24 Infos (0 new)</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:23:42 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/map.xmsgs?&DataKey=Info'>13 Infos (0 new)</A></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
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<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:19 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
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<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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</TABLE>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
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<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:30:20 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/synthesis/spi_master_atlys_top_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:42 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/translate/spi_master_atlys_top_translate.nlf'>Post-Translate Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:45 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/map/spi_master_atlys_top_map.nlf'>Post-Map Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:20:15 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:01 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/par/spi_master_atlys_top_timesim.nlf'>Post-Place and Route Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:26 2011</TD></TR>
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<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Aug 10 23:31:06 2011</TD></TR>
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</TABLE>
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<br><center><b>Date Generated:</b> 08/28/2011 - 23:44:54</center>
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