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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
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<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<center><big><big><b>System Settings</b></big></big></center><br>
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<A NAME="Environment Settings"></A>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Environment Variable</b></td>
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<td><b>xst</b></td>
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<td><b>ngdbuild</b></td>
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<td><b>map</b></td>
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<td><b>par</b></td>
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</tr>
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<tr>
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<td>PATHEXT</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
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<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
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</tr>
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<tr>
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<td>Path</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
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</tr>
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<tr>
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<td>XILINX</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
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<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
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</tr>
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<tr>
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<td>XILINX_DSP</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
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<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
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<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
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</tr>
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<tr>
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<td>XILINX_EDK</td>
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<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
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<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
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<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
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<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
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</tr>
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<tr>
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<td>XILINX_PLANAHEAD</td>
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<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
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<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
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<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
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</tr>
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</TABLE>
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<A NAME="Synthesis Property Settings"></A>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Switch Name</b></td>
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<td><b>Property Name</b></td>
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<td><b>Value</b></td>
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<td><b>Default Value</b></td>
69
</tr>
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<tr>
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<td>-ifn</td>
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<td>&nbsp;</td>
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<td>spi_master_atlys_top.prj</td>
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<td>&nbsp;</td>
75
</tr>
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<tr>
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<td>-ifmt</td>
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<td>&nbsp;</td>
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<td>mixed</td>
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<td>Mixed</td>
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</tr>
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<tr>
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<td>-ofn</td>
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<td>&nbsp;</td>
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<td>spi_master_atlys_top</td>
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<td>&nbsp;</td>
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</tr>
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<tr>
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<td>-ofmt</td>
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<td>&nbsp;</td>
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<td>NGC</td>
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<td>NGC</td>
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</tr>
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<tr>
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<td>-p</td>
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<td>&nbsp;</td>
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<td>xc6slx45-2-csg324</td>
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<td>&nbsp;</td>
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</tr>
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<tr>
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<td>-top</td>
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<td>&nbsp;</td>
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<td>spi_master_atlys_top</td>
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<td>&nbsp;</td>
105
</tr>
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<tr>
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<td>-opt_mode</td>
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<td>Optimization Goal</td>
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<td>Speed</td>
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<td>Speed</td>
111
</tr>
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<tr>
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<td>-opt_level</td>
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<td>Optimization Effort</td>
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<td>2</td>
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<td>1</td>
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</tr>
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<tr>
119
<td>-power</td>
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<td>Power Reduction</td>
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<td>NO</td>
122
<td>No</td>
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</tr>
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<tr>
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<td>-iuc</td>
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<td>Use synthesis Constraints File</td>
127
<td>NO</td>
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<td>No</td>
129
</tr>
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<tr>
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<td>-keep_hierarchy</td>
132
<td>Keep Hierarchy</td>
133
<td>No</td>
134
<td>No</td>
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</tr>
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<tr>
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<td>-netlist_hierarchy</td>
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<td>Netlist Hierarchy</td>
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<td>As_Optimized</td>
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<td>As_Optimized</td>
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</tr>
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<tr>
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<td>-rtlview</td>
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<td>Generate RTL Schematic</td>
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<td>Yes</td>
146
<td>No</td>
147
</tr>
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<tr>
149
<td>-glob_opt</td>
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<td>Global Optimization Goal</td>
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<td>AllClockNets</td>
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<td>AllClockNets</td>
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</tr>
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<tr>
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<td>-read_cores</td>
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<td>Read Cores</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-write_timing_constraints</td>
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<td>Write Timing Constraints</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-cross_clock_analysis</td>
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<td>Cross Clock Analysis</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-bus_delimiter</td>
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<td>Bus Delimiter</td>
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<td>&lt;&gt;</td>
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<td>&lt;&gt;</td>
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</tr>
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<tr>
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<td>-slice_utilization_ratio</td>
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<td>Slice Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-bram_utilization_ratio</td>
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<td>BRAM Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-dsp_utilization_ratio</td>
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<td>DSP Utilization Ratio</td>
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<td>100</td>
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<td>100</td>
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</tr>
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<tr>
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<td>-reduce_control_sets</td>
198
<td>&nbsp;</td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-fsm_extract</td>
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<td>&nbsp;</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-fsm_encoding</td>
210
<td>&nbsp;</td>
211
<td>Gray</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-safe_implementation</td>
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<td>&nbsp;</td>
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<td>No</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-fsm_style</td>
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<td>&nbsp;</td>
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<td>LUT</td>
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<td>LUT</td>
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</tr>
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<tr>
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<td>-ram_extract</td>
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<td>&nbsp;</td>
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<td>No</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-rom_extract</td>
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<td>&nbsp;</td>
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<td>No</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-shreg_extract</td>
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<td>&nbsp;</td>
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<td>NO</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-auto_bram_packing</td>
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<td>&nbsp;</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-resource_sharing</td>
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<td>&nbsp;</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-async_to_sync</td>
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<td>&nbsp;</td>
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<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-use_dsp48</td>
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<td>&nbsp;</td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-iobuf</td>
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<td>&nbsp;</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-max_fanout</td>
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<td>&nbsp;</td>
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<td>100000</td>
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<td>100000</td>
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</tr>
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<tr>
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<td>-bufg</td>
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<td>&nbsp;</td>
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<td>16</td>
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<td>16</td>
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</tr>
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<tr>
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<td>-register_duplication</td>
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<td>&nbsp;</td>
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<td>YES</td>
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<td>Yes</td>
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</tr>
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<tr>
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<td>-register_balancing</td>
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<td>&nbsp;</td>
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<td>No</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-optimize_primitives</td>
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<td>&nbsp;</td>
301
<td>NO</td>
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<td>No</td>
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</tr>
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<tr>
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<td>-use_clock_enable</td>
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<td>&nbsp;</td>
307
<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-use_sync_set</td>
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<td>&nbsp;</td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
317
<td>-use_sync_reset</td>
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<td>&nbsp;</td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-iob</td>
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<td>&nbsp;</td>
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<td>Auto</td>
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<td>Auto</td>
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</tr>
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<tr>
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<td>-equivalent_register_removal</td>
330
<td>&nbsp;</td>
331
<td>YES</td>
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<td>Yes</td>
333
</tr>
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<tr>
335
<td>-slice_utilization_ratio_maxmargin</td>
336
<td>&nbsp;</td>
337
<td>5</td>
338
<td>0</td>
339
</tr>
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</TABLE>
341
<A NAME="Translation Property Settings"></A>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
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</tr>
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<tr bgcolor='#ffff99'>
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<td><b>Switch Name</b></td>
348
<td><b>Property Name</b></td>
349
<td><b>Value</b></td>
350
<td><b>Default Value</b></td>
351
</tr>
352
<tr>
353
<td>-intstyle</td>
354
<td>&nbsp;</td>
355
<td>ise</td>
356
<td>None</td>
357
</tr>
358
<tr>
359
<td>-dd</td>
360
<td>&nbsp;</td>
361
<td>_ngo</td>
362
<td>None</td>
363
</tr>
364
<tr>
365
<td>-p</td>
366
<td>&nbsp;</td>
367
<td>xc6slx45-csg324-2</td>
368
<td>None</td>
369
</tr>
370
<tr>
371
<td>-uc</td>
372
<td>&nbsp;</td>
373
<td>spi_master_atlys.ucf</td>
374
<td>None</td>
375
</tr>
376
</TABLE>
377
<A NAME="Map Property Settings"></A>
378
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
379
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
380
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
381
</tr>
382
<tr bgcolor='#ffff99'>
383
<td><b>Switch Name</b></td>
384
<td><b>Property Name</b></td>
385
<td><b>Value</b></td>
386
<td><b>Default Value</b></td>
387
</tr>
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<tr>
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<td>-detail</td>
390
<td>Generate Detailed MAP Report</td>
391
<td>TRUE</td>
392
<td>TRUE</td>
393
</tr>
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<tr>
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<td>-ol</td>
396
<td>Place & Route Effort Level (Overall)</td>
397
<td>high</td>
398
<td>high</td>
399
</tr>
400
<tr>
401
<td>-xe</td>
402
<td>Placer Extra Effort Map</td>
403
<td>NORMAL</td>
404
<td>&nbsp;</td>
405
</tr>
406
<tr>
407
<td>-xt</td>
408
<td>Extra Cost Tables</td>
409
<td>0</td>
410
<td>0</td>
411
</tr>
412
<tr>
413
<td>-global_opt</td>
414
<td>Global Optimization map</td>
415
<td>TRUE</td>
416
<td>FALSE</td>
417
</tr>
418
<tr>
419
<td>-ir</td>
420
<td>Use RLOC Constraints</td>
421
<td>OFF</td>
422
<td>OFF</td>
423
</tr>
424
<tr>
425
<td>-mt</td>
426
<td>Enable Multi-Threading</td>
427
<td>2</td>
428
<td>0</td>
429
</tr>
430
<tr>
431
<td>-t</td>
432
<td>Starting Placer Cost Table (1-100) Map</td>
433
<td>1</td>
434
<td>0</td>
435
</tr>
436
<tr>
437
<td>-r</td>
438
<td>Register Ordering</td>
439
<td>4</td>
440
<td>4</td>
441
</tr>
442
<tr>
443
<td>-equivalent_register_removal</td>
444
<td>Equivalent Register Removal</td>
445
<td>TRUE</td>
446
<td>TRUE</td>
447
</tr>
448
<tr>
449
<td>-intstyle</td>
450
<td>&nbsp;</td>
451
<td>ise</td>
452
<td>None</td>
453
</tr>
454
<tr>
455
<td>-lc</td>
456
<td>LUT Combining</td>
457
<td>area</td>
458
<td>off</td>
459
</tr>
460
<tr>
461
<td>-o</td>
462
<td>&nbsp;</td>
463
<td>spi_master_atlys_top_map.ncd</td>
464
<td>None</td>
465
</tr>
466
<tr>
467
<td>-w</td>
468
<td>&nbsp;</td>
469
<td>true</td>
470
<td>false</td>
471
</tr>
472
<tr>
473
<td>-pr</td>
474
<td>Pack I/O Registers/Latches into IOBs</td>
475
<td>off</td>
476
<td>off</td>
477
</tr>
478
<tr>
479
<td>-p</td>
480
<td>&nbsp;</td>
481
<td>xc6slx45-csg324-2</td>
482
<td>None</td>
483
</tr>
484
</TABLE>
485
<A NAME="Operating System Information"></A>
486
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
487
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
488
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
489
</tr>
490
<tr bgcolor='#ffff99'>
491
<td><b>Operating System Information</b></td>
492
<td><b>xst</b></td>
493
<td><b>ngdbuild</b></td>
494
<td><b>map</b></td>
495
<td><b>par</b></td>
496
</tr>
497
<tr>
498
<td>CPU Architecture/Speed</td>
499
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
500
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
501
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
502 12 jdoin
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
503 5 jdoin
</tr>
504
<tr>
505
<td>Host</td>
506
<td>Develop-W7</td>
507
<td>Develop-W7</td>
508
<td>Develop-W7</td>
509 12 jdoin
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
510 5 jdoin
</tr>
511
<tr>
512
<td>OS Name</td>
513
<td>Microsoft Windows 7 , 32-bit</td>
514
<td>Microsoft Windows 7 , 32-bit</td>
515
<td>Microsoft Windows 7 , 32-bit</td>
516 12 jdoin
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
517 5 jdoin
</tr>
518
<tr>
519
<td>OS Release</td>
520
<td>Service Pack 1  (build 7601)</td>
521
<td>Service Pack 1  (build 7601)</td>
522
<td>Service Pack 1  (build 7601)</td>
523 12 jdoin
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
524 5 jdoin
</tr>
525
</TABLE>
526
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