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----------------------------------------------------------------------------------
2
-- Author:          Jonny Doin, jdoin@opencores.org
3
-- 
4
-- Create Date:     15:36:20 05/15/2011
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-- Module Name:     SPI_SLAVE - RTL
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-- Project Name:    SPI INTERFACE
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-- Target Devices:  Spartan-6
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-- Tool versions:   ISE 13.1
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-- Description: 
10
--
11
--      This block is the SPI slave interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
13
--      The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
14
--      Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
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--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
16
--      clock domains.
17
--
18
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
19
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch 
20
--      signaling ('PREFETCH').
21
--
22
--      PARALLEL WRITE INTERFACE
23
--      The parallel interface has a input port 'di_i' and an output port 'do_o'.
24
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 
25
--      When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i' 
26
--      cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i' 
27
--      in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
28
--      The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
29
--      The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
30
--      race conditions at the register transfer.
31
--      The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
32
--      For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
33
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
34
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
35
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
36
--      if continuous transmission is intended. 
37
--      When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
38
--
39
--      PARALLEL WRITE PIPELINED SEQUENCE
40
--      =================================
41
--                     __    __    __    __    __    __    __ 
42
--      clk_i       __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
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--                           ___________                        
44
--      di_req_o    ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'clk_i'
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--                  ______________ ___________________________...
46
--      di_i        __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
47
--                                             ________                        
48
--      wren_i      __________________________/        \______...     -- 'wren_i' enables latch on rising edge of 'clk_i'
49
--                      
50
--
51
--      PARALLEL READ INTERFACE
52
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete 
53
--      word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
54
--      The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
55
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
56
--      When the interface is idle, data at the 'do_o' port holds the last word received.
57
--
58
--      PARALLEL READ PIPELINED SEQUENCE
59
--      ================================
60
--                      ______        ______        ______        ______
61
--      clk_spi_i   ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- spi base clock
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--                     __    __    __    __    __    __    __    __    __  
63
--      clk_i       __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock
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--                  _________________ _____________________________________...  -- 1) received data is transferred to 'do_buffer_reg'
65
--      do_o        __old_data_______X__________new_data___________________...  --    after last bit received, at next shift clock.
66
--                                                   ____________               
67
--      do_valid_o  ________________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
68
--                                                                              --    on the 3rd 'clk_i' rising edge.
69
--
70
--
71
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
72
--
73
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
74
--                                                                   
75
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave                
76
--                                                                   
77
--      Author(s):      Jonny Doin, jdoin@opencores.org
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--                                                                   
79
--      Copyright (C) 2011 Authors and OPENCORES.ORG
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--      --------------------------------------------
81
--                                                                   
82
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--      removed from the file and that any derivative work contains the original copyright notice and the associated 
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--      disclaimer. 
85
--                                                                   
86
--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
87
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
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--      (at your option) any later version.
89
--                                                                   
90
--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
91
--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
92
--      details.
93
--
94
--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
95
--      it from http://www.opencores.org/lgpl.shtml
96
--                                                                   
97
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
98
--
99
-- 2011/05/15   v0.10.0050  [JD]    created the slave logic, with 2 clock domains, from SPI_MASTER module.
100
-- 2011/05/15   v0.15.0055  [JD]    fixed logic for starting state when CPHA='1'.
101
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
102
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
103
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
104
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
105
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce 
106
--                                  synthesis LUT overhead in Spartan-6 architecture.
107
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
108
-- 2011/06/12   v0.97.0079  [JD]    implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
109
-- 2011/06/17   v0.97.0079  [JD]    implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
110
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
111
--
112
--                                                                   
113
-----------------------------------------------------------------------------------------------------------------------
114
--  TODO
115
--  ====
116
--
117
--
118
-----------------------------------------------------------------------------------------------------------------------
119
library IEEE;
120
use IEEE.STD_LOGIC_1164.ALL;
121
use IEEE.NUMERIC_STD.ALL;
122
use IEEE.STD_LOGIC_UNSIGNED.ALL;
123
 
124
entity spi_slave is
125
    Generic (
126
        N : positive := 32;                                             -- 32bit serial word length is default
127
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
128
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
129
        PREFETCH : positive := 3);                                      -- prefetch lookahead cycles
130
    Port (
131
        clk_i : in std_logic := 'X';                                    -- internal interface clock (clocks di/do registers)
132
        spi_ssel_i : in std_logic := 'X';                               -- spi bus slave select line
133
        spi_sck_i : in std_logic := 'X';                                -- spi bus sck clock (clocks the shift register core)
134
        spi_mosi_i : in std_logic := 'X';                               -- spi bus mosi input
135
        spi_miso_o : out std_logic := 'X';                              -- spi bus spi_miso_o output
136
        di_req_o : out std_logic;                                       -- preload lookahead data request line
137
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel load data in (clocked in on rising edge of clk_i)
138
        wren_i : in std_logic := 'X';                                   -- user data write enable
139
        do_valid_o : out std_logic;                                     -- do_o data valid strobe, valid during one clk_i rising edge.
140
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked out on falling clk_i)
141
        --- debug ports: can be removed for the application circuit ---
142
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
143
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
144
        wren_ack_o : out std_logic;                                     -- debug: wren ack from state machine
145
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
146
        state_dbg_o : out std_logic_vector (5 downto 0);                -- debug: internal state register
147
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
148
    );
149
end spi_slave;
150
 
151
--================================================================================================================
152
-- SYNTHESIS CONSIDERATIONS
153
-- ========================
154
-- There are several output ports that are used to simulate and verify the core operation. 
155
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
156
-- circuitry. 
157
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
158
-- synthesis tool will remove the receive logic from the generated circuitry.
159
--================================================================================================================
160
 
161
architecture RTL of spi_slave is
162
    -- constants to control FlipFlop synthesis
163
    constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA);
164
    constant SAMPLE_LEVEL : std_logic := SAMPLE_EDGE;
165
    constant SHIFT_EDGE : std_logic := (CPOL xor CPHA);
166
    --
167
    -- GLOBAL RESET:
168
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
169
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
170
    --      especially for the Spartan-6 and newer CLB architectures, where a local reset can
171
    --      reduce the usability of the slice registers, due to the need to share the control
172
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
173
    --      By using GSR for the initialization, and reducing RESET local init to the bare
174
    --      essential, the model achieves better LUT/FF packing and CLB usability.
175
    --
176
    -- internal state signals for register and combinational stages
177
    signal state_next : natural range N+1 downto 0 := 0;
178
    signal state_reg : natural range N+1 downto 0 := 0;
179
    -- shifter signals for register and combinational stages
180
    signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
181
    signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
182
    -- input bit sampled buffer
183
    signal rx_bit_reg : std_logic := '0';
184
    -- buffered di_i data signals for register and combinational stages
185
    signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
186
    -- internal wren_i stretcher for fsm combinational stage
187
    signal wren : std_logic := '0';
188
    signal wren_ack_next : std_logic := '0';
189
    signal wren_ack_reg : std_logic := '0';
190
    -- buffered do_o data signals for register and combinational stages
191
    signal do_buffer_next : std_logic_vector (N-1 downto 0)  := (others => '0');
192
    signal do_buffer_reg : std_logic_vector (N-1 downto 0)  := (others => '0');
193
    -- internal signal to flag transfer to do_buffer_reg
194
    signal do_transfer_next : std_logic := '0';
195
    signal do_transfer_reg : std_logic := '0';
196
    -- internal input data request signal 
197
    signal di_req : std_logic := '0';
198
    -- cross-clock do_valid_o logic
199
    signal do_valid_next : std_logic := '0';
200
    signal do_valid_A : std_logic := '0';
201
    signal do_valid_B : std_logic := '0';
202
    signal do_valid_C : std_logic := '0';
203
    signal do_valid_D : std_logic := '0';
204
    signal do_valid_o_reg : std_logic := '0';
205
    -- cross-clock di_req_o logic
206
    signal di_req_o_next : std_logic := '0';
207
    signal di_req_o_A : std_logic := '0';
208
    signal di_req_o_B : std_logic := '0';
209
    signal di_req_o_C : std_logic := '0';
210
    signal di_req_o_D : std_logic := '0';
211
    signal di_req_o_reg : std_logic := '0';
212
begin
213
    --=============================================================================================
214
    --  GENERICS CONSTRAINTS CHECKING
215
    --=============================================================================================
216
    -- minimum word width is 8 bits
217
    assert N >= 8
218
    report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
219
    severity FAILURE;
220
    -- maximum prefetch lookahead check
221
    assert PREFETCH <= N-5
222
    report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
223
    severity FAILURE;
224
 
225
    --=============================================================================================
226
    --  REGISTERED INPUTS
227
    --=============================================================================================
228
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
229
    rx_bit_proc : process (spi_sck_i, spi_mosi_i) is
230
    begin
231
        if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then
232
            rx_bit_reg <= spi_mosi_i;
233
        end if;
234
    end process rx_bit_proc;
235
 
236
    --=============================================================================================
237
    --  RTL CORE REGISTER PROCESSES
238
    --=============================================================================================
239
    -- fsm state and data registers change on spi SHIFT clock
240
    core_reg_proc : process (spi_sck_i, spi_ssel_i) is
241
    begin
242
        -- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
243
        if spi_ssel_i = '1' then                                -- async clr
244
            state_reg <= 0;                                     -- state falls back to idle when slave not selected
245
        elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then   -- on SHIFT edge, update all core registers
246
            state_reg <= state_next;                            -- core fsm changes state with spi SHIFT clock
247
        end if;
248
        -- FFD registers clocked on SHIFT edge
249
        if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then      -- on fsm state change, update all core registers
250
            sh_reg <= sh_next;                                  -- core shift register
251
            do_buffer_reg <= do_buffer_next;                    -- registered data output
252
            do_transfer_reg <= do_transfer_next;                -- cross-clock transfer flag
253
            wren_ack_reg <= wren_ack_next;                      -- wren ack for data load synchronization
254
        end if;
255
    end process core_reg_proc;
256
 
257
    --=============================================================================================
258
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
259
    --=============================================================================================
260
    -- do_valid_o and di_req_o strobe output logic
261
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
262
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
263
    out_transfer_proc : process ( clk_i, do_transfer_reg, di_req,
264
                                  do_valid_A, do_valid_B, do_valid_D,
265
                                  di_req_o_A, di_req_o_B, di_req_o_D) is
266
    begin
267
        if clk_i'event and clk_i = '1' then                     -- clock at parallel port clock
268
            -- do_transfer_reg -> do_valid_o_reg
269
            do_valid_A <= do_transfer_reg;                      -- the input signal must be at least 2 clocks long
270
            do_valid_B <= do_valid_A;                           -- feed it to a ripple chain of FFDs
271
            do_valid_C <= do_valid_B;
272
            do_valid_D <= do_valid_C;
273
            do_valid_o_reg <= do_valid_next;                    -- registered output pulse
274
            --------------------------------
275
            -- di_req -> di_req_o_reg
276
            di_req_o_A <= di_req;                          -- the input signal must be at least 2 clocks long
277
            di_req_o_B <= di_req_o_A;                           -- feed it to a ripple chain of FFDs
278
            di_req_o_C <= di_req_o_B;
279
            di_req_o_D <= di_req_o_C;
280
            di_req_o_reg <= di_req_o_next;                      -- registered output pulse
281
        end if;
282
        -- generate a 2-clocks pulse at the 3rd clock cycle
283
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
284
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
285
    end process out_transfer_proc;
286
    -- parallel load input registers: data register and write enable
287
    in_transfer_proc: process (clk_i, wren_i, wren_ack_reg) is
288
    begin
289
        -- registered data input, input register with clock enable
290
        if clk_i'event and clk_i = '1' then
291
            if wren_i = '1' then
292
                di_reg <= di_i;                                 -- parallel data input buffer register
293
            end if;
294
        end  if;
295
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
296
        if clk_i'event and clk_i = '1' then
297
            if wren_i = '1' then                                -- wren_i is the sync preset for wren
298
                wren <= '1';
299
            elsif wren_ack_reg = '1' then                       -- wren_ack is the sync reset for wren
300
                wren <= '0';
301
            end if;
302
        end  if;
303
    end process in_transfer_proc;
304
 
305
    --=============================================================================================
306
    --  RTL COMBINATIONAL LOGIC PROCESSES
307
    --=============================================================================================
308
    -- state and datapath combinational logic
309
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, do_buffer_reg,
310
                                do_transfer_reg, di_reg, wren, wren_ack_reg) is
311
    begin
312
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
313
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
314
        do_transfer_next <= do_transfer_reg;                            -- output data flag
315
        wren_ack_next <= '0';                                           -- remove data load ack for all but the load stages
316
        di_req <= '0';                                                  -- prefetch data request: deassert when shifting data
317
        spi_miso_o <= sh_reg(N-1);                                      -- output serial data from the MSb
318
        state_next <= state_reg - 1;                                    -- update next state at each sck pulse
319
        case state_reg is
320
            when (N) =>
321
                do_transfer_next <= '0';                                -- reset transfer signal
322
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
323
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
324
            when (N-1) downto (PREFETCH+3) =>
325
                do_transfer_next <= '0';                                -- reset transfer signal
326
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
327
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
328
            when (PREFETCH+2) downto 2 =>
329
                -- raise data prefetch request
330
                di_req <= '1';                                          -- request data in advance to allow for pipeline delays
331
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
332
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
333
            when 1 =>
334
                -- restart from state 'N' if more sck pulses come
335
                di_req <= '1';                                          -- request data in advance to allow for pipeline delays
336
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
337
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
338
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
339
                state_next <= N;                                            -- next state is top bit of new data
340
                if wren = '1' then                                      -- load tx register if valid data present at di_reg
341
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
342
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
343
                else
344
                    sh_next <= (others => '0');                         -- load null data (output '0' if no load)
345
                end if;
346
            when 0 =>
347
                di_req <= not wren_ack_reg;                             -- will request data if shifter empty
348
                do_transfer_next <= '0';                                -- clear signal transfer to do_buffer
349
                spi_miso_o <= di_reg(N-1);                              -- shift out first tx bit from the MSb
350
                if CPHA = '0' then
351
                    -- initial state for CPHA=0, when slave interface is first selected or idle
352
                    state_next <= N-1;                                  -- next state is top bit of new data
353
                    sh_next(0) <= rx_bit_reg;                           -- shift in rx bit into LSb
354
                    sh_next(N-1 downto 1) <= di_reg(N-2 downto 0);      -- shift inner bits
355
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
356
                else
357
                    -- initial state for CPHA=1, when slave interface is first selected or idle
358
                    state_next <= N;                                    -- next state is top bit of new data
359
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
360
                end if;
361
            when others =>
362
                state_next <= 0;                                        -- state 0 is safe state
363
        end case;
364
    end process core_combi_proc;
365
 
366
    --=============================================================================================
367
    --  RTL OUTPUT LOGIC PROCESSES
368
    --=============================================================================================
369
    -- data output processes
370
    do_o_proc :         do_o <= do_buffer_reg;                              -- do_o always available
371
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                       -- copy registered do_valid_o to output
372
    di_req_o_proc:      di_req_o <= di_req_o_reg;                           -- copy registered di_req_o to output
373
 
374
    --=============================================================================================
375
    --  DEBUG LOGIC PROCESSES
376
    --=============================================================================================
377
    -- these signals are useful for verification, and can be deleted or commented-out after debug.
378
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
379
    state_debug_proc:   state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
380
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
381
    wren_o_proc:        wren_o <= wren;
382
    wren_ack_o_proc:    wren_ack_o <= wren_ack_reg;
383
    sh_reg_debug_proc:  sh_reg_dbg_o <= sh_reg;                                     -- export sh_reg to debug
384
end architecture RTL;
385
 

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