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[/] [spi_verilog_master_slave/] [trunk/] [rtl/] [spi_master.v] - Blame information for rev 7

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////////////////////////////////////////////////////////////////////////////////
////                                                                        ////
//// Project Name: SPI (Verilog)                                            ////
////                                                                        ////
//// Module Name: spi_master                                                ////
////                                                                        ////
////                                                                        ////
////  This file is part of the Ethernet IP core project                     ////
////  http://opencores.com/project,spi_verilog_master_slave                 ////
////                                                                        ////
////  Author(s):                                                            ////
////      Santhosh G (santhg@opencores.org)                                 ////
////                                                                        ////
////  Refer to Readme.txt for more information                              ////
////                                                                        ////
////////////////////////////////////////////////////////////////////////////////
////                                                                        ////
//// Copyright (C) 2014, 2015 Authors                                       ////
////                                                                        ////
//// This source file may be used and distributed without                   ////
//// restriction provided that this copyright statement is not              ////
//// removed from the file and that any derivative work contains            ////
//// the original copyright notice and the associated disclaimer.           ////
////                                                                        ////
//// This source file is free software; you can redistribute it             ////
//// and/or modify it under the terms of the GNU Lesser General             ////
//// Public License as published by the Free Software Foundation;           ////
//// either version 2.1 of the License, or (at your option) any             ////
//// later version.                                                         ////
////                                                                        ////
//// This source is distributed in the hope that it will be                 ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied             ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ////
//// PURPOSE.  See the GNU Lesser General Public License for more           ////
//// details.                                                               ////
////                                                                        ////
//// You should have received a copy of the GNU Lesser General              ////
//// Public License along with this source; if not, download it             ////
//// from http://www.opencores.org/lgpl.shtml                               ////
////                                                                        ////
////////////////////////////////////////////////////////////////////////////////
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  SPI MODE 3
                CHANGE DATA @ NEGEDGE
                read data @posedge
 
 RSTB-active low asyn reset, CLK-clock, T_RB=0-rx  1-TX, mlb=0-LSB 1st 1-msb 1st
 START=1- starts data transmission cdiv 0=clk/4 1=/8   2=/16  3=/32
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata);
    input rstb,clk,mlb,start;
    input [7:0] tdat;  //transmit data
    input [1:0] cdiv;  //clock divider
        input din;
        output reg ss;
        output reg sck;
        output reg dout;
    output reg done;
        output reg [7:0] rdata; //received data
 
parameter idle=2'b00;
parameter send=2'b10;
parameter finish=2'b11;
reg [1:0] cur,nxt;
 
        reg [7:0] treg,rreg;
        reg [3:0] nbit;
        reg [4:0] mid,cnt;
        reg shift,clr;
 
//FSM i/o
always @(start or cur or nbit or cdiv or rreg) begin
                 nxt=cur;
                 clr=0;
                 shift=0;//ss=0;
                 case(cur)
                        idle:begin
                                if(start==1)
                               begin
                                                         case (cdiv)
                                                                2'b00: mid=2;
                                                                2'b01: mid=4;
                                                                2'b10: mid=8;
                                                                2'b11: mid=16;
                                                         endcase
                                                shift=1;
                                                done=1'b0;
                                                nxt=send;
                                                end
                        end //idle
                        send:begin
                                ss=0;
                                if(nbit!=8)
                                        begin shift=1; end
                                else begin
                                                rdata=rreg;done=1'b1;
                                                nxt=finish;
                                        end
                                end//send
                        finish:begin
                                        shift=0;
                                        ss=1;
                                        clr=1;
                                        nxt=idle;
                                 end
                        default: nxt=finish;
      endcase
    end//always
 
//state transistion
always@(negedge clk or negedge rstb) begin
 if(rstb==0)
   cur<=finish;
 else
   cur<=nxt;
 end
 
//setup falling edge (shift dout) sample rising edge (read din)
always@(negedge clk or posedge clr) begin
  if(clr==1)
                begin cnt=0; sck=1; end
  else begin
        if(shift==1) begin
                cnt=cnt+1;
          if(cnt==mid) begin
                sck=~sck;
                cnt=0;
                end //mid
        end //shift
 end //rst
end //always
 
//sample @ rising edge (read din)
always@(posedge sck or posedge clr ) begin // or negedge rstb
 if(clr==1)  begin
                        nbit=0;  rreg=8'hFF;  end
    else begin
                  if(mlb==0) //LSB first, din@msb -> right shift
                        begin  rreg={din,rreg[7:1]};  end
                  else  //MSB first, din@lsb -> left shift
                        begin  rreg={rreg[6:0],din};  end
                  nbit=nbit+1;
 end //rst
end //always
 
always@(negedge sck or posedge clr) begin
 if(clr==1) begin
          treg=8'hFF;  dout=1;
  end
 else begin
                if(nbit==0) begin //load data into TREG
                        treg=tdat; dout=mlb?treg[7]:treg[0];
                end //nbit_if
                else begin
                        if(mlb==0) //LSB first, shift right
                                begin treg={1'b1,treg[7:1]}; dout=treg[0]; end
                        else//MSB first shift LEFT
                                begin treg={treg[6:0],1'b1}; dout=treg[7]; end
                end
 end //rst
end //always
 
 
endmodule

Line No.	Rev	Author	Line
1	7	santhg	`////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Project Name: SPI (Verilog) ////`
4			`//// ////`
5			`//// Module Name: spi_master ////`
6			`//// ////`
7			`//// ////`
8			`//// This file is part of the Ethernet IP core project ////`
9			`//// http://opencores.com/project,spi_verilog_master_slave ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// Santhosh G (santhg@opencores.org) ////`
13			`//// ////`
14			`//// Refer to Readme.txt for more information ////`
15			`//// ////`
16			`////////////////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2014, 2015 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`////////////////////////////////////////////////////////////////////////////////`
42			`/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~`
43			`SPI MODE 3`
44			`CHANGE DATA @ NEGEDGE`
45			`read data @posedge`
46
47			`RSTB-active low asyn reset, CLK-clock, T_RB=0-rx 1-TX, mlb=0-LSB 1st 1-msb 1st`
48			`START=1- starts data transmission cdiv 0=clk/4 1=/8 2=/16 3=/32`
49			`~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/`
50			`module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata);`
51			`input rstb,clk,mlb,start;`
52			`input [7:0] tdat; //transmit data`
53			`input [1:0] cdiv; //clock divider`
54			`input din;`
55			`output reg ss;`
56			`output reg sck;`
57			`output reg dout;`
58			`output reg done;`
59			`output reg [7:0] rdata; //received data`
60
61			`parameter idle=2'b00;`
62			`parameter send=2'b10;`
63			`parameter finish=2'b11;`
64			`reg [1:0] cur,nxt;`
65
66			`reg [7:0] treg,rreg;`
67			`reg [3:0] nbit;`
68			`reg [4:0] mid,cnt;`
69			`reg shift,clr;`
70
71			`//FSM i/o`
72			`always @(start or cur or nbit or cdiv or rreg) begin`
73			`nxt=cur;`
74			`clr=0;`
75			`shift=0;//ss=0;`
76			`case(cur)`
77			`idle:begin`
78			`if(start==1)`
79			`begin`
80			`case (cdiv)`
81			`2'b00: mid=2;`
82			`2'b01: mid=4;`
83			`2'b10: mid=8;`
84			`2'b11: mid=16;`
85			`endcase`
86			`shift=1;`
87			`done=1'b0;`
88			`nxt=send;`
89			`end`
90			`end //idle`
91			`send:begin`
92			`ss=0;`
93			`if(nbit!=8)`
94			`begin shift=1; end`
95			`else begin`
96			`rdata=rreg;done=1'b1;`
97			`nxt=finish;`
98			`end`
99			`end//send`
100			`finish:begin`
101			`shift=0;`
102			`ss=1;`
103			`clr=1;`
104			`nxt=idle;`
105			`end`
106			`default: nxt=finish;`
107			`endcase`
108			`end//always`
109
110			`//state transistion`
111			`always@(negedge clk or negedge rstb) begin`
112			`if(rstb==0)`
113			`cur<=finish;`
114			`else`
115			`cur<=nxt;`
116			`end`
117
118			`//setup falling edge (shift dout) sample rising edge (read din)`
119			`always@(negedge clk or posedge clr) begin`
120			`if(clr==1)`
121			`begin cnt=0; sck=1; end`
122			`else begin`
123			`if(shift==1) begin`
124			`cnt=cnt+1;`
125			`if(cnt==mid) begin`
126			`sck=~sck;`
127			`cnt=0;`
128			`end //mid`
129			`end //shift`
130			`end //rst`
131			`end //always`
132
133			`//sample @ rising edge (read din)`
134			`always@(posedge sck or posedge clr ) begin // or negedge rstb`
135			`if(clr==1) begin`
136			`nbit=0; rreg=8'hFF; end`
137			`else begin`
138			`if(mlb==0) //LSB first, din@msb -> right shift`
139			`begin rreg={din,rreg[7:1]}; end`
140			`else //MSB first, din@lsb -> left shift`
141			`begin rreg={rreg[6:0],din}; end`
142			`nbit=nbit+1;`
143			`end //rst`
144			`end //always`
145
146			`always@(negedge sck or posedge clr) begin`
147			`if(clr==1) begin`
148			`treg=8'hFF; dout=1;`
149			`end`
150			`else begin`
151			`if(nbit==0) begin //load data into TREG`
152			`treg=tdat; dout=mlb?treg[7]:treg[0];`
153			`end //nbit_if`
154			`else begin`
155			`if(mlb==0) //LSB first, shift right`
156			`begin treg={1'b1,treg[7:1]}; dout=treg[0]; end`
157			`else//MSB first shift LEFT`
158			`begin treg={treg[6:0],1'b1}; dout=treg[7]; end`
159			`end`
160			`end //rst`
161			`end //always`
162
163
164			`endmodule`

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[/] [spi_verilog_master_slave/] [trunk/] [rtl/] [spi_master.v] - Blame information for rev 7