| 1 |
7 |
santhg |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// Project Name: SPI (Verilog) ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// Module Name: spi_slave ////
|
| 6 |
|
|
//// ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// This file is part of the Ethernet IP core project ////
|
| 9 |
|
|
//// http://opencores.com/project,spi_verilog_master_slave ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// Author(s): ////
|
| 12 |
|
|
//// Santhosh G (santhg@opencores.org) ////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//// Refer to Readme.txt for more information ////
|
| 15 |
|
|
//// ////
|
| 16 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//// Copyright (C) 2014, 2015 Authors ////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// This source file may be used and distributed without ////
|
| 21 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 22 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 23 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 24 |
|
|
//// ////
|
| 25 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 26 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 27 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 28 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 29 |
|
|
//// later version. ////
|
| 30 |
|
|
//// ////
|
| 31 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 32 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 33 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 34 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 35 |
|
|
//// details. ////
|
| 36 |
|
|
//// ////
|
| 37 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 38 |
|
|
//// Public License along with this source; if not, download it ////
|
| 39 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 40 |
|
|
//// ////
|
| 41 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 42 |
|
|
/* SPI MODE 3
|
| 43 |
|
|
CHANGE DATA (sdout) @ NEGEDGE SCK
|
| 44 |
|
|
read data (sdin) @posedge SCK
|
| 45 |
|
|
*/
|
| 46 |
|
|
module spi_slave (rstb,ten,tdata,mlb,ss,sck,sdin, sdout,done,rdata);
|
| 47 |
|
|
input rstb,ss,sck,sdin,ten,mlb;
|
| 48 |
|
|
input [7:0] tdata;
|
| 49 |
|
|
output sdout; //slave out master in
|
| 50 |
|
|
output reg done;
|
| 51 |
|
|
output reg [7:0] rdata;
|
| 52 |
|
|
|
| 53 |
|
|
reg [7:0] treg,rreg;
|
| 54 |
|
|
reg [3:0] nb;
|
| 55 |
|
|
wire sout;
|
| 56 |
|
|
|
| 57 |
|
|
assign sout=mlb?treg[7]:treg[0];
|
| 58 |
|
|
assign sdout=( (!ss)&&ten )?sout:1'bz; //if 1=> send data else TRI-STATE sdout
|
| 59 |
|
|
|
| 60 |
|
|
|
| 61 |
|
|
//read from sdout
|
| 62 |
|
|
always @(posedge sck or negedge rstb)
|
| 63 |
|
|
begin
|
| 64 |
|
|
if (rstb==0)
|
| 65 |
|
|
begin rreg = 8'h00; rdata = 8'h00; done = 0; nb = 0; end //
|
| 66 |
|
|
else if (!ss) begin
|
| 67 |
|
|
if(mlb==0) //LSB first, in@msb -> right shift
|
| 68 |
|
|
begin rreg ={sdin,rreg[7:1]}; end
|
| 69 |
|
|
else //MSB first, in@lsb -> left shift
|
| 70 |
|
|
begin rreg ={rreg[6:0],sdin}; end
|
| 71 |
|
|
//increment bit count
|
| 72 |
|
|
nb=nb+1;
|
| 73 |
|
|
if(nb!=8) done=0;
|
| 74 |
|
|
else begin rdata=rreg; done=1; nb=0; end
|
| 75 |
|
|
end //if(!ss)_END if(nb==8)
|
| 76 |
|
|
end
|
| 77 |
|
|
|
| 78 |
|
|
//send to sdout
|
| 79 |
|
|
always @(negedge sck or negedge rstb)
|
| 80 |
|
|
begin
|
| 81 |
|
|
if (rstb==0)
|
| 82 |
|
|
begin treg = 8'hFF; end
|
| 83 |
|
|
else begin
|
| 84 |
|
|
if(!ss) begin
|
| 85 |
|
|
if(nb==0) treg=tdata;
|
| 86 |
|
|
else begin
|
| 87 |
|
|
if(mlb==0) //LSB first, out=lsb -> right shift
|
| 88 |
|
|
begin treg = {1'b1,treg[7:1]}; end
|
| 89 |
|
|
else //MSB first, out=msb -> left shift
|
| 90 |
|
|
begin treg = {treg[6:0],1'b1}; end
|
| 91 |
|
|
end
|
| 92 |
|
|
end //!ss
|
| 93 |
|
|
end //rstb
|
| 94 |
|
|
end //always
|
| 95 |
|
|
|
| 96 |
|
|
endmodule
|
| 97 |
|
|
|
| 98 |
|
|
/*
|
| 99 |
|
|
if(mlb==0) //LSB first, out=lsb -> right shift
|
| 100 |
|
|
begin treg = {treg[7],treg[7:1]}; end
|
| 101 |
|
|
else //MSB first, out=msb -> left shift
|
| 102 |
|
|
begin treg = {treg[6:0],treg[0]}; end
|
| 103 |
|
|
*/
|
| 104 |
|
|
|
| 105 |
|
|
|
| 106 |
|
|
/*
|
| 107 |
|
|
force -freeze sim:/SPI_slave/sck 0 0, 1 {25 ns} -r 50 -can 410
|
| 108 |
|
|
run 405ns
|
| 109 |
|
|
noforce sim:/SPI_slave/sck
|
| 110 |
|
|
force -freeze sim:/SPI_slave/sck 1 0
|
| 111 |
|
|
*/
|
