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[/] [README.md] - Blame information for rev 11

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Steel is a microprocessor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications. It is designed to be easy to use and targeted for embedded systems projects.
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## Key features
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* Simple and easy to use
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* Implements the RV32I base instruction set + Zicsr extension + M-mode privileged architecture
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* 3 pipeline stages, single-issue
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* Hardware described in Verilog
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* Full documentation
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* Passed all RISC-V Compliance Suite tests for the RV32I and Zicsr instruction sets
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* 1.36 CoreMarks/MHz
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## Getting started
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To start using Steel, follow these steps:
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1. Import all files inside the **rtl** directory into your project
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2. Instantiate the core into a Verilog/SystemVerilog module (an instantiation template is provided below)
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3. Connect Steel to a clock source, a reset signal and memory. There is an interface to fetch instructions and another to read/write data, so we recommend a dual-port memory
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There are also interfaces to request for interrupts and to update the time register. The signals of these interfaces must be hardwired to zero if unused. [Read the docs](https://rafaelcalcada.github.io/steel-core/) for more information about this signals.
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```verilog
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steel_top #(
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    // You must provide a 32-bit value. If omitted the boot address is set to 0x00000000
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    // ---------------------------------------------------------------------------------
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    .BOOT_ADDRESS()
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    ) core (
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    // Clock source and reset
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    // ---------------------------------------------------------------------------------
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    .CLK(),         // System clock (input, required, 1-bit)
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    .RESET(),       // System reset (input, required, 1-bit, synchronous, active high)
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    // Instruction fetch interface
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    // ---------------------------------------------------------------------------------
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    .I_ADDR(),      // Instruction address (output, 32-bit)
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    .INSTR(),       // Instruction data (input, required, 32-bit)
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    // Data read/write interface
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    // ---------------------------------------------------------------------------------
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    .D_ADDR(),      // Data address (output, 32-bit)
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    .DATA_IN(),     // Data read from memory (input, required, 32-bit)
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    .DATA_OUT(),    // Data to write into memory (output, 32-bit)
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    .WR_REQ(),      // Write enable (output, 1-bit)
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    .WR_MASK(),     // Write byte mask (output, 4-bit)
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    // Interrupt request interface (hardwire to zero if unused)
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    // ---------------------------------------------------------------------------------
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    .E_IRQ(),       // External interrupt request (optional, active high, 1-bit)
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    .T_IRQ(),       // Timer interrupt request (optional, active high, 1-bit)
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    .S_IRQ()        // Software interrupt request (optional, active high, 1-bit)
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    // Time register update interface (hardwire to zero if unused)
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    // ---------------------------------------------------------------------------------
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    .REAL_TIME(),   // Value read from a real-time counter (optional, 64-bit)
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);
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```
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## Documentation
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Steel documentation is available at [https://rafaelcalcada.github.io/steel-core/](https://rafaelcalcada.github.io/steel-core/) and provides information on:
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* How to compile software for Steel
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* I/O signals and communication to other devices
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* Configuration
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* Exceptions, interrupts and trap handling
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* Implementation details
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* Timing diagrams
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## License
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Steel is distributed under the MIT License. Read the `LICENSE.md` file before using Steel.
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## About the author
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The author is a computer engineering student at UFRGS (graduates at the end of 2020).
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Contact: rafaelcalcada@gmail.com / rafaelcalcada@hotmail.com
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## Acknowledgements
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My colleague [Francisco Knebel](https://github.com/FranciscoKnebel) deserves special thanks for his collaboration with this work.

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