Steel is a microprocessor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications. It is designed to be easy to use and targeted for embedded systems projects.
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## Key features
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* Simple and easy to use
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* Implements the RV32I base instruction set + Zicsr extension + M-mode privileged architecture
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* 3 pipeline stages, single-issue
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* Hardware described in Verilog
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* Full documentation
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* Passed all RISC-V Compliance Suite tests for the RV32I and Zicsr instruction sets
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* 1.36 CoreMarks/MHz
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## Licensing
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Steel is distributed under the [MIT License](https://en.wikipedia.org/wiki/MIT_License). The license text is reproduced in the `LICENCE.md` file. Read it carefully and make sure you understand its terms before using Steel in your projects.
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## Specifications
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Steel aims to be compliant with the following versions of the RISC-V specifications:
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* Base ISA RV32I version **2.1**
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* Zicsr extension version **2.0**
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* Machine ISA version **1.11**
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## GitHub repo
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Steel files and documentation are available at GitHub ([github.com/rafaelcalcada/steel-core](https://github.com/rafaelcalcada/steel-core)).
