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[/] [rtl/] [bench/] [tb_alu.v] - Blame information for rev 11

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//////////////////////////////////////////////////////////////////////////////////
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
// 
// Create Date: 03.04.2020 18:35:35
// Module Name: tb_alu
// Project Name: Steel Core
// Description: ALU testbench
// 
// Dependencies: globals.vh
//               alu.v
// 
// Version 0.01
// 
//////////////////////////////////////////////////////////////////////////////////
 
/*********************************************************************************
 
MIT License
 
Copyright (c) 2020 Rafael de Oliveira Calçada
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
********************************************************************************/
 
`timescale 1ns / 1ps
`include "../globals.vh"
 
module tb_alu();
 
    reg [31:0] OP_1;
    reg [31:0] OP_2;
    reg [3:0] OPCODE;
    wire [31:0] RESULT;
 
    alu dut(
 
        .OP_1(          OP_1),
        .OP_2(          OP_2),
        .OPCODE(      OPCODE),
        .RESULT(      RESULT)
 
    );
 
    reg [31:0] expected_result;
    integer i;
 
    initial
    begin
 
        $display("Testing ALU...");
 
        $display("Executing extreme values test for ADD and SUB operations...");
 
        OP_1 = 32'h00000001; // decimal = 1
        OP_2 = 32'h7FFFFFFF; // the biggest positive decimal
        OPCODE = `ALU_ADD;
        expected_result = 32'h80000000; // the lowest negative decimal
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'h80000000; // the lowest negative decimal
        OP_2 = 32'h00000001; // decimal = 1
        OPCODE = `ALU_SUB;
        expected_result = 32'h7FFFFFFF; // the biggest positive decimal
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'h00000000; // decimal = 0
        OP_2 = 32'h00000001; // decimal = 1
        OPCODE = `ALU_SUB;
        expected_result = 32'hFFFFFFFF; // decimal = -1
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'hFFFFFFFF; // decimal = -1
        OP_2 = 32'h00000001; // decimal = 1
        OPCODE = `ALU_ADD;
        expected_result = 32'h00000000; // decimal = 0
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'h00000001; // decimal = 1
        OP_2 = 32'hFFFFFFFF; // decimal = -1
        OPCODE = `ALU_ADD;
        expected_result = 32'h00000000; // decimal = 0
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'h00000001; // decimal = 1
        OP_2 = 32'hFFFFFFFF; // decimal = -1
        OPCODE = `ALU_SUB;
        expected_result = 32'h00000002; // decimal = 2
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        OP_1 = 32'hFFFFFFFF; // decimal = -1
        OP_2 = 32'h00000001; // decimal = 1
        OPCODE = `ALU_SUB;
        expected_result = 32'hFFFFFFFE; // decimal = -2
        #10;
        if (RESULT != expected_result)
            begin
                $display("FAIL. Check the results.");
                $finish;
            end
 
        $display("Test successful.");
        $display("Testing 10000 pseudorandom values for all operations...");
 
        $display("Testing ADD operation...");
            OPCODE = `ALU_ADD;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 + OP_2;
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("ADD operation successfully tested.");
 
        $display("Testing SUB operation...");
            OPCODE = `ALU_SUB;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 - OP_2;
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SUB operation successfully tested.");
 
        $display("Testing SLTU operation...");
            OPCODE = `ALU_SLTU;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = {31'b0, OP_1 < OP_2};
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SLTU operation successfully tested.");
 
        $display("Testing SLT operation...");
            OPCODE = `ALU_SLT;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = {31'b0, $signed(OP_1) < $signed(OP_2)};
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SLT operation successfully tested.");
 
        $display("Testing AND operation...");
            OPCODE = `ALU_AND;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 & OP_2;
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("AND operation successfully tested.");
 
        $display("Testing OR operation...");
            OPCODE = `ALU_OR;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 | OP_2;
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("OR operation successfully tested.");
 
        $display("Testing XOR operation...");
            OPCODE = `ALU_XOR;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 ^ OP_2;
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("XOR operation successfully tested.");
 
        $display("Testing SLL operation...");
            OPCODE = `ALU_SLL;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 << OP_2[4:0];
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SLL operation successfully tested.");
 
        $display("Testing SRL operation...");
            OPCODE = `ALU_SRL;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = OP_1 >> OP_2[4:0];
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SRL operation successfully tested.");
 
        $display("Testing SRA operation...");
            OPCODE = `ALU_SRA;
            for(i = 0; i < 10000; i=i+1)
            begin
 
                OP_1 = $random;
                OP_2 = $random;
                #10;
                expected_result = $signed(OP_1) >>> OP_2[4:0];
                if (RESULT != expected_result)
                begin
                    $display("FAIL. Check the results.");
                    $finish;
                end
 
            end
        $display("SRA operation successfully tested.");
 
        $display("All ALU operations successfully tested for pseudorandom values.");
 
        $display("ALU successfully tested.");
 
    end
 
endmodule

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Subversion Repositories steelcore

[/] [rtl/] [bench/] [tb_alu.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	rafaelcalc	`//////////////////////////////////////////////////////////////////////////////////`
2			`// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)`
3			`//`
4			`// Create Date: 03.04.2020 18:35:35`
5			`// Module Name: tb_alu`
6			`// Project Name: Steel Core`
7			`// Description: ALU testbench`
8			`//`
9			`// Dependencies: globals.vh`
10			`// alu.v`
11			`//`
12			`// Version 0.01`
13			`//`
14			`//////////////////////////////////////////////////////////////////////////////////`
15
16			`/*********************************************************************************`
17
18			`MIT License`
19
20			`Copyright (c) 2020 Rafael de Oliveira Calçada`
21
22			`Permission is hereby granted, free of charge, to any person obtaining a copy`
23			`of this software and associated documentation files (the "Software"), to deal`
24			`in the Software without restriction, including without limitation the rights`
25			`to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
26			`copies of the Software, and to permit persons to whom the Software is`
27			`furnished to do so, subject to the following conditions:`
28
29			`The above copyright notice and this permission notice shall be included in all`
30			`copies or substantial portions of the Software.`
31
32			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
33			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
34			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
35			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
36			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
37			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
38			`SOFTWARE.`
39
40			`********************************************************************************/`
41
42			`timescale 1ns / 1ps
43			`include "../globals.vh"
44
45			`module tb_alu();`
46
47			`reg [31:0] OP_1;`
48			`reg [31:0] OP_2;`
49			`reg [3:0] OPCODE;`
50			`wire [31:0] RESULT;`
51
52			`alu dut(`
53
54			`.OP_1( OP_1),`
55			`.OP_2( OP_2),`
56			`.OPCODE( OPCODE),`
57			`.RESULT( RESULT)`
58
59			`);`
60
61			`reg [31:0] expected_result;`
62			`integer i;`
63
64			`initial`
65			`begin`
66
67			`$display("Testing ALU...");`
68
69			`$display("Executing extreme values test for ADD and SUB operations...");`
70
71			`OP_1 = 32'h00000001; // decimal = 1`
72			`OP_2 = 32'h7FFFFFFF; // the biggest positive decimal`
73			OPCODE = `ALU_ADD;
74			`expected_result = 32'h80000000; // the lowest negative decimal`
75			`#10;`
76			`if (RESULT != expected_result)`
77			`begin`
78			`$display("FAIL. Check the results.");`
79			`$finish;`
80			`end`
81
82			`OP_1 = 32'h80000000; // the lowest negative decimal`
83			`OP_2 = 32'h00000001; // decimal = 1`
84			OPCODE = `ALU_SUB;
85			`expected_result = 32'h7FFFFFFF; // the biggest positive decimal`
86			`#10;`
87			`if (RESULT != expected_result)`
88			`begin`
89			`$display("FAIL. Check the results.");`
90			`$finish;`
91			`end`
92
93			`OP_1 = 32'h00000000; // decimal = 0`
94			`OP_2 = 32'h00000001; // decimal = 1`
95			OPCODE = `ALU_SUB;
96			`expected_result = 32'hFFFFFFFF; // decimal = -1`
97			`#10;`
98			`if (RESULT != expected_result)`
99			`begin`
100			`$display("FAIL. Check the results.");`
101			`$finish;`
102			`end`
103
104			`OP_1 = 32'hFFFFFFFF; // decimal = -1`
105			`OP_2 = 32'h00000001; // decimal = 1`
106			OPCODE = `ALU_ADD;
107			`expected_result = 32'h00000000; // decimal = 0`
108			`#10;`
109			`if (RESULT != expected_result)`
110			`begin`
111			`$display("FAIL. Check the results.");`
112			`$finish;`
113			`end`
114
115			`OP_1 = 32'h00000001; // decimal = 1`
116			`OP_2 = 32'hFFFFFFFF; // decimal = -1`
117			OPCODE = `ALU_ADD;
118			`expected_result = 32'h00000000; // decimal = 0`
119			`#10;`
120			`if (RESULT != expected_result)`
121			`begin`
122			`$display("FAIL. Check the results.");`
123			`$finish;`
124			`end`
125
126			`OP_1 = 32'h00000001; // decimal = 1`
127			`OP_2 = 32'hFFFFFFFF; // decimal = -1`
128			OPCODE = `ALU_SUB;
129			`expected_result = 32'h00000002; // decimal = 2`
130			`#10;`
131			`if (RESULT != expected_result)`
132			`begin`
133			`$display("FAIL. Check the results.");`
134			`$finish;`
135			`end`
136
137			`OP_1 = 32'hFFFFFFFF; // decimal = -1`
138			`OP_2 = 32'h00000001; // decimal = 1`
139			OPCODE = `ALU_SUB;
140			`expected_result = 32'hFFFFFFFE; // decimal = -2`
141			`#10;`
142			`if (RESULT != expected_result)`
143			`begin`
144			`$display("FAIL. Check the results.");`
145			`$finish;`
146			`end`
147
148			`$display("Test successful.");`
149			`$display("Testing 10000 pseudorandom values for all operations...");`
150
151			`$display("Testing ADD operation...");`
152			OPCODE = `ALU_ADD;
153			`for(i = 0; i < 10000; i=i+1)`
154			`begin`
155
156			`OP_1 = $random;`
157			`OP_2 = $random;`
158			`#10;`
159			`expected_result = OP_1 + OP_2;`
160			`if (RESULT != expected_result)`
161			`begin`
162			`$display("FAIL. Check the results.");`
163			`$finish;`
164			`end`
165
166			`end`
167			`$display("ADD operation successfully tested.");`
168
169			`$display("Testing SUB operation...");`
170			OPCODE = `ALU_SUB;
171			`for(i = 0; i < 10000; i=i+1)`
172			`begin`
173
174			`OP_1 = $random;`
175			`OP_2 = $random;`
176			`#10;`
177			`expected_result = OP_1 - OP_2;`
178			`if (RESULT != expected_result)`
179			`begin`
180			`$display("FAIL. Check the results.");`
181			`$finish;`
182			`end`
183
184			`end`
185			`$display("SUB operation successfully tested.");`
186
187			`$display("Testing SLTU operation...");`
188			OPCODE = `ALU_SLTU;
189			`for(i = 0; i < 10000; i=i+1)`
190			`begin`
191
192			`OP_1 = $random;`
193			`OP_2 = $random;`
194			`#10;`
195			`expected_result = {31'b0, OP_1 < OP_2};`
196			`if (RESULT != expected_result)`
197			`begin`
198			`$display("FAIL. Check the results.");`
199			`$finish;`
200			`end`
201
202			`end`
203			`$display("SLTU operation successfully tested.");`
204
205			`$display("Testing SLT operation...");`
206			OPCODE = `ALU_SLT;
207			`for(i = 0; i < 10000; i=i+1)`
208			`begin`
209
210			`OP_1 = $random;`
211			`OP_2 = $random;`
212			`#10;`
213			`expected_result = {31'b0, $signed(OP_1) < $signed(OP_2)};`
214			`if (RESULT != expected_result)`
215			`begin`
216			`$display("FAIL. Check the results.");`
217			`$finish;`
218			`end`
219
220			`end`
221			`$display("SLT operation successfully tested.");`
222
223			`$display("Testing AND operation...");`
224			OPCODE = `ALU_AND;
225			`for(i = 0; i < 10000; i=i+1)`
226			`begin`
227
228			`OP_1 = $random;`
229			`OP_2 = $random;`
230			`#10;`
231			`expected_result = OP_1 & OP_2;`
232			`if (RESULT != expected_result)`
233			`begin`
234			`$display("FAIL. Check the results.");`
235			`$finish;`
236			`end`
237
238			`end`
239			`$display("AND operation successfully tested.");`
240
241			`$display("Testing OR operation...");`
242			OPCODE = `ALU_OR;
243			`for(i = 0; i < 10000; i=i+1)`
244			`begin`
245
246			`OP_1 = $random;`
247			`OP_2 = $random;`
248			`#10;`
249			`expected_result = OP_1 \| OP_2;`
250			`if (RESULT != expected_result)`
251			`begin`
252			`$display("FAIL. Check the results.");`
253			`$finish;`
254			`end`
255
256			`end`
257			`$display("OR operation successfully tested.");`
258
259			`$display("Testing XOR operation...");`
260			OPCODE = `ALU_XOR;
261			`for(i = 0; i < 10000; i=i+1)`
262			`begin`
263
264			`OP_1 = $random;`
265			`OP_2 = $random;`
266			`#10;`
267			`expected_result = OP_1 ^ OP_2;`
268			`if (RESULT != expected_result)`
269			`begin`
270			`$display("FAIL. Check the results.");`
271			`$finish;`
272			`end`
273
274			`end`
275			`$display("XOR operation successfully tested.");`
276
277			`$display("Testing SLL operation...");`
278			OPCODE = `ALU_SLL;
279			`for(i = 0; i < 10000; i=i+1)`
280			`begin`
281
282			`OP_1 = $random;`
283			`OP_2 = $random;`
284			`#10;`
285			`expected_result = OP_1 << OP_2[4:0];`
286			`if (RESULT != expected_result)`
287			`begin`
288			`$display("FAIL. Check the results.");`
289			`$finish;`
290			`end`
291
292			`end`
293			`$display("SLL operation successfully tested.");`
294
295			`$display("Testing SRL operation...");`
296			OPCODE = `ALU_SRL;
297			`for(i = 0; i < 10000; i=i+1)`
298			`begin`
299
300			`OP_1 = $random;`
301			`OP_2 = $random;`
302			`#10;`
303			`expected_result = OP_1 >> OP_2[4:0];`
304			`if (RESULT != expected_result)`
305			`begin`
306			`$display("FAIL. Check the results.");`
307			`$finish;`
308			`end`
309
310			`end`
311			`$display("SRL operation successfully tested.");`
312
313			`$display("Testing SRA operation...");`
314			OPCODE = `ALU_SRA;
315			`for(i = 0; i < 10000; i=i+1)`
316			`begin`
317
318			`OP_1 = $random;`
319			`OP_2 = $random;`
320			`#10;`
321			`expected_result = $signed(OP_1) >>> OP_2[4:0];`
322			`if (RESULT != expected_result)`
323			`begin`
324			`$display("FAIL. Check the results.");`
325			`$finish;`
326			`end`
327
328			`end`
329			`$display("SRA operation successfully tested.");`
330
331			`$display("All ALU operations successfully tested for pseudorandom values.");`
332
333			`$display("ALU successfully tested.");`
334
335			`end`
336
337			`endmodule`