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[/] [rtl/] [bench/] [tb_store_unit.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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// 
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// Create Date: 02.06.2020 16:03:55
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// Module Name: tb_store_unit
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// Project Name: Steel Core
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// Description: Store Unit testbench
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// 
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// Dependencies: globals.vh
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//               store_unit.v
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "../globals.vh"
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module tb_store_unit();
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    reg [2:0] FUNCT3;
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    reg [31:0] IADDER_OUT;
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    reg [31:0] RS2;
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    reg MEM_WR_REQ;
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    wire [31:0] DATA_OUT;
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    wire [31:0] D_ADDR;
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    wire [3:0] WR_MASK;
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    wire WR_REQ;
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    store_unit dut(
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        .FUNCT3(FUNCT3[1:0]),
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        .IADDER_OUT(IADDER_OUT),
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        .RS2(RS2),
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        .MEM_WR_REQ(MEM_WR_REQ),
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        .DATA_OUT(DATA_OUT),
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        .D_ADDR(D_ADDR),
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        .WR_MASK(WR_MASK),
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        .WR_REQ(WR_REQ)
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    );
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    integer i;
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    initial
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    begin
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        FUNCT3 = `FUNCT3_BYTE;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b0;
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        $display("Testing D_ADDR generation...");
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        for(i = 0; i < 20; i=i+1)
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        begin
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            IADDER_OUT = $random;
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            #10;
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            if(D_ADDR != {IADDER_OUT[31:2], 2'b00})
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            begin
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                $display("FAIL. Check the results.");
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                $finish;
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            end
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        end
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        $display("D_ADDR generation OK.");
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        $display("Testing SB signals generation...");
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        FUNCT3 = `FUNCT3_BYTE;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b00;
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        #10;
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        if(DATA_OUT != {24'b0, RS2[7:0]})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b0001)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        FUNCT3 = `FUNCT3_BYTE;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b01;
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        #10;
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        if(DATA_OUT != {16'b0, RS2[7:0], 8'b0})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b0010)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        FUNCT3 = `FUNCT3_BYTE;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b10;
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        #10;
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        if(DATA_OUT != {8'b0, RS2[7:0], 16'b0})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b0100)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        FUNCT3 = `FUNCT3_BYTE;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b11;
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        #10;
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        if(DATA_OUT != {RS2[7:0], 24'b0})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b1000)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        $display("SB signals generation successfully tested.");
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        $display("Testing SH signals generation...");
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        FUNCT3 = `FUNCT3_HALF;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b00;
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        #10;
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        if(DATA_OUT != {16'b0, RS2[15:0]})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b0011)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        FUNCT3 = `FUNCT3_HALF;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b10;
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        #10;
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        if(DATA_OUT != {RS2[15:0], 16'b0})
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b1100)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        $display("SH signals generation successfully tested.");
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        $display("Testing SW signals generation...");
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        FUNCT3 = `FUNCT3_WORD;
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        RS2 = $random;
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        MEM_WR_REQ = 1'b1;
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        IADDER_OUT[1:0] = 2'b00;
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        #10;
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        if(DATA_OUT != RS2)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_REQ != 1'b1)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        if(WR_MASK != 4'b1111)
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        begin
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            $display("FAIL. Check the results.");
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            $finish;
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        end
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        $display("SW signals generation successfully tested.");
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        $display("Store Unit successfully tested.");
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    end
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endmodule

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