OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [rtl/] [branch_unit.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
3
// 
4
// Create Date: 26.04.2020 18:29:52
5
// Module Name: branch_unit
6
// Project Name: Steel Core 
7
// Description: Branch decision unit
8
// 
9
// Dependencies: globals.vh
10
// 
11
// Version 0.01
12
// 
13
//////////////////////////////////////////////////////////////////////////////////
14
 
15
/*********************************************************************************
16
 
17
MIT License
18
 
19
Copyright (c) 2020 Rafael de Oliveira Calçada
20
 
21
Permission is hereby granted, free of charge, to any person obtaining a copy
22
of this software and associated documentation files (the "Software"), to deal
23
in the Software without restriction, including without limitation the rights
24
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
25
copies of the Software, and to permit persons to whom the Software is
26
furnished to do so, subject to the following conditions:
27
 
28
The above copyright notice and this permission notice shall be included in all
29
copies or substantial portions of the Software.
30
 
31
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
34
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
35
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
36
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37
SOFTWARE.
38
 
39
********************************************************************************/
40
 
41
`timescale 1ns / 1ps
42
`include "globals.vh"
43
 
44
module branch_unit(
45
 
46
    input wire [6:2] OPCODE_6_TO_2,
47
    input wire [2:0] FUNCT3,
48
    input wire [31:0] RS1,
49
    input wire [31:0] RS2,
50
    output wire BRANCH_TAKEN
51
 
52
    );
53
 
54
    wire pc_mux_sel;
55
    wire pc_mux_sel_en;
56
    wire is_branch;
57
    wire is_jal;
58
    wire is_jalr;
59
    wire is_jump;
60
    wire eq;
61
    wire ne;
62
    wire lt;
63
    wire ge;
64
    wire ltu;
65
    wire geu;
66
    reg take;
67
 
68
    assign is_jal = OPCODE_6_TO_2[6] & OPCODE_6_TO_2[5] & ~OPCODE_6_TO_2[4] & OPCODE_6_TO_2[3] & OPCODE_6_TO_2[2];
69
    assign is_jalr = OPCODE_6_TO_2[6] & OPCODE_6_TO_2[5] & ~OPCODE_6_TO_2[4] & ~OPCODE_6_TO_2[3] & OPCODE_6_TO_2[2];
70
    assign is_jump = is_jal | is_jalr;
71
    assign eq = (RS1 == RS2);
72
    assign ne = !eq;
73
    assign lt = RS1[31] ^ RS2[31] ? RS1[31] : ltu;
74
    assign ge = !lt;
75
    assign ltu = (RS1 < RS2);
76
    assign geu = !ltu;
77
    assign is_branch = OPCODE_6_TO_2[6] & OPCODE_6_TO_2[5] & ~OPCODE_6_TO_2[4] & ~OPCODE_6_TO_2[3] & ~OPCODE_6_TO_2[2];
78
    assign pc_mux_sel_en = is_branch | is_jal | is_jalr;
79
    assign pc_mux_sel = (is_jump == 1'b1) ? 1'b1 : take;
80
    assign BRANCH_TAKEN = pc_mux_sel_en & pc_mux_sel;
81
 
82
    always @(*)
83
    begin
84
        case (FUNCT3)
85
            3'b000: take = eq;
86
            3'b001: take = ne;
87
            3'b100: take = lt;
88
            3'b101: take = ge;
89
            3'b110: take = ltu;
90
            3'b111: take = geu;
91
            default: take = 1'b0;
92
        endcase
93
    end
94
 
95
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.