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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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// 
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// Create Date: 26.04.2020 23:33:34
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// Module Name: csr_file
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// Project Name: Steel Core 
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// Description: Control and Status Register File 
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// 
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// Dependencies: globals.vh
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "globals.vh"
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module csr_file(
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    input wire CLK,
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    input wire RESET,
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    input wire WR_EN,
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    input wire [11:0] CSR_ADDR,
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    input wire [2:0] CSR_OP,
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    input wire [4:0] CSR_UIMM,
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    input wire [31:0] CSR_DATA_IN,
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    output reg [31:0] CSR_DATA_OUT,
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    // from pipeline stage 1
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    input wire [31:0] PC,
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    // from pipeline stage 3
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    input wire [31:0] IADDER_OUT,
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    // interface with CLIC
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    input wire E_IRQ,
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    input wire T_IRQ,
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    input wire S_IRQ,
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    // interface with Machine Control Module
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    input wire I_OR_E,
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    input wire SET_CAUSE,
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    input wire [3:0] CAUSE_IN,
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    input wire SET_EPC,
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    input wire INSTRET_INC,
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    input wire MIE_CLEAR,
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    input wire MIE_SET,
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    input wire MISALIGNED_EXCEPTION,
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    output reg MIE,
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    output wire MEIE_OUT,
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    output wire MTIE_OUT,
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    output wire MSIE_OUT,
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    output wire MEIP_OUT,
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    output wire MTIP_OUT,
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    output wire MSIP_OUT,
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    // platform real time CLK value
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    input wire [63:0] REAL_TIME,
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    // these two outputs are connected to the PC MUX
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    output wire [31:0] EPC_OUT,
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    output wire [31:0] TRAP_ADDRESS
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    );
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    // Machine trap setup
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    wire [31:0] mstatus; // machine status register
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    wire [31:0] misa; // machine ISA register
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    wire [31:0] mie_reg; // machine interrupt enable register
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    wire [31:0] mtvec;
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    wire [1:0] mxl; // machine XLEN
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    wire [25:0] mextensions; // ISA extensions
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    reg [1:0] mtvec_mode; // machine trap mode
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    reg [29:0] mtvec_base; // machine trap base address
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    reg mpie; // mach. prior interrupt enable
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    reg meie; // mach. external interrupt enable
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    reg mtie; // mach. timer interrupt enable
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    reg msie; // mach. software interrupt enable
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    // Machine trap handling
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    reg [31:0] mscratch; // machine scratch register
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    reg [31:0] mepc; // machine exception program counter
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    reg [31:0] mtval; // machine trap value register
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    wire [31:0] mcause; // machine trap cause register
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    wire [31:0] mip_reg; // machine interrupt pending register
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    reg int_or_exc; // interrupt or exception signal
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    reg [3:0] cause; // interrupt cause
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    reg [26:0] cause_rem; // remaining bits of mcause register 
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    reg meip; // mach. external interrupt pending
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    reg mtip; // mach. timer interrupt pending
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    reg msip; // mach. software interrupt pending
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    // Machine counters
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    reg [63:0] mcycle;
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    reg [63:0] mtime;
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    reg [63:0] minstret;
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    // Machine counters setup
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    wire [31:0] mcountinhibit;
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    reg mcountinhibit_cy;
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    reg mcountinhibit_ir;
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130
    // CSR operation control
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    // ----------------------------------------------------------------------------
132
 
133
    reg [31:0] data_wr;
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    wire [31:0] pre_data;
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    assign pre_data = CSR_OP[2] == 1'b1 ? {27'b0, CSR_UIMM} : CSR_DATA_IN;
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138
    always @*
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    begin
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        case(CSR_OP[1:0])
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            `CSR_RW: data_wr <= pre_data;
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            `CSR_RS: data_wr <= CSR_DATA_OUT | pre_data;
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            `CSR_RC: data_wr <= CSR_DATA_OUT & ~pre_data;
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            `CSR_NOP: data_wr <= CSR_DATA_OUT;
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        endcase
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    end
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148
    always @*
149
    begin
150
        case(CSR_ADDR)
151
            `CYCLE:         CSR_DATA_OUT = mcycle[31:0];
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            `CYCLEH:        CSR_DATA_OUT = mcycle[63:32];
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            `TIME:          CSR_DATA_OUT = mtime[31:0];
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            `TIMEH:         CSR_DATA_OUT = mtime[63:32];
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            `INSTRET:       CSR_DATA_OUT = minstret[31:0];
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            `INSTRETH:      CSR_DATA_OUT = minstret[63:32];
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            `MSTATUS:       CSR_DATA_OUT = mstatus;
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            `MISA:          CSR_DATA_OUT = misa;
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            `MIE:           CSR_DATA_OUT = mie_reg;
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            `MTVEC:         CSR_DATA_OUT = mtvec;
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            `MSCRATCH:      CSR_DATA_OUT = mscratch;
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            `MEPC:          CSR_DATA_OUT = mepc;
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            `MCAUSE:        CSR_DATA_OUT = mcause;
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            `MTVAL:         CSR_DATA_OUT = mtval;
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            `MIP:           CSR_DATA_OUT = mip_reg;
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            `MCYCLE:        CSR_DATA_OUT = mcycle[31:0];
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            `MCYCLEH:       CSR_DATA_OUT = mcycle[63:32];
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            `MINSTRET:      CSR_DATA_OUT = minstret[31:0];
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            `MINSTRETH:     CSR_DATA_OUT = minstret[63:32];
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            `MCOUNTINHIBIT: CSR_DATA_OUT = mcountinhibit;
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            default:        CSR_DATA_OUT = 32'b0;
172
        endcase
173
    end
174
 
175
    // MSTATUS register
176
    //                       MPP           
177
    assign mstatus = {19'b0, 2'b11, 3'b0, mpie, 3'b0 , MIE, 3'b0};
178
    always @(posedge CLK)
179
    begin
180
        if(RESET)
181
        begin
182
            MIE <= 1'b0;
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            mpie <= 1'b1;
184
        end
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        else if(CSR_ADDR == `MSTATUS && WR_EN)
186
        begin
187
            MIE <= data_wr[3];
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            mpie <= data_wr[7];
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        end
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        else if(MIE_CLEAR == 1'b1)
191
        begin
192
            mpie <= MIE;
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            MIE <= 1'b0;
194
        end
195
        else if(MIE_SET == 1'b1)
196
        begin
197
            MIE <= mpie;
198
            mpie <= 1'b1;
199
        end
200
    end
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202
    // MISA register
203
    assign mxl = 2'b01;
204
    assign mextensions = 26'b00000000000000000100000000;
205
    assign misa = {mxl, 4'b0, mextensions};
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207
    // MIE register
208
    assign mie_reg = {20'b0, meie, 3'b0, mtie, 3'b0, msie, 3'b0};
209
    assign MEIE_OUT = meie;
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    assign MTIE_OUT = mtie;
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    assign MSIE_OUT = msie;
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    always @(posedge CLK)
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    begin
214
        if(RESET)
215
        begin
216
            meie <= 1'b0;
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            mtie <= 1'b0;
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            msie <= 1'b0;
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        end
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        else if(CSR_ADDR == `MIE && WR_EN)
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        begin
222
            meie <= data_wr[11];
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            mtie <= data_wr[7];
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            msie <= data_wr[3];
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        end
226
    end
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    // MTVEC register
229
    assign mtvec = {mtvec_base, mtvec_mode};
230
    wire [31:0] trap_mux_out;
231
    wire [31:0] vec_mux_out;
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    wire [31:0] base_offset;
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    assign base_offset = cause << 2;
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    assign trap_mux_out = int_or_exc ? vec_mux_out : {mtvec_base, 2'b00};
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    assign vec_mux_out = mtvec[0] ? {mtvec_base, 2'b00} + base_offset : {mtvec_base, 2'b00};
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    assign TRAP_ADDRESS = trap_mux_out;
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    always @(posedge CLK)
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    begin
239
        if(RESET)
240
        begin
241
            mtvec_mode <= `MTVEC_MODE_RESET;
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            mtvec_base <= `MTVEC_BASE_RESET;
243
        end
244
        else if(CSR_ADDR == `MTVEC && WR_EN)
245
        begin
246
            mtvec_mode <= data_wr[1:0];
247
            mtvec_base <= data_wr[31:2];
248
        end
249
    end
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251
    // MSCRATCH register
252
    always @(posedge CLK)
253
    begin
254
        if(RESET) mscratch <= `MSCRATCH_RESET;
255
        else if(CSR_ADDR == `MSCRATCH && WR_EN) mscratch <= data_wr;
256
    end
257
 
258
    // MEPC register
259
    assign EPC_OUT = mepc;
260
    always @(posedge CLK)
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    begin
262
        if(RESET) mepc <= `MEPC_RESET;
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        else if(SET_EPC) mepc <= PC;
264
        else if(CSR_ADDR == `MEPC && WR_EN) mepc <= {data_wr[31:2], 2'b00};
265
    end
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267
    // MCAUSE register
268
    assign mcause = {int_or_exc, cause_rem, cause};
269
    always @(posedge CLK)
270
    begin
271
        if(RESET)
272
        begin
273
            cause <= 4'b0000;
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            cause_rem <= 27'b0;
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            int_or_exc <= 1'b0;
276
        end
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        else if(SET_CAUSE)
278
        begin
279
            cause <= CAUSE_IN;
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            cause_rem <= 27'b0;
281
            int_or_exc <= I_OR_E;
282
        end
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        else if(CSR_ADDR == `MCAUSE && WR_EN)
284
        begin
285
            cause <= data_wr[3:0];
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            cause_rem <= data_wr[30:4];
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            int_or_exc <= data_wr[31];
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289
        end
290
    end
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292
    // MIP register
293
    assign mip_reg = {20'b0, meip, 3'b0, mtip, 3'b0, msip, 3'b0};
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    assign MEIP_OUT = meip;
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    assign MTIP_OUT = mtip;
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    assign MSIP_OUT = msip;
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    always @(posedge CLK)
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    begin
299
        if(RESET)
300
        begin
301
            meip <= 1'b0;
302
            mtip <= 1'b0;
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            msip <= 1'b0;
304
        end
305
        else
306
        begin
307
            meip <= E_IRQ;
308
            mtip <= T_IRQ;
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            msip <= S_IRQ;
310
        end
311
    end
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313
    // MTVAL register
314
    always @(posedge CLK)
315
    begin
316
        if(RESET) mtval <= 32'b0;
317
        else if(SET_CAUSE)
318
        begin
319
            if(MISALIGNED_EXCEPTION) mtval <= IADDER_OUT;
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            else mtval <= 32'b0;
321
        end
322
        else if(CSR_ADDR == `MTVAL && WR_EN) mtval <= data_wr;
323
    end
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325
    // MCOUNTINHIBIT register
326
    assign mcountinhibit = {29'b0, mcountinhibit_ir, 1'b0, mcountinhibit_cy};
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    always @(posedge CLK)
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    begin
329
        if(RESET)
330
        begin
331
            mcountinhibit_cy <= `MCOUNTINHIBIT_CY_RESET;
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            mcountinhibit_ir <= `MCOUNTINHIBIT_IR_RESET;
333
        end
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        else if(CSR_ADDR == `MCOUNTINHIBIT && WR_EN)
335
        begin
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            mcountinhibit_cy <= data_wr[2];
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            mcountinhibit_ir <= data_wr[0];
338
        end
339
    end
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    // Counters
342
    always @(posedge CLK)
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    begin
344
        if(RESET)
345
        begin
346
            mcycle <= {`MCYCLEH_RESET, `MCYCLE_RESET};
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            minstret <= {`MINSTRETH_RESET, `MINSTRET_RESET};
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            mtime <= {`TIMEH_RESET, `TIME_RESET};
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        end
350
        else
351
        begin
352
            mtime <= REAL_TIME;
353
 
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            if(CSR_ADDR == `MCYCLE && WR_EN)
355
            begin
356
                if(mcountinhibit_cy == 1'b0) mcycle <= {mcycle[63:32], data_wr} + 1;
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                else mcycle <= {mcycle[63:32], data_wr};
358
            end
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            else if(CSR_ADDR == `MCYCLEH && WR_EN)
360
            begin
361
                if(mcountinhibit_cy == 1'b0) mcycle <= {data_wr, mcycle[31:0]} + 1;
362
                else mcycle <= {data_wr, mcycle[31:0]};
363
            end
364
            else
365
            begin
366
                if(mcountinhibit_cy == 1'b0) mcycle <= mcycle + 1;
367
                else mcycle <= mcycle;
368
            end
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370
            if(CSR_ADDR == `MINSTRET && WR_EN)
371
            begin
372
                if(mcountinhibit_ir == 1'b0) minstret <= {minstret[63:32], data_wr} + INSTRET_INC;
373
                else minstret <= {minstret[63:32], data_wr};
374
            end
375
            else if(CSR_ADDR == `MINSTRETH && WR_EN)
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            begin
377
                if(mcountinhibit_ir == 1'b0) minstret <= {data_wr, minstret[31:0]} + INSTRET_INC;
378
                else minstret <= {data_wr, minstret[31:0]};
379
            end
380
            else
381
            begin
382
                if(mcountinhibit_ir == 1'b0) minstret <= minstret + INSTRET_INC;
383
                else minstret <= minstret;
384
            end
385
 
386
        end
387
    end
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endmodule

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