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[/] [rtl/] [decoder.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
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// 
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// Create Date: 25.04.2020 14:49:16
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// Module Name: decoder
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// Project Name: Steel Core 
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// Description: Decodes the instruction and generates control signals 
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// 
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// Dependencies: globals.vh
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "globals.vh"
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module decoder(
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    input wire [6:0] OPCODE,
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    input wire FUNCT7_5,
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    input wire [2:0] FUNCT3,
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    input wire [1:0] IADDER_OUT_1_TO_0,
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    input wire TRAP_TAKEN,
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    output wire [3:0] ALU_OPCODE,
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    output wire MEM_WR_REQ,
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    output wire [1:0] LOAD_SIZE,
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    output wire LOAD_UNSIGNED,
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    output wire ALU_SRC,
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    output wire IADDER_SRC,
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    output wire CSR_WR_EN,
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    output wire RF_WR_EN,
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    output wire [2:0] WB_MUX_SEL,
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    output wire [2:0] IMM_TYPE,
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    output wire [2:0] CSR_OP,
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    output wire ILLEGAL_INSTR,
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    output wire MISALIGNED_LOAD,
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    output wire MISALIGNED_STORE
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    );
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    wire is_branch;
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    wire is_jal;
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    wire is_jalr;
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    wire is_auipc;
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    wire is_lui;
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    wire is_load;
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    wire is_store;
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    wire is_system;
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    wire is_csr;
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    wire is_op;
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    wire is_op_imm;
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    wire is_misc_mem;
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    wire is_addi;
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    wire is_slti;
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    wire is_sltiu;
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    wire is_andi;
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    wire is_ori;
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    wire is_xori;
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    wire is_addiw;
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    wire is_implemented_instr;
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    wire mal_word;
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    wire mal_half;
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    wire misaligned;
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    assign LOAD_SIZE[0] = FUNCT3[0];
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    assign LOAD_SIZE[1] = FUNCT3[1];
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    assign LOAD_UNSIGNED = FUNCT3[2];
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    assign ALU_SRC = OPCODE[5];
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    assign is_branch = OPCODE[6] & OPCODE[5] & ~OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_jal = OPCODE[6] & OPCODE[5] & ~OPCODE[4] & OPCODE[3] & OPCODE[2];
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    assign is_jalr = OPCODE[6] & OPCODE[5] & ~OPCODE[4] & ~OPCODE[3] & OPCODE[2];
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    assign is_auipc = ~OPCODE[6] & ~OPCODE[5] & OPCODE[4] & ~OPCODE[3] & OPCODE[2];
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    assign is_lui = ~OPCODE[6] & OPCODE[5] & OPCODE[4] & ~OPCODE[3] & OPCODE[2];
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    assign is_op = ~OPCODE[6] & OPCODE[5] & OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_op_imm = ~OPCODE[6] & ~OPCODE[5] & OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_addi = is_op_imm & ~FUNCT3[2] & ~FUNCT3[1] & ~FUNCT3[0];
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    assign is_slti = is_op_imm & ~FUNCT3[2] & FUNCT3[1] & ~FUNCT3[0];
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    assign is_sltiu = is_op_imm & ~FUNCT3[2] & FUNCT3[1] & FUNCT3[0];
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    assign is_andi = is_op_imm & FUNCT3[2] & FUNCT3[1] & FUNCT3[0];
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    assign is_ori = is_op_imm & FUNCT3[2] & FUNCT3[1] & ~FUNCT3[0];
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    assign is_xori = is_op_imm & FUNCT3[2] & ~FUNCT3[1] & ~FUNCT3[0];
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    assign is_load = ~OPCODE[6] & ~OPCODE[5] & ~OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_store = ~OPCODE[6] & OPCODE[5] & ~OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_system = OPCODE[6] & OPCODE[5] & OPCODE[4] & ~OPCODE[3] & ~OPCODE[2];
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    assign is_misc_mem = ~OPCODE[6] & ~OPCODE[5] & ~OPCODE[4] & OPCODE[3] & OPCODE[2];
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    assign is_csr = is_system & (FUNCT3[2] | FUNCT3[1] | FUNCT3[0]);
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    assign IADDER_SRC = is_load | is_store | is_jalr;
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    assign RF_WR_EN = is_lui | is_auipc | is_jalr | is_jal | is_op | is_load | is_csr | is_op_imm;
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    assign CSR_WR_EN = is_csr;
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    assign ALU_OPCODE[2:0] = FUNCT3;
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    assign ALU_OPCODE[3] = FUNCT7_5 & ~(is_addi | is_slti | is_sltiu | is_andi | is_ori | is_xori);
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    assign WB_MUX_SEL[0] = is_load | is_auipc | is_jal | is_jalr;
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    assign WB_MUX_SEL[1] = is_lui | is_auipc;
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    assign WB_MUX_SEL[2] = is_csr | is_jal | is_jalr;
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    assign IMM_TYPE[0] = is_op_imm | is_load | is_jalr | is_branch | is_jal;
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    assign IMM_TYPE[1] = is_store | is_branch | is_csr;
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    assign IMM_TYPE[2] = is_lui | is_auipc | is_jal | is_csr;
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    assign CSR_OP = FUNCT3;
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    assign is_implemented_instr = is_op | is_op_imm | is_branch | is_jal | is_jalr | is_auipc | is_lui | is_system | is_misc_mem | is_load | is_store;
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    assign ILLEGAL_INSTR = ~OPCODE[1] | ~OPCODE[0] | ~is_implemented_instr;
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    assign mal_word = FUNCT3[1] & ~FUNCT3[0] & (IADDER_OUT_1_TO_0[1] | IADDER_OUT_1_TO_0[0]);
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    assign mal_half = ~FUNCT3[1] & FUNCT3[0] & IADDER_OUT_1_TO_0[0];
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    assign misaligned = mal_word | mal_half;
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    assign MISALIGNED_STORE = is_store & misaligned;
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    assign MISALIGNED_LOAD = is_load & misaligned;
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    assign MEM_WR_REQ = is_store & ~misaligned & ~TRAP_TAKEN;
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endmodule

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