OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [rtl/] [imm_generator.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
3
// 
4
// Create Date: 26.04.2020 22:01:22
5
// Module Name: imm_generator
6
// Project Name: Steel Core 
7
// Description: Generates the immediate according with the instruction 
8
// 
9
// Dependencies: globals.vh
10
// 
11
// Version 0.01
12
// 
13
//////////////////////////////////////////////////////////////////////////////////
14
 
15
/*********************************************************************************
16
 
17
MIT License
18
 
19
Copyright (c) 2020 Rafael de Oliveira Calçada
20
 
21
Permission is hereby granted, free of charge, to any person obtaining a copy
22
of this software and associated documentation files (the "Software"), to deal
23
in the Software without restriction, including without limitation the rights
24
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
25
copies of the Software, and to permit persons to whom the Software is
26
furnished to do so, subject to the following conditions:
27
 
28
The above copyright notice and this permission notice shall be included in all
29
copies or substantial portions of the Software.
30
 
31
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
34
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
35
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
36
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37
SOFTWARE.
38
 
39
********************************************************************************/
40
 
41
`timescale 1ns / 1ps
42
`include "globals.vh"
43
 
44
module imm_generator(
45
 
46
    input wire [31:7] INSTR,
47
    input wire [2:0] IMM_TYPE,
48
    output reg [31:0] IMM
49
 
50
    );
51
 
52
    wire [31:0] i_type;
53
    wire [31:0] s_type;
54
    wire [31:0] b_type;
55
    wire [31:0] u_type;
56
    wire [31:0] j_type;
57
    wire [31:0] csr_type;
58
 
59
    assign i_type = { {20{INSTR[31]}}, INSTR[31:20] };
60
    assign s_type = { {20{INSTR[31]}}, INSTR[31:25], INSTR[11:7] };
61
    assign b_type = { {19{INSTR[31]}}, INSTR[31], INSTR[7], INSTR[30:25], INSTR[11:8], 1'b0 };
62
    assign u_type = { INSTR[31:12], 12'h000 };
63
    assign j_type = { {11{INSTR[31]}}, INSTR[31], INSTR[19:12], INSTR[20], INSTR[30:21], 1'b0 };
64
    assign csr_type = { 27'b0, INSTR[19:15] };
65
 
66
    always @(*)
67
    begin
68
       case (IMM_TYPE)
69
           3'b000: IMM = i_type;
70
           `I_TYPE: IMM = i_type;
71
           `S_TYPE: IMM = s_type;
72
           `B_TYPE: IMM = b_type;
73
           `U_TYPE: IMM = u_type;
74
           `J_TYPE: IMM = j_type;
75
           `CSR_TYPE: IMM = csr_type;
76
           3'b111: IMM = i_type;
77
       endcase
78
    end
79
 
80
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.