OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [soc/] [ram.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
3
// 
4
// Create Date: 06.07.2020 21:38:42
5
// Module Name: ram
6
// Project Name: Steel SoC 
7
// Description: 8 KByte Random Access Memory 
8
// 
9
// Dependencies: -
10
// 
11
// Version 0.01
12
// 
13
//////////////////////////////////////////////////////////////////////////////////
14
 
15
/*********************************************************************************
16
MIT License
17
Copyright (c) 2020 Rafael de Oliveira Calçada
18
Permission is hereby granted, free of charge, to any person obtaining a copy
19
of this software and associated documentation files (the "Software"), to deal
20
in the Software without restriction, including without limitation the rights
21
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
22
copies of the Software, and to permit persons to whom the Software is
23
furnished to do so, subject to the following conditions:
24
The above copyright notice and this permission notice shall be included in all
25
copies or substantial portions of the Software.
26
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32
SOFTWARE.
33
********************************************************************************/
34
 
35
`timescale 1ns / 1ps
36
 
37
module ram(
38
 
39
    input wire CLK,
40
 
41
    input wire [10:0] ADDRA,
42
    input wire [10:0] ADDRB,
43
    input wire [31:0] DINA,
44
    input wire [3:0] WEA,
45
    output wire [31:0] DOUTA,
46
    output wire [31:0] DOUTB
47
 
48
    );
49
 
50
    reg [31:0] ram [0:8191];
51
    reg [10:0] prev_addra;
52
    reg [10:0] prev_addrb;
53
 
54
    integer i;
55
 
56
    // MEMORY INITIALIZATION
57
    initial
58
    begin
59
        for(i = 0; i < 2048;i = i+1) ram[i] = 32'b0;
60
        $readmemh("hello.hex", ram);
61
    end
62
 
63
    always @(posedge CLK) prev_addra <= ADDRA;
64
    always @(posedge CLK) prev_addrb <= ADDRB;
65
 
66
    always @(posedge CLK)
67
    begin
68
        if(WEA[0]) ram[ADDRA][7:0] <= DINA[7:0];
69
        if(WEA[1]) ram[ADDRA][15:8] <= DINA[15:8];
70
        if(WEA[2]) ram[ADDRA][23:16] <= DINA[23:16];
71
        if(WEA[3]) ram[ADDRA][31:24] <= DINA[31:24];
72
    end
73
 
74
    assign DOUTA = ram[prev_addra];
75
    assign DOUTB = ram[prev_addrb];
76
 
77
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.