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[/] [soc/] [soc_top.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
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// 
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// Create Date: 04.07.2020 20:56:52
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// Module Name: soc_top
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// Project Name: Steel SoC 
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// Description: Example system built with Steel Core 
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// 
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// Dependencies: globals.vh
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//               machine_control.v
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//               alu.v
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//               integer_file.v
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//               branch_unit.v
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//               decoder.v
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//               csr_file.v
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//               imm_generator.v
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//               load_unit.v
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//               store_unit.v
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//               steel_top.v
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//               bus_arbiter.v
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//               ram.v
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//               uart_tx.v
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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module soc_top #(
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    parameter BOOT_ADDRESS = 32'h00000014
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    )(
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    input wire CLK, // 100MHz (Nexys4 clock speed)
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    input wire RESET,
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    output wire UART_TX
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    );
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    wire e_irq;
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    wire [31:0] daddr_uart;
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    wire [31:0] daddr_core;
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    wire [31:0] daddr_mem;
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    wire [31:0] dout_uart;
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    wire [31:0] dout_core;
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    wire [31:0] dout_mem;
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    wire wr_req_uart;
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    wire wr_req_core;
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        wire wr_req_mem;
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    wire [31:0] din_uart;
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    wire [31:0] din_core;
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    wire [31:0] din_mem;
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    wire [3:0] wr_mask_core;
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    wire [3:0] wr_mask_mem;
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    wire [31:0] i_addr;
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    wire [31:0] instr;
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        reg clk50mhz = 1'b0;
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        always @(posedge CLK) clk50mhz <= !clk50mhz;
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    steel_top #(
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        .BOOT_ADDRESS(BOOT_ADDRESS)
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        ) core (
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        .CLK(clk50mhz),
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        .RESET(RESET),
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        .REAL_TIME(64'b0),
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        .I_ADDR(i_addr),
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        .INSTR(instr),
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        .D_ADDR(daddr_core),
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        .DATA_OUT(dout_core),
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        .WR_REQ(wr_req_core),
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        .WR_MASK(wr_mask_core),
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        .DATA_IN(din_core),
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        .E_IRQ(1'b0),
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        .T_IRQ(1'b0),
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        .S_IRQ(1'b0)
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        );
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    bus_arbiter ba(
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        .CLK(clk50mhz),
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        .RESET(RESET),
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        .D_ADDR(daddr_core),
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        .DATA_OUT(dout_core),
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        .WR_REQ(wr_req_core),
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        .WR_MASK(wr_mask_core),
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        .DATA_IN(din_core),
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        .D_ADDR_1(daddr_uart),
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        .DATA_OUT_1(dout_uart),
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        .WR_MASK_1(),
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        .WR_REQ_1(wr_req_uart),
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        .DATA_IN_1(din_uart),
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        .D_ADDR_2(daddr_mem),
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        .DATA_OUT_2(dout_mem),
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        .WR_REQ_2(wr_req_mem),
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        .WR_MASK_2(wr_mask_mem),
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        .DATA_IN_2(din_mem)
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        );
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    ram mem(
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        .CLK(clk50mhz),
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        .ADDRA(daddr_mem[12:2]),
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        .ADDRB(i_addr[12:2]),
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        .DINA(dout_mem),
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        .WEA(wr_mask_mem),
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        .DOUTA(din_mem),
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        .DOUTB(instr)
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        );
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    uart_tx utx(
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        .CLK(clk50mhz),
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        .WDATA(dout_uart[7:0]),
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        .WR_EN(wr_req_uart),
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        .RDATA(din_uart),
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        .TX(UART_TX)
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        );
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endmodule

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