OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [vivado/] [steel-core.srcs/] [sim_1/] [imports/] [steel-core/] [rtl/] [bench/] [tb_steel_top.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
3
// 
4
// Create Date: 26.04.2020 20:52:25
5
// Module Name: tb_steel_top
6
// Project Name: Steel Core
7
// Description: Steel Core testbench (Applies all tests from RISC-V Test Suite)
8
// 
9
// Dependencies: globals.vh
10
//               machine_control.v
11
//               alu.v
12
//               integer_file.v
13
//               branch_unit.v
14
//               decoder.v
15
//               csr_file.v
16
//               imm_generator.v
17
//               load_unit.v
18
//               store_unit.v
19
//               steel_top.v
20
// 
21
// Version 0.01
22
// 
23
//////////////////////////////////////////////////////////////////////////////////
24
 
25
/*********************************************************************************
26
 
27
MIT License
28
 
29
Copyright (c) 2020 Rafael de Oliveira Calçada
30
 
31
Permission is hereby granted, free of charge, to any person obtaining a copy
32
of this software and associated documentation files (the "Software"), to deal
33
in the Software without restriction, including without limitation the rights
34
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
35
copies of the Software, and to permit persons to whom the Software is
36
furnished to do so, subject to the following conditions:
37
 
38
The above copyright notice and this permission notice shall be included in all
39
copies or substantial portions of the Software.
40
 
41
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
44
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
46
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
47
SOFTWARE.
48
 
49
********************************************************************************/
50
 
51
`timescale 1ns / 1ps
52
`include "../globals.vh"
53
 
54
module tb_steel_top();
55
 
56
    reg CLK;
57
    reg RESET;
58
    wire [31:0] I_ADDR;
59
    reg [31:0] INSTR;
60
    wire [31:0] D_ADDR;
61
    wire [31:0] DATA_OUT;
62
    wire WR_REQ;
63
    wire [3:0] WR_MASK;
64
    reg [31:0] DATA_IN;
65
    reg E_IRQ;
66
    reg T_IRQ;
67
    reg S_IRQ;
68
 
69
    reg [8*20:0] tests [0:38] = {
70
        "rv32ui-p-addi.mem",
71
        "rv32ui-p-bgeu.mem",
72
        "rv32ui-p-lb.mem",
73
        "rv32ui-p-or.mem",
74
        "rv32ui-p-sltiu.mem",
75
        "rv32ui-p-sub.mem",
76
        "rv32ui-p-add.mem",
77
        "rv32ui-p-blt.mem",
78
        "rv32ui-p-lbu.mem",
79
        "rv32ui-p-sb.mem",
80
        "rv32ui-p-slt.mem",
81
        "rv32ui-p-sw.mem",
82
        "rv32ui-p-andi.mem",
83
        "rv32ui-p-bltu.mem",
84
        "rv32ui-p-lh.mem",
85
        "rv32ui-p-sh.mem",
86
        "rv32ui-p-sltu.mem",
87
        "rv32ui-p-xori.mem",
88
        "rv32ui-p-and.mem",
89
        "rv32ui-p-bne.mem",
90
        "rv32ui-p-lhu.mem",
91
        "rv32ui-p-simple.mem",
92
        "rv32ui-p-srai.mem",
93
        "rv32ui-p-xor.mem",
94
        "rv32ui-p-auipc.mem",
95
        "rv32ui-p-fence_i.mem",
96
        "rv32ui-p-lui.mem",
97
        "rv32ui-p-slli.mem",
98
        "rv32ui-p-sra.mem",
99
        "rv32ui-p-beq.mem",
100
        "rv32ui-p-jal.mem",
101
        "rv32ui-p-lw.mem",
102
        "rv32ui-p-sll.mem",
103
        "rv32ui-p-srli.mem",
104
        "rv32ui-p-bge.mem",
105
        "rv32ui-p-jalr.mem",
106
        "rv32ui-p-ori.mem",
107
        "rv32ui-p-slti.mem",
108
        "rv32ui-p-srl.mem"
109
        };
110
 
111
    steel_top #(
112
 
113
        .BOOT_ADDRESS(32'h00000000)
114
 
115
        ) dut (
116
 
117
        .CLK(CLK),
118
        .RESET(RESET),
119
        .REAL_TIME(64'b0),
120
        .I_ADDR(I_ADDR),
121
        .INSTR(INSTR),
122
        .D_ADDR(D_ADDR),
123
        .DATA_OUT(DATA_OUT),
124
        .WR_REQ(WR_REQ),
125
        .WR_MASK(WR_MASK),
126
        .DATA_IN(DATA_IN),
127
        .E_IRQ(E_IRQ),
128
        .T_IRQ(T_IRQ),
129
        .S_IRQ(S_IRQ)
130
 
131
    );
132
 
133
    reg [31:0] ram [0:16383];
134
    integer i;
135
    integer j;
136
    integer k;
137
 
138
    always
139
    begin
140
        #10 CLK = !CLK;
141
    end
142
 
143
    initial
144
    begin
145
 
146
        for(k = 0; k < 39; k=k+1)
147
        begin
148
 
149
            // LOADS PROGRAM INTO MEMORY 
150
            for(i = 0; i < 65535; i=i+1) ram[i] = 8'b0;
151
            $display("Running %s...", tests[k]);
152
            $readmemh(tests[k],ram);
153
 
154
            // INITIAL VALUES
155
            RESET = 1'b0;
156
            CLK = 1'b0;
157
            E_IRQ = 1'b0;
158
            T_IRQ = 1'b0;
159
            S_IRQ = 1'b0;
160
 
161
            // RESET
162
            #5;
163
            RESET = 1'b1;
164
            #15;
165
            RESET = 1'b0;
166
 
167
            // one second loop
168
            for(j = 0; j < 50000000; j = j + 1)
169
            begin
170
                #20;
171
                if(WR_REQ == 1'b1 && D_ADDR == 32'h00001000)
172
                begin
173
                    $display("Result: %h", DATA_OUT);
174
                    #20;
175
                    j = 50000000;
176
                end
177
            end
178
 
179
        end
180
 
181
        $display("Steel Core testbench done. If all results are 00000001 then everything works fine.");
182
 
183
    end
184
 
185
    always @(posedge CLK or posedge RESET)
186
    begin
187
        if(RESET)
188
        begin
189
            INSTR = ram[I_ADDR[16:2]];
190
            DATA_IN = ram[D_ADDR[16:2]];
191
        end
192
        else
193
        begin
194
            INSTR = ram[I_ADDR[16:2]];
195
            DATA_IN = ram[D_ADDR[16:2]];
196
            if(WR_REQ)
197
            begin
198
                if(WR_MASK[0])
199
                begin
200
                    ram[D_ADDR[16:2]][7:0] <= DATA_OUT[7:0];
201
                end
202
                if(WR_MASK[1])
203
                begin
204
                    ram[D_ADDR[16:2]][15:8] <= DATA_OUT[15:8];
205
                end
206
                if(WR_MASK[2])
207
                begin
208
                    ram[D_ADDR[16:2]][23:16] <= DATA_OUT[23:16];
209
                end
210
                if(WR_MASK[3])
211
                begin
212
                    ram[D_ADDR[16:2]][31:24] <= DATA_OUT[31:24];
213
                end
214
            end
215
        end
216
    end
217
 
218
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.