OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [vivado/] [steel-core.srcs/] [sim_1/] [imports/] [steel-core/] [soc/] [bench/] [tb_soc_top.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
3
// 
4
// Create Date: 11.07.2020 14:55:12
5
// Module Name: tb_soc_top
6
// Project Name: Steel SoC 
7
// Description: Example SoC testbench 
8
// 
9
// Dependencies: globals.vh
10
//               machine_control.v
11
//               alu.v
12
//               integer_file.v
13
//               branch_unit.v
14
//               decoder.v
15
//               csr_file.v
16
//               imm_generator.v
17
//               load_unit.v
18
//               store_unit.v
19
//               steel_top.v
20
//               bus_arbiter.v
21
//               ram.v
22
//               uart_tx.v
23
// 
24
// Version 0.01
25
// 
26
//////////////////////////////////////////////////////////////////////////////////
27
 
28
/*********************************************************************************
29
 
30
MIT License
31
 
32
Copyright (c) 2020 Rafael de Oliveira Calçada
33
 
34
Permission is hereby granted, free of charge, to any person obtaining a copy
35
of this software and associated documentation files (the "Software"), to deal
36
in the Software without restriction, including without limitation the rights
37
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38
copies of the Software, and to permit persons to whom the Software is
39
furnished to do so, subject to the following conditions:
40
 
41
The above copyright notice and this permission notice shall be included in all
42
copies or substantial portions of the Software.
43
 
44
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
47
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
50
SOFTWARE.
51
 
52
********************************************************************************/
53
 
54
module tb_soc_top();
55
 
56
    reg CLK;
57
    reg RESET;
58
    wire UART_TX;
59
 
60
    soc_top #(
61
 
62
        .BOOT_ADDRESS(32'h00000018)
63
 
64
        ) dut (
65
 
66
        .CLK(CLK),
67
        .RESET(RESET),
68
        .UART_TX(UART_TX)
69
    );
70
 
71
    always #10 CLK = !CLK;
72
 
73
    // The purpose of this testbench is to observe the UART waveform
74
 
75
    initial
76
    begin
77
        CLK = 1'b0;
78
        RESET = 1'b1;
79
        #100;
80
        RESET = 1'b0;
81
        $stop();
82
    end
83
 
84
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.