OpenCores
URL https://opencores.org/ocsvn/suslik/suslik/trunk

Subversion Repositories suslik

[/] [suslik/] [branches/] [tlb/] [rtl/] [codecache.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 gorand2
`include "config.v"
2
 
3
module codecache(input clk,input [31:0] addrA,output `muxnet [31:0] dataA,input [511:0] cacheLine,output wire hit,input readen,input insert,input initEntry);
4
  wire tagwe;
5
  wire [31:0] tagAddrA;
6
  wire [31:0] tagAddrW;
7
  wire [115:0] tagDataA;
8
  `muxnet [115:0] tagDataW;
9
  reg  [31:0] tagAddrA_reg;
10
 
11
  wire ram0We,ram1We,ram2We,ram3We;
12
  wire [31:0] ramAddrW;
13
  wire [511:0] ramDataR0;
14
  wire [511:0] ramDataR1;
15
  wire [511:0] ramDataR2;
16
  wire [511:0] ramDataR3;
17
  wire [511:0] ramDataW;
18
  reg  [511:0] cacheLine_reg;
19
 
20
  wire [31:0] pad0;
21
  wire [31:0] pad1;
22
  wire [31:0] pad2;
23
  wire [31:0] pad3;
24
  wire [1:0] pos0;
25
  wire [1:0] pos1;
26
  wire [1:0] pos2;
27
  wire [1:0] pos3;
28
  wire val0;
29
  wire val1;
30
  wire val2;
31
  wire val3;
32
 
33
  wire [1:0] newPos0;
34
  wire [1:0] newPos1;
35
  wire [1:0] newPos2;
36
  wire [1:0] newPos3;
37
 
38
 
39
  `muxnet hit3,hit2,hit1,hit0;
40
  reg readen_reg=0;
41
  reg insert_reg=0;
42
  reg initEntry_reg=0;
43
  reg [31:0] addrA_reg;
44
  reg [115:0] tagDataA_fwd;
45
  wire [115:0] ramTagDataA;
46
  reg tag_fwd=0;
47
 
48
  wire [31:0] dataA0;
49
  wire [31:0] dataA1;
50
  wire [31:0] dataA2;
51
  wire [31:0] dataA3;
52
 
53
  codecacheramtag tag0(clk,tagwe,tagAddrA[11:6],tagAddrW[11:6],ramTagDataA,tagDataW);
54
  codecacheram ram0(clk,ram0We,tagAddrA[11:6],ramAddrW[11:6],ramDataR0,ramDataW);
55
  codecacheram ram1(clk,ram1We,tagAddrA[11:6],ramAddrW[11:6],ramDataR1,ramDataW);
56
  codecacheram ram2(clk,ram2We,tagAddrA[11:6],ramAddrW[11:6],ramDataR2,ramDataW);
57
  codecacheram ram3(clk,ram3We,tagAddrA[11:6],ramAddrW[11:6],ramDataR3,ramDataW);
58
  instr_sel instr_sel0(ramDataR0,tagAddrA_reg[5:2],dataA0);
59
  instr_sel instr_sel1(ramDataR1,tagAddrA_reg[5:2],dataA1);
60
  instr_sel instr_sel2(ramDataR2,tagAddrA_reg[5:2],dataA2);
61
  instr_sel instr_sel3(ramDataR3,tagAddrA_reg[5:2],dataA3);
62
  get_new_pos newpos0(pos0,pos1,pos2,pos3,hit0,hit1,hit2,hit3,newPos0,newPos1,newPos2,newPos3);
63
 
64
  assign tagAddrA=addrA;
65
  assign tagwe=readen_reg || insert_reg || initEntry_reg;
66
  assign tagAddrW=tagAddrA_reg;
67
 
68
  assign tagDataA=tag_fwd ? tagDataA_fwd : ramTagDataA;
69
 
70
  assign { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],pos3,pos2,pos1,pos0,val3,val2,val1,val0 } = tagDataA;
71
  assign pad3[5:0]=6'b0;
72
  assign pad2[5:0]=6'b0;
73
  assign pad1[5:0]=6'b0;
74
  assign pad0[5:0]=6'b0;
75
 
76
  assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,val0 } : 116'b`muxval;
77
  assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,1'b1 } : 116'b`muxval;
78
  assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,1'b1,val0 } : 116'b`muxval;
79
  assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,1'b1,val1,val0 } : 116'b`muxval;
80
  assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,1'b1,val2,val1,val0 } : 116'b`muxval;
81
//  assign tagDataW=(insert_reg && !hit) ? 116'b0 : 116'bz;
82
  assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0,2'b11,2'b10,2'b01,2'b00,1'b0,1'b0,1'b0,1'b0} : 116'b`muxval;
83
  assign tagDataW=(!insert_reg && !readen_reg && !initEntry_reg) ? 116'b0 : 116'b`muxval;
84
 
85
  assign hit3=readen_reg ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
86
  assign hit2=readen_reg ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
87
  assign hit1=readen_reg ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
88
  assign hit0=readen_reg ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
89
 
90
  assign hit3=insert_reg ? (pos3==2'b11) : 1'b`muxval;
91
  assign hit2=insert_reg ? (pos2==2'b11) : 1'b`muxval;
92
  assign hit1=insert_reg ? (pos1==2'b11) : 1'b`muxval;
93
  assign hit0=insert_reg ? (pos0==2'b11) : 1'b`muxval;
94
 
95
  assign hit3=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval;
96
  assign hit2=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval;
97
  assign hit1=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval;
98
  assign hit0=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval;
99
 
100
  assign hit=hit3 || hit2 || hit1 || hit0;
101
 
102
  assign ram0We=insert_reg && hit0;
103
  assign ram1We=insert_reg && hit1;
104
  assign ram2We=insert_reg && hit2;
105
  assign ram3We=insert_reg && hit3;
106
 
107
  assign dataA=hit0 ? dataA0 : 32'b`muxval;
108
  assign dataA=hit1 ? dataA1 : 32'b`muxval;
109
  assign dataA=hit2 ? dataA2 : 32'b`muxval;
110
  assign dataA=hit3 ? dataA3 : 32'b`muxval;
111
  assign dataA= hit ? 32'b`muxval : 32'b0;
112
 
113
  assign ramDataW=cacheLine_reg;
114
  assign ramAddrW=tagAddrA_reg;
115
 
116
  always @(posedge clk)
117
    begin
118
      readen_reg<=readen;
119
      tagAddrA_reg<=tagAddrA;
120
      insert_reg<=insert;
121
      addrA_reg<=addrA;
122
      cacheLine_reg<=cacheLine;
123
      initEntry_reg<=initEntry;
124
      tagDataA_fwd<=ramTagDataA;
125
      tag_fwd<=(readen_reg || insert_reg || initEntry_reg) && (addrA[11:6]==addrA_reg[11:6]);
126
    end
127
 
128
endmodule
129
 
130
module codecacheram(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [511:0] dataA,input [511:0] dataW);
131
  reg [511:0] ram [63:0];
132
 
133
  always @(posedge clk)
134
    begin
135
      dataA<=ram[addrA];
136
      if (we) ram[addrW]<=dataW;
137
    end
138
 
139
endmodule
140
 
141
/*
142
tag for 4 way set-asociative LRU code cache
143
{
144
{pad3,pad2,pad1,pad0}, //4x 26 bit physical address
145
{pos3,pos2,pos1,pos0}, //4xeach 2 bit LRU position, 8 bit
146
{val3,val2,val1,val0}  //4x 1 bit valid entry, 4 bit
147
}
148
length =29*4=116 bit tag
149
*/
150
 
151
module codecacheramtag(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [115:0] dataA,input [115:0] dataW);
152
  reg [115:0] ram [63:0];
153
 
154
  always @(posedge clk)
155
    begin
156
      dataA<=ram[addrA];
157
      if (we) ram[addrW]<=dataW;
158
    end
159
 
160
endmodule
161
 
162
 
163
 
164
module instr_sel(input [511:0] dataIn,input [3:0] sel, output [31:0] instr);
165
  wire [255:0] bit3Data;
166
  wire [127:0] bit2Data;
167
  wire [63:0]  bit1Data;
168
 
169
  assign bit3Data=sel[3] ? dataIn[511:256] : dataIn[255:0];
170
  assign bit2Data=sel[2] ? bit3Data[255:128] : bit3Data[127:0];
171
  assign bit1Data=sel[1] ? bit2Data[127:64] : bit2Data[63:0];
172
  assign instr   =sel[0] ? bit1Data[63:32] : bit1Data[31:0];
173
 
174
endmodule
175
 
176
 
177
module get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3,
178
                   input hit0,input hit1,input hit2,input hit3,
179
                   output `muxnet [1:0] newPos0,output `muxnet [1:0] newPos1,output `muxnet [1:0] newPos2,output `muxnet [1:0] newPos3);
180
  wire hit;
181
 
182
  assign hit=hit0 || hit1 || hit2 || hit3;
183
 
184
  assign newPos0=hit0 ? 0 : 2'b`muxval;
185
  assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1  ) : 2'b`muxval;
186
  assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2  ) : 2'b`muxval;
187
  assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3  ) : 2'b`muxval;
188
 
189
  assign newPos1=hit1 ? 0 : 2'b`muxval;
190
  assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0  ) : 2'b`muxval;
191
  assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2  ) : 2'b`muxval;
192
  assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3  ) : 2'b`muxval;
193
 
194
  assign newPos2=hit2 ? 0 : 2'b`muxval;
195
  assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1  ) : 2'b`muxval;
196
  assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0  ) : 2'b`muxval;
197
  assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3  ) : 2'b`muxval;
198
 
199
  assign newPos3=hit3 ? 0 : 2'b`muxval;
200
  assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1  ) : 2'b`muxval;
201
  assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2  ) : 2'b`muxval;
202
  assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0  ) : 2'b`muxval;
203
 
204
  assign newPos0=hit ? 2'b`muxval : pos0;
205
  assign newPos1=hit ? 2'b`muxval : pos1;
206
  assign newPos2=hit ? 2'b`muxval : pos2;
207
  assign newPos3=hit ? 2'b`muxval : pos3;
208
 
209
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.