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[/] [suslik/] [branches/] [tlb/] [rtl/] [codecache.v] - Blame information for rev 6

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1 2 gorand2
`include "config.v"
2
 
3 6 gorand2
module codecache(
4
  input clk,
5
  input [31:0] addrA,
6
  input [31:0] addrB,
7
  input tlbA;
8
  input tlbB;
9
  output [31:0] dataA,
10
  input [127:0] cacheLine,
11
  output hit,
12
  input readen,
13
  input insert,
14
  input initEntry);
15 2 gorand2
  wire tagwe;
16
  wire [31:0] tagAddrA;
17
  wire [31:0] tagAddrW;
18 6 gorand2
  wire [123:0] tagDataA;
19
  wire [123:0] tagDataW;
20 2 gorand2
  reg  [31:0] tagAddrA_reg;
21
 
22
  wire ram0We,ram1We,ram2We,ram3We;
23
  wire [31:0] ramAddrW;
24 6 gorand2
  wire [127:0] ramDataR0;
25
  wire [127:0] ramDataR1;
26
  wire [127:0] ramDataR2;
27
  wire [127:0] ramDataR3;
28
  wire [127:0] ramDataW;
29
  reg  [127:0] cacheLine_reg;
30 2 gorand2
 
31
  wire [31:0] pad0;
32
  wire [31:0] pad1;
33
  wire [31:0] pad2;
34
  wire [31:0] pad3;
35
  wire [1:0] pos0;
36
  wire [1:0] pos1;
37
  wire [1:0] pos2;
38
  wire [1:0] pos3;
39
  wire val0;
40
  wire val1;
41
  wire val2;
42
  wire val3;
43
 
44
  wire [1:0] newPos0;
45
  wire [1:0] newPos1;
46
  wire [1:0] newPos2;
47
  wire [1:0] newPos3;
48
 
49
 
50 6 gorand2
  wire hit3,hit2,hit1,hit0;
51
  wire hit3A,hit2A,hit1A,hit0A;
52
  wire hit3B,hit2B,hit1B,hit0B;
53
  wire hitA,hitB;
54
 
55 2 gorand2
  reg readen_reg=0;
56
  reg insert_reg=0;
57
  reg initEntry_reg=0;
58
  reg [31:0] addrA_reg;
59 6 gorand2
  reg [31:0] addrB_reg;
60
  reg [123:0] tagDataA_fwd;
61
  wire [123:0] ramTagDataA;
62 2 gorand2
  reg tag_fwd=0;
63
 
64
  wire [31:0] dataA0;
65
  wire [31:0] dataA1;
66
  wire [31:0] dataA2;
67
  wire [31:0] dataA3;
68 6 gorand2
 
69
  codecacheramtag tag0(clk,tagwe,tagAddrA[11:4],tagAddrW[11:4],ramTagDataA,tagDataW);
70
  codecacheram ram0(clk,ram0We,tagAddrA[11:4],ramAddrW[11:4],ramDataR0,ramDataW);
71
  codecacheram ram1(clk,ram1We,tagAddrA[11:4],ramAddrW[11:4],ramDataR1,ramDataW);
72
  codecacheram ram2(clk,ram2We,tagAddrA[11:4],ramAddrW[11:4],ramDataR2,ramDataW);
73
  codecacheram ram3(clk,ram3We,tagAddrA[11:4],ramAddrW[11:4],ramDataR3,ramDataW);
74
  instr_sel instr_sel0(ramDataR0,tagAddrA_reg[3:2],dataA0);
75
  instr_sel instr_sel1(ramDataR1,tagAddrA_reg[3:2],dataA1);
76
  instr_sel instr_sel2(ramDataR2,tagAddrA_reg[3:2],dataA2);
77
  instr_sel instr_sel3(ramDataR3,tagAddrA_reg[3:2],dataA3);
78
  get_new_pos newpos0(pos0,pos1,pos2,pos3,hit0A&tlbA||hit0B&tlbB,
79
    hit1A&tlbA||hit1B&tlbB,hit2A&tlbA||hit2B&tlbB,hit3A&tlbA||hit3B&tlbB,
80
    newPos0,newPos1,newPos2,newPos3);
81 2 gorand2
 
82
  assign tagAddrA=addrA;
83
  assign tagwe=readen_reg || insert_reg || initEntry_reg;
84
  assign tagAddrW=tagAddrA_reg;
85
 
86
  assign tagDataA=tag_fwd ? tagDataA_fwd : ramTagDataA;
87
 
88 6 gorand2
  assign { pad3[31:4],pad2[31:4],pad1[31:4],pad0[31:4],pos3,pos2,pos1,pos0,val3,val2,val1,val0 } = tagDataA;
89
  assign pad3[3:0]=4'b0;
90
  assign pad2[3:0]=4'b0;
91
  assign pad1[3:0]=4'b0;
92
  assign pad0[3:0]=4'b0;
93 2 gorand2
 
94 6 gorand2
  assign tagDataW=readen_reg ? { pad3[31:4],pad2[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,val0 } : 124'bz;
95
  assign tagDataW=(insert_reg && hit0) ? { pad3[31:4],pad2[31:4],pad1[31:4],tagAddrA_reg[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,1'b1 } : 124'bz;
96
  assign tagDataW=(insert_reg && hit1) ? { pad3[31:4],pad2[31:4],tagAddrA_reg[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,1'b1,val0 } : 124'bz;
97
  assign tagDataW=(insert_reg && hit2) ? { pad3[31:4],tagAddrA_reg[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,1'b1,val1,val0 } : 124'bz;
98
  assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,1'b1,val2,val1,val0 } : 124'bz;
99 2 gorand2
//  assign tagDataW=(insert_reg && !hit) ? 116'b0 : 116'bz;
100 6 gorand2
  assign tagDataW=initEntry_reg ? { 28'b0,28'b0,28'b0,28'b0,2'b11,2'b10,2'b01,2'b00,1'b0,1'b0,1'b0,1'b0} : 124'bz;
101
  assign tagDataW=(!insert_reg && !readen_reg && !initEntry_reg) ? 124'b0 : 124'bz;
102 2 gorand2
 
103 6 gorand2
  assign hit3A=readen_reg & val3 && (pad3[31:4]==tagAddrA_reg[31:4]) : 1'bz;
104
  assign hit2A=readen_reg & val2 && (pad2[31:4]==tagAddrA_reg[31:4]) : 1'bz;
105
  assign hit1A=readen_reg & val1 && (pad1[31:4]==tagAddrA_reg[31:4]) : 1'bz;
106
  assign hit0A=readen_reg & val0 && (pad0[31:4]==tagAddrA_reg[31:4]) : 1'bz;
107 2 gorand2
 
108 6 gorand2
  assign hit3B=readen_reg & val3 && (pad3[31:4]==tagAddrB_reg[31:4]) : 1'bz;
109
  assign hit2B=readen_reg & val2 && (pad2[31:4]==tagAddrB_reg[31:4]) : 1'bz;
110
  assign hit1B=readen_reg & val1 && (pad1[31:4]==tagAddrB_reg[31:4]) : 1'bz;
111
  assign hit0B=readen_reg & val0 && (pad0[31:4]==tagAddrB_reg[31:4]) : 1'bz;
112 2 gorand2
 
113 6 gorand2
  assign hit3=insert_reg & (pos3==2'b11);
114
  assign hit2=insert_reg & (pos2==2'b11);
115
  assign hit1=insert_reg & (pos1==2'b11);
116
  assign hit0=insert_reg & (pos0==2'b11);
117 2 gorand2
 
118 6 gorand2
 
119
  assign hitA=hit3A || hit2A || hit1A || hit0A;
120
  assign hitB=hit3B || hit2B || hit1B || hit0B;
121 2 gorand2
 
122
  assign ram0We=insert_reg && hit0;
123
  assign ram1We=insert_reg && hit1;
124
  assign ram2We=insert_reg && hit2;
125
  assign ram3We=insert_reg && hit3;
126
 
127 6 gorand2
  assign dataA=hit0A & tlbA ? dataA0 : 32'bz;
128
  assign dataA=hit1A & tlbA ? dataA1 : 32'bz;
129
  assign dataA=hit2A & tlbA ? dataA2 : 32'bz;
130
  assign dataA=hit3A & tlbA ? dataA3 : 32'bz;
131
  assign dataA=hit0B & tlbB ? dataA0 : 32'bz;
132
  assign dataA=hit1B & tlbB ? dataA1 : 32'bz;
133
  assign dataA=hit2B & tlbB ? dataA2 : 32'bz;
134
  assign dataA=hit3B & tlbB ? dataA3 : 32'bz;
135
  assign dataA= hitA & tlbA || hitB & tlbB ? 32'bz : 32'b0;
136 2 gorand2
 
137
  assign ramDataW=cacheLine_reg;
138
  assign ramAddrW=tagAddrA_reg;
139
 
140 6 gorand2
  assign hit=hitA & tlbA || hitB & tlbB;
141
 
142 2 gorand2
  always @(posedge clk)
143
    begin
144
      readen_reg<=readen;
145
      tagAddrA_reg<=tagAddrA;
146
      insert_reg<=insert;
147
      addrA_reg<=addrA;
148 6 gorand2
      addrB_reg<=addrB;
149 2 gorand2
      cacheLine_reg<=cacheLine;
150
      initEntry_reg<=initEntry;
151
      tagDataA_fwd<=ramTagDataA;
152 6 gorand2
      tag_fwd<=(readen_reg || insert_reg || initEntry_reg) && (addrA[11:4]==addrA_reg[11:4]);
153 2 gorand2
    end
154
 
155
endmodule
156
 
157 6 gorand2
module codecacheram(input clk,input we,input [7:0] addrA,input [7:0] addrW,output [127:0] dataA,input [127:0] dataW);
158
  reg [127:0] ram [127:0];
159 2 gorand2
 
160 6 gorand2
  reg [7:0] addrA_reg;
161
 
162
  assign dataA=ram[addrA_reg];
163
 
164 2 gorand2
  always @(posedge clk)
165
    begin
166
      if (we) ram[addrW]<=dataW;
167 6 gorand2
      addrA_reg<=addrA;
168 2 gorand2
    end
169
 
170
endmodule
171
 
172
/*
173
tag for 4 way set-asociative LRU code cache
174
{
175
{pad3,pad2,pad1,pad0}, //4x 26 bit physical address
176
{pos3,pos2,pos1,pos0}, //4xeach 2 bit LRU position, 8 bit
177
{val3,val2,val1,val0}  //4x 1 bit valid entry, 4 bit
178
}
179
length =29*4=116 bit tag
180
*/
181
 
182 6 gorand2
module codecacheramtag(input clk,input we,input [7:0] addrA,input [7:0] addrW,output reg [123:0] dataA,input [123:0] dataW);
183
  reg [123:0] ram [63:0];
184 2 gorand2
 
185 6 gorand2
  reg [7:0] addrA_reg;
186
  assign dataA=ram[addrA_reg];
187
 
188 2 gorand2
  always @(posedge clk)
189
    begin
190 6 gorand2
      addrA_reg<=addrA;
191 2 gorand2
      if (we) ram[addrW]<=dataW;
192
    end
193
 
194
endmodule
195
 
196
 
197
 
198 6 gorand2
module instr_sel(input [127:0] dataIn,input [1:0] sel, output [31:0] instr);
199 2 gorand2
  wire [63:0]  bit1Data;
200
 
201 6 gorand2
  assign bit1Data=sel[1] ? dataIn[127:64] : dataIn[63:0];
202 2 gorand2
  assign instr   =sel[0] ? bit1Data[63:32] : bit1Data[31:0];
203
 
204
endmodule
205
 
206
 
207
module get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3,
208
                   input hit0,input hit1,input hit2,input hit3,
209 6 gorand2
                   output wire [1:0] newPos0,output wire [1:0] newPos1,output wire [1:0] newPos2,output wire [1:0] newPos3);
210 2 gorand2
  wire hit;
211
 
212
  assign hit=hit0 || hit1 || hit2 || hit3;
213
 
214 6 gorand2
  assign newPos0=hit0 ? 0 : 2'bz;
215
  assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1  ) : 2'bz;
216
  assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2  ) : 2'bz;
217
  assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3  ) : 2'bz;
218 2 gorand2
 
219 6 gorand2
  assign newPos1=hit1 ? 0 : 2'bz;
220
  assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0  ) : 2'bz;
221
  assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2  ) : 2'bz;
222
  assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3  ) : 2'bz;
223 2 gorand2
 
224 6 gorand2
  assign newPos2=hit2 ? 0 : 2'bz;
225
  assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1  ) : 2'bz;
226
  assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0  ) : 2'bz;
227
  assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3  ) : 2'bz;
228 2 gorand2
 
229 6 gorand2
  assign newPos3=hit3 ? 0 : 2'bz;
230
  assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1  ) : 2'bz;
231
  assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2  ) : 2'bz;
232
  assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0  ) : 2'bz;
233 2 gorand2
 
234 6 gorand2
  assign newPos0=hit ? 2'bz : pos0;
235
  assign newPos1=hit ? 2'bz : pos1;
236
  assign newPos2=hit ? 2'bz : pos2;
237
  assign newPos3=hit ? 2'bz : pos3;
238 2 gorand2
 
239
endmodule

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