OpenCores
URL https://opencores.org/ocsvn/suslik/suslik/trunk

Subversion Repositories suslik

[/] [suslik/] [trunk/] [rtl/] [cpu.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 gorand2
 
2
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr);
3
 
4
  input [31:0] instr, val1, val2;
5
  output [31:0] valres;
6
  output wire wrtval,cjmpinstr;
7
  output cjmp;
8
  input [31:0] const1;
9
  input [31:0] retaddr;
10
  wire [5:0] code;
11
  wire [31:0] valcmp;
12
  wire CF,NF,VF,ZF;
13
 
14
  /*
15
    wrtval=1 if valres needs to be stored in register.
16
    cjmpinstr=1 if compare and jump instruction
17
    cjmp=1 if jump taken 0 otherwise (only valid if cjmpinstr=1)
18
  */
19
 
20
  //assign const1={{16{instr[31]}},instr[31:21],instr[15:11]};
21
  assign code=instr[5:0];
22
 
23
  assign valres=(code==0) ? {const1[15:0],val1[15:0]}    : 32'bz;
24
  assign valres=(code==1) ? const1        : 32'bz;
25
  assign valres=(code==2) ? val1 & val2            : 32'bz;
26
  assign valres=(code==3) ? val1 & const1 : 32'bz;
27
  assign valres=(code==4) ? val1 | val2            : 32'bz;
28
  assign valres=(code==5) ? val1 | const1 : 32'bz;
29
  assign valres=(code==6) ? val1 ^ val2            : 32'bz;
30
  assign valres=(code==7) ? val1 ^ const1 : 32'bz;
31
  assign valres=(code==8) ? val1 + val2            : 32'bz;
32
  assign valres=(code==9) ? val1 + const1 : 32'bz;
33
  assign valres=(code==10)? val1 - val2            : 32'bz;
34
  assign valres=(code==11)? val1 - const1 : 32'bz;
35
  //12=no-op
36
  assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
37
  assign valres=(code==46) ? retaddr : 32'bz;
38
  assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
39
  assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
40
  assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
41
  assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
42
  assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
43
  assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
44
 
45
  assign valres=wrtval ? 32'bz : 32'b0;
46
 
47
  assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
48
 
49
  //flags for compare &jump
50
  assign {CF,valcmp}=val1 - val2;
51
  assign NF=valcmp[31];
52
  assign ZF=(val1==val2);
53
  assign VF=(val1[31] & !val2[31] & !valcmp[31]) | (!val1[31] & val2[31] & valcmp[31]);
54
 
55
  assign cjmpinstr=((code>=32)&&(code<=45));
56
 
57
  assign cjmp= (code==32) ? (CF)              : 1'bz;
58
  assign cjmp= (code==33) ? (!CF)             : 1'bz;
59
  assign cjmp= (code==34) ? (ZF)              : 1'bz;
60
  assign cjmp= (code==35) ? (!ZF)             : 1'bz;
61
  assign cjmp= (code==36) ? (CF ^ ZF)         : 1'bz;
62
  assign cjmp= (code==37) ? !(CF ^ ZF)        : 1'bz;
63
  assign cjmp= (code==38) ? (NF)              : 1'bz;
64
  assign cjmp= (code==39) ? !(NF)             : 1'bz;
65
  assign cjmp= (code==40) ? (VF ^ NF)         : 1'bz;
66
  assign cjmp= (code==41) ? !(VF ^ NF)        : 1'bz;
67
  assign cjmp= (code==42) ? ((VF ^ NF) | ZF)  : 1'bz;
68
  assign cjmp= (code==43) ? !((VF ^ NF) | ZF) : 1'bz;
69
  assign cjmp= (code==44) ? (VF)              : 1'bz;
70
  assign cjmp= (code==45) ? (!VF)             : 1'bz;
71
 
72
  assign cjmp= cjmpinstr ? 1'bz : 1'b0;
73
 
74
endmodule
75
 
76
module subagu(input clk, input stall,input [4:0] stginhibit,input [31:0] baseOP,input [31:0] instr0,input [31:0] instr, input [31:0] instrprev,output wire [31:0] addr,output wire aguwrtval,output wire delayedstall, output reg [1:0] readsz, output wire readen,output wire writeen, input [31:0] offset);
77
  wire [4:0] instr_rA,instrprev_rF;
78
  wire writeinstrprev;
79
  wire [5:0] instrprev_code,instr_code,instr0_code;
80
  wire instr0_load,instr0_store,instr_load,instr_store;
81
  reg aguwrtval_reg;
82
  reg delayedstall_reg=0;
83
  //reg readen_reg;
84
  //wire [18:0] shortaddr;
85
 
86
  assign instr_rA=instr[10:6];
87
  assign instrprev_rF=instrprev[20:16];
88
  assign instrprev_code=instrprev[5:0];
89
  assign instr_code=instr[5:0];
90
  assign instr0_code=instr0[5:0];
91
 
92
  assign writereginstrprev=((instrprev_code<=11) || (instrprev_code==13) ||
93
    ((instrprev_code >= 56) && (instrprev_code <=58))) && !stginhibit[4] && !stall; //remove !stall ??
94
  assign delayedstall=writereginstrprev && (instr_load || instr_store) && ( instr_rA==instrprev_rF ) && (!stginhibit[3]); //add constant add stalless support
95
 
96
  assign instr_load=(instr_code >= 56) && (instr_code <=58);
97
  assign instr_store=(instr_code >= 60) && (instr_code <=62);
98
  assign instr0_load=(instr0_code >= 56) && (instr0_code <=58);
99
  assign instr0_store=(instr0_code >= 60) && (instr0_code <=62);
100
 
101
  assign addr=baseOP + offset;
102
  //assign shortaddr=baseOP[18:0] + offset[18:0];
103
 
104
  assign readen=instr_load && !stall && !stginhibit[3];
105
  assign writeen=instr_store && !stall && !stginhibit[3] && !delayedstall_reg;
106
  assign aguwrtval=!stall && !stginhibit[4] && aguwrtval_reg;
107
 
108
  always @(posedge clk)
109
    begin
110
      if (!stall && !stginhibit[3]) aguwrtval_reg<=instr_load;
111
      ///*if (!stall && !stginhibit[2]) */readen_reg<=instr0_load;
112
      if (!stall && !stginhibit[2])
113
        case (instr0_code)
114
          56: readsz<=2;
115
          57: readsz<=1;
116
          58: readsz<=0;
117
          60: readsz<=2;
118
          61: readsz<=1;
119
          62: readsz<=0;
120
          default: readsz<=0;
121
        endcase
122
      delayedstall_reg<=delayedstall;
123
    end
124
 
125
endmodule
126
 
127
 
128
module regfileint0(clk,we,rA,rB,rC,rF,dataA,dataB,dataC,dataF);
129
  input [4:0] rA,rB,rC,rF;
130
  output wire [31:0] dataA,dataB,dataC;
131
  input [31:0] dataF;
132
  input clk,we;
133
  reg [31:0] regs [31:0];
134
 
135
  regram ram0(clk,we,rA,rF,dataA,dataF);
136
  regram ram1(clk,we,rB,rF,dataB,dataF);
137
  regram ram2(clk,we,rC,rF,dataC,dataF);
138
 
139
endmodule
140
 
141
module regram(input clk,input we,input [4:0] rA, input [4:0] rF, output reg [31:0] dataA, input [31:0] dataF);
142
  reg [31:0] regs[31:0];
143
  always @(posedge clk)
144
    begin
145
      dataA<=regs[rA];
146
      if (we) regs[rF]<=dataF;
147
    end
148
endmodule
149
 
150
module ioinstr(input clk,input stall, input [4:0] stginhibit,input [31:0] instr,input [31:0] val1,input [31:0] val2, output [31:0] valres, input multiCycleStall,
151
               output wire wrtVal, output wire doStall, output wire keepStalling,
152
               output wire [31:0] ioBusAddr,output reg [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
153
               output wire ioBusWr,output wire ioBusRd);
154
 
155
wire [5:0] code;
156
wire [5:0] auxCode;
157
reg keepStalling_reg=0;
158
reg [31:0] inputValue;
159
assign code=instr[5:0];
160
assign auxCode=instr[26:21];
161
assign doStall=(code==31) && !multiCycleStall && !stall && !stginhibit[4];
162
assign wrtVal=multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2)) && !stall && !stginhibit[4];
163
assign ioBusAddr=val1;
164
assign ioBusOut=val2;
165
 
166
assign ioBusOut=val2;
167
assign ioBusAddr=val1;
168
assign ioBusWr=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==4) || (auxCode==5) || (auxCode==6));
169
assign ioBusRd=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2));
170
assign valres=inputValue;
171
 
172
assign keepStalling=keepStalling_reg;
173
 
174
always @(auxCode)
175
  begin
176
    case(auxCode)
177
      0,4: ioBusSize=0;
178
      1,5: ioBusSize=1;
179
      2,6: ioBusSize=2;
180
      default: ioBusSize=0;
181
    endcase
182
  end
183
 
184
always @(posedge clk)
185
  begin
186
    if (!stall && !stginhibit[4] && (code==31) && !multiCycleStall)
187
      begin
188
        keepStalling_reg<=1;
189
      end
190
    if (ioBusRdy)
191
      begin
192
        keepStalling_reg<=0;
193
      end
194
    if (ioBusRdy)
195
      begin
196
        inputValue<=ioBusIn;
197
      end
198
  end
199
 
200
endmodule
201
 
202
module brpred(input clk,input stall, input [4:0] stginhibit,input [31:0] fetchaddr, output wire hit, output wire [31:0] branchinstr,
203
              output wire [31:0] nextaddr,output wire branchtaken,
204
              input [31:0] insertaddr, input [31:0] insertinstr,input [31:0] inserttargetnext,input inserttaken,input jumpinstr,output wire addrMismatch);
205
  wire wen;
206
  wire [5:0] ramAddrB;
207
  wire [96:0] ramDataA;
208
  wire [96:0] ramDataB;
209
  wire [96:0] dataA;
210
  reg [31:0] fetchaddr_reg=0;
211
  reg branchtaken3;
212
  reg branchtaken4;
213
  reg branchtaken5;
214
  reg wen_reg=0;
215
  reg fwd;
216
  reg [96:0] fwdData;
217
  reg init=1;
218
  reg [5:0] initcount=63;
219
 
220
  reg [31:0] nextaddr3;
221
  reg [31:0] nextaddr4;
222
  reg [31:0] nextaddr5;
223
 
224
  brpred_ram ram0(clk,fetchaddr[7:2],ramAddrB,wen, ramDataA, ramDataB);
225
 
226
  assign dataA=fwd ? fwdData : ramDataA;
227
 
228
  assign hit=(dataA[63:32]==fetchaddr_reg);
229
  assign branchinstr=dataA[31:0];
230
  assign branchtaken=dataA[96];
231
  assign nextaddr=dataA[95:64];
232
 
233
  assign wen=((!stall && !stginhibit[4]) && (branchtaken5 ^ inserttaken) && jumpinstr) | init; //only write on failed prediction
234
  assign ramDataB=(!init) ? {inserttaken,inserttargetnext,insertaddr,insertinstr} : {1'b0,32'b0,32'b11,32'b0};
235
  assign ramAddrB= init ? initcount : insertaddr[7:2];
236
 
237
  assign addrMismatch=jumpinstr && (inserttargetnext != nextaddr5) && branchtaken5;
238
 
239
  always @(posedge clk)
240
    begin
241
      wen_reg<=wen;
242
      fwd<=wen && (ramAddrB == fetchaddr[7:2]);
243
      fwdData<=ramDataB;
244
 
245
      if (init)
246
        begin
247
          initcount<=initcount-1;
248
          if (initcount==0) init<=0;
249
        end
250
 
251
      if (!stall)
252
        begin
253
          fetchaddr_reg<=fetchaddr;
254
        end
255
      if (!stall && !stginhibit[1])
256
        begin
257
          branchtaken3<=hit && branchtaken;
258
          nextaddr3<=nextaddr;
259
        end
260
      if (!stall && !stginhibit[2])
261
        begin
262
          branchtaken4<=branchtaken3;
263
          nextaddr4<=nextaddr3;
264
        end
265
      if (!stall && !stginhibit[3])
266
        begin
267
          branchtaken5<=branchtaken4;
268
          nextaddr5<=nextaddr4;
269
        end
270
      if (!stall && !stginhibit[4])
271
        begin
272
        end
273
    end
274
endmodule
275
 
276
module brpred_ram(input clk, input [5:0] addrA, input [5:0] addrB, input wen, output reg [96:0] dataA, input [96:0] dataB);
277
  reg [96:0] ram[63:0];
278
  always @(posedge clk)
279
    begin
280
      dataA<=ram[addrA];
281
      if (wen) ram[addrB]<=dataB;
282
    end
283
endmodule
284
 
285
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
286
              input [511:0] busInput,output wire [511:0] busOutput,
287
              output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
288
              output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy);
289
  wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
290
  reg [31:0] readaddr_reg;
291
  reg [4:0] stginhibit=5'b11110;
292
  reg [4:0] stginhibit_wrt;
293
  reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
294
  reg stall0=0;
295
  wor stall;
296
  wire [4:0] rA0,rB0,rC,rF0,rFprev,rFprevprev;
297
  //reg [31:0] cjmpoff;
298
  reg [4:0] rA,rB,rF,rAprev,rBprev;
299
  wire intregwe;
300
  wire [31:0] intregdataF;
301
  wire [31:0] intregdataA,intregdataB,intregdataC;
302
  wire [31:0] opA,opB,opC,opF;
303
  reg rAfwd,rBfwd,rCfwd,rAfwd0,rBfwd0,rCfwd0;
304
  reg cycle1prev=0;
305
  reg [31:0] instr0=0;
306
  //reg [31:0] reg_instr0;
307
  wire aluwrtval,alucjmpinstr,alucjmp;
308
  //reg regfwrt=0;
309
  reg [31:0] regfwd;
310
  wire [31:0] aguaddr;
311
  wire agustall,aguwrtval;
312
  wire [1:0] agureadsz;
313
  wire agureaden;
314
  wire aguwriteen;
315
  reg agureaden_reg;
316
  reg aguwriteen_reg;
317
  reg agustall_reg=0;
318
  //aguwrtval ignores exceptions for now
319
  reg [31:0] cjmpoffset;
320
  reg [31:0] cjmpoffset0;
321
  reg [31:0] cjmpaddr;
322
  wire brpred_hit;
323
  wire [31:0] brpred_instr;
324
  wire [31:0] brpred_nextaddr;
325
  wire brpred_taken;
326
  wire [31:0] brpred_instertaddr;
327
  wire [31:0] brpred_instertinstr;
328
  wire [31:0] brpred_insertnextaddr;
329
  wire brpred_inserttaken;
330
  wire brpred_jumpinstr;
331
  wire brpred_addrMismatch;
332
 
333
  reg brtaken3,brtaken4,brtaken5;
334
 
335
  reg init=1;
336
  reg ccInit=1;
337
  reg dcInit=1;
338
  reg [6:0] initcount=66;
339
  reg [5:0] ccInitCount=63;
340
  reg [5:0] dcInitCount=63;
341
  reg [4:0] codeMiss=0;
342
  wire [31:0] ccFetchAddr;
343
  //wire [511:0] cacheLineInput;
344
  wire ccHit,ccReadEn,ccInsert;
345
  reg ccInsertInProgress_tsk=0;
346
  reg ccInsertRamReq_tsk=0;
347
  reg ccInsertInsert_tsk=0;
348
  reg ccInsertWait1_tsk=0;
349
  reg ccInsertWait2_tsk=0;
350
 
351
  wire [31:0] dcAddr;
352
  wire [511:0] dcDataA;
353
  wire [511:0] dcDataWriteBack;
354
  reg  [511:0] dcDataWriteBack_reg;
355
  wire dcHit;
356
  wire dcReadEn,dcWriteEn,dcInsert,dcInitEntry;
357
  reg dcInsertInProgress_tsk=0;
358
  reg dcInsertRamReq_tsk=0;
359
  reg dcInsertInsert_tsk=0;
360
  reg dcInsertCheckDirty_tsk=0;
361
  reg dcInsertWriteBack_tsk=0;
362
  reg [31:0] dcReadAddr;
363
  reg [31:0] dcOldAddr_reg;
364
  wire [31:0] dcOldAddr;
365
 
366
  reg [31:0] constBits; // contains the constant bits
367
  reg [31:0] constBits4;
368
  reg prevUpperBits=0; //bit 0 set => constBits countains the upper constant bits of the next instruction
369
 
370
  wire [31:0] retAddr;
371
  wire uJmpInstr;
372
  reg [31:0] aguaddr_reg;
373
 
374
  reg [4:0] multiCycleStall=0;
375
 
376
  wire [31:0] ioInstrResult;
377
  wire wasGlobalStall=multiCycleStall[4];
378
  wire ioInstrWrtVal;
379
  wire ioInstrDoStall;
380
  wire ioInstrKeepStalling;
381
 
382
 
383
  //dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
384
  datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
385
  regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
386
  aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr);
387
  ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
388
                   ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
389
  subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
390
  brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
391
                 brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
392
  codecache codecache0(clk,ccFetchAddr,fetchdata,busInput,ccHit,ccReadEn,ccInsert,ccInit);
393
 
394
  assign dummy=stginhibit[4:1];
395
  assign fetchaddr=!(!stall && !stginhibit[1] && brpred_hit&&brpred_taken) ? IP : brpred_nextaddr;
396
  assign stall=init || ccInsertInProgress_tsk || dcInsertInProgress_tsk || ioInstrKeepStalling;
397
 
398
  assign readdata=dcDataA[31:0];
399
  assign dcReadEn=agureaden && !agustall;
400
  assign dcWriteEn=aguwriteen && !agustall;
401
  assign dcInsert=dcInsertInsert_tsk && busDataReady;
402
  assign dcInitEntry=dcInit;
403
 
404
  assign dcAddr=dcInit ? { 20'b0,dcInitCount,6'b0} : 32'bz;
405
  assign dcAddr=(dcReadEn || dcWriteEn) ? readaddr : 32'bz;
406
  assign dcAddr=dcInsert ? dcReadAddr : 32'bz;
407
  assign dcAddr=(!dcInit && !dcReadEn && !dcWriteEn && !dcInsert) ? 32'b0 : 32'bz;
408
 
409
  assign ccFetchAddr=ccInit ? { 20'b0,ccInitCount,6'b0} : 32'bz;
410
  assign ccFetchAddr=(!ccInit && !ccInsertInsert_tsk)? fetchaddr : 32'bz; //that should change to accomodate cache line insert
411
  assign ccFetchAddr=ccInsertInsert_tsk ? IP & 32'hffff_ffc0 : 32'bz;
412
 
413
  assign ccReadEn=!stall && !codeMiss[1] && !ccInit && !init;
414
  assign ccInsert=ccInsertInsert_tsk && busDataReady;
415
 
416
  assign busAddr=ccInsertRamReq_tsk ? IP & 32'hffff_ffc0 :32'bz;
417
  assign busAddr=dcInsertRamReq_tsk ? dcReadAddr & 32'hffff_ffc0: 32'bz;
418
  assign busAddr=dcInsertWriteBack_tsk ? dcOldAddr_reg : 32'bz;
419
  assign busAddr=(!ccInsertRamReq_tsk && !dcInsertRamReq_tsk && !dcInsertWriteBack_tsk) ? 32'b0 : 32'bz;
420
 
421
  assign busRead=(ccInsertRamReq_tsk || dcInsertRamReq_tsk) && busEnRead;
422
  assign busWrite=dcInsertWriteBack_tsk && busEnWrite;
423
 
424
  assign dcDataWriteBack=dcDataA;
425
  assign busOutput=dcDataWriteBack_reg;
426
 
427
  assign rA0=instr0[10:6];
428
  assign rB0=instr0[15:11];
429
  assign rF0=instr0[20:16];
430
  assign rC=instr0[10:6];
431
 
432
  assign intregwe=!stall && !stginhibit[4] && (aluwrtval || aguwrtval) && (!agustall_reg) && !((agureaden_reg || aguwriteen_reg) && !dcHit); // adjust for other cases ie mem read-done;
433
  assign intregdataF= aguwrtval ? readdata : opF; //adjust for ie mem read-done
434
  assign opA=rAfwd ? regfwd : intregdataA;
435
  assign opB=rBfwd ? regfwd : intregdataB;
436
  assign opC=rCfwd ? regfwd : intregdataC;
437
 
438
  //assign instr0=fetchdata; //change for branch prediction
439
 
440
  assign rFprev=instr[20:16];
441
  assign rFprevprev=instr4[20:16];
442
  //assign rAfwd=(rA==rFprev);
443
  //assign rBfwd=(rB==rFprev);
444
  //assign intregdataF=opF;
445
 
446
  assign readaddr=aguaddr;
447
 
448
  assign brpred_jumpinstr=alucjmpinstr || uJmpInstr;
449
  assign brpred_inserttaken=alucjmp || uJmpInstr;
450
  assign brpred_instertinstr=instr4;
451
  assign brpred_instertaddr=IP5;
452
  assign brpred_insertnextaddr=alucjmpinstr ? cjmpaddr : aguaddr_reg ;
453
 
454
  assign retAddr=IP5+4;
455
  assign uJmpInstr=(instr4[5:0]==46 || instr4[5:0]==47);
456
 
457
  //regfwrt<=0;
458
  always @(posedge clk)
459
    begin
460
      if (init)
461
        begin
462
          initcount<=initcount-1;
463
          if (initcount==0) init<=0;
464
        end
465
      if (ccInit)
466
        begin
467
          ccInitCount<=ccInitCount-1;
468
          if (ccInitCount==0) ccInit<=0;
469
        end
470
      if (dcInit)
471
        begin
472
          dcInitCount<=dcInitCount-1;
473
          if (dcInitCount==0) dcInit<=0;
474
        end
475
      if (ccInsertRamReq_tsk && busEnRead)
476
        begin
477
          ccInsertRamReq_tsk<=0;
478
          ccInsertInsert_tsk<=1;
479
        end
480
      if (ccInsertInsert_tsk && busDataReady)
481
        begin
482
          ccInsertInsert_tsk<=0;
483
          ccInsertWait1_tsk<=1;
484
        end
485
      if (ccInsertWait1_tsk)
486
        begin
487
          ccInsertWait1_tsk<=0;
488
          ccInsertWait2_tsk<=1;
489
        end
490
      if (ccInsertWait2_tsk)
491
        begin
492
          ccInsertWait2_tsk<=0;
493
          ccInsertInProgress_tsk<=0;
494
        end
495
      if (dcInsertRamReq_tsk && busEnRead)
496
        begin
497
          dcInsertRamReq_tsk<=0;
498
          dcInsertInsert_tsk<=1;
499
        end
500
      if (dcInsertInsert_tsk && busDataReady)
501
        begin
502
          dcInsertInsert_tsk<=0;
503
          dcInsertCheckDirty_tsk<=1;
504
        end
505
      if (dcInsertCheckDirty_tsk)
506
        begin
507
          dcInsertCheckDirty_tsk<=0;
508
          if (dcHit)
509
            begin
510
              dcInsertWriteBack_tsk<=1;
511
              dcOldAddr_reg<=dcOldAddr;
512
              dcDataWriteBack_reg<=dcDataWriteBack;
513
            end
514
          else
515
            begin
516
              dcInsertInProgress_tsk<=0;
517
            end
518
        end
519
      if (dcInsertWriteBack_tsk && busEnWrite)
520
        begin
521
          dcInsertWriteBack_tsk<=0;
522
          dcInsertInProgress_tsk<=0;
523
        end
524
      //stginhibit_wrt=stginhibit;
525
      if (stginhibit[1]) stginhibit_wrt[2]=1;
526
      if (stginhibit[2]) stginhibit_wrt[3]=1;
527
      if (stginhibit[3]) stginhibit_wrt[4]=1;
528
      agustall_reg<=agustall;
529
      agureaden_reg<=agureaden;
530
      aguwriteen_reg<=aguwriteen;
531
      readaddr_reg<=readaddr;
532
      //cycle 1
533
      if (!stall)
534
        begin
535
         stginhibit[1]<=0;
536
         cycle1prev<=1;
537
         IP<=fetchaddr+4;
538
         IP2<=fetchaddr;
539
         multiCycleStall[1]<=multiCycleStall[0];
540
         multiCycleStall[0]<=0;
541
        end
542
      else  cycle1prev<=0;
543
 
544
      //cycle 2
545
      if (!stall && !stginhibit[1])
546
        begin
547
          stginhibit[2]<=0;
548
          IP3<=IP2;
549
          multiCycleStall[2]<=multiCycleStall[1];
550
          if (!(brpred_hit&&brpred_taken)) instr0<=ccHit ? fetchdata : 32'b01100;
551
            else instr0<=brpred_instr;
552
          brtaken3<=(brpred_hit&&brpred_taken);
553
          if (!ccHit)
554
            begin
555
              codeMiss[1]<=1;
556
              codeMiss[2]<=1;
557
            end
558
          if (codeMiss[1]) codeMiss[2]<=1;
559
 
560
        end
561
      //cycle 3
562
      if (!stall && !stginhibit[2])
563
        begin
564
          instr<=instr0;
565
          //reg_instr0<=fetchdata;
566
          stginhibit[3]<=0;
567
          multiCycleStall[3]<=multiCycleStall[2];
568
          IP4<=IP3;
569
          rA<=instr0[10:6];
570
          rB<=instr0[15:11];
571
          brtaken4<=brtaken3;
572
          codeMiss[3]<=codeMiss[2];
573
          cjmpoffset0<={ {14{instr0[31]}}, instr0[31:16],2'b0 };
574
          if (instr0[5:0]==30) //upper bits instr
575
            begin
576
              prevUpperBits<=1;
577
              constBits[31:16]<=instr0[31:16];
578
            end
579
          else
580
            begin
581
              prevUpperBits<=0;
582
            end
583
          if (instr0[5:0]==60 || instr0[5:0]==61 || instr0[5:0]==62) //store instr
584
            begin
585
              constBits[15:0]<=instr0[31:16];
586
            end
587
          else  //non-store instr
588
            begin
589
              constBits[15:0]<={instr0[31:21],instr0[15:11]};
590
            end
591
          if (!prevUpperBits) constBits[31:16]<={16{instr0[31]}};
592
        end
593
      //cycle 4
594
      if (!stall && !stginhibit[3])
595
        begin
596
          constBits4<=constBits;
597
          stginhibit[4]<=0;
598
          IP5<=IP4;
599
          multiCycleStall[4]<=multiCycleStall[3];
600
          rAfwd0<=(rA0==rFprev);
601
          rBfwd0<=(rB0==rFprev);
602
          instr4<=instr;
603
          rF<=instr[20:16];
604
          cjmpoffset<={ {14{instr[31]}}, instr[31:16],2'b0 };
605
          cjmpaddr<=IP4+cjmpoffset0;
606
          brtaken5<=brtaken4;
607
          codeMiss[4]<=codeMiss[3];
608
          aguaddr_reg<=aguaddr;
609
        end
610
      //cycle 5
611
 
612
      if (!stall && !stginhibit[4]) //remove !stall ??
613
        begin
614
          rAfwd<=rAfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //adjust for other sources of data
615
          rBfwd<=rBfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //these 2 indicate forwarding of operands from regfwd
616
          rCfwd<=(rA0==rFprevprev) && (aluwrtval || aguwrtval) && (!agustall_reg);
617
 
618
          regfwd<=aguwrtval ? readdata : opF;
619
          if (codeMiss[4])
620
            begin
621
              stginhibit<=5'b11110;
622
              codeMiss<=0;
623
              IP<=IP5;
624
              ccInsertInProgress_tsk<=1;
625
              ccInsertRamReq_tsk<=1;
626
            end
627
          else if ((agureaden_reg || aguwriteen_reg) && !dcHit && !agustall_reg)
628
            begin
629
              stginhibit<=5'b11110;
630
              codeMiss<=0;
631
              IP<=IP5;
632
              dcInsertInProgress_tsk<=1;
633
              dcInsertRamReq_tsk<=1;
634
              dcReadAddr<=readaddr_reg;
635
            end
636
          else if ((((alucjmpinstr && alucjmp) || uJmpInstr) ^ brtaken5) || brpred_addrMismatch)
637
            begin
638
              stginhibit<=5'b11110;
639
              codeMiss<=0;
640
              IP<=(alucjmp || uJmpInstr) ? (alucjmpinstr ? (IP5+cjmpoffset) : (opA+constBits4) ): IP5+4;
641
            end
642
          else if (agustall_reg)
643
            begin
644
              stginhibit<=5'b11110;
645
              codeMiss<=0;
646
              IP<=IP5;
647
            end
648
          else if (ioInstrDoStall)
649
            begin
650
              stginhibit<=5'b11110;
651
              codeMiss<=0;
652
              IP<=IP5;
653
              multiCycleStall[0]<=1;
654
            end
655
        end
656
      else
657
        begin
658
          rAfwd<=0;
659
          rBfwd<=0;
660
          rCfwd<=0;
661
        end
662
      //
663
    end
664
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.