OpenCores
URL https://opencores.org/ocsvn/suslik/suslik/trunk

Subversion Repositories suslik

[/] [suslik/] [trunk/] [rtl/] [cpu.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 gorand2
 
2 8 gorand2
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec);
3 2 gorand2
 
4
  input [31:0] instr, val1, val2;
5
  output [31:0] valres;
6
  output wire wrtval,cjmpinstr;
7
  output cjmp;
8
  input [31:0] const1;
9
  input [31:0] retaddr;
10 8 gorand2
  output wrspec;
11
 
12 2 gorand2
  wire [5:0] code;
13
  wire [31:0] valcmp;
14
  wire CF,NF,VF,ZF;
15 8 gorand2
 
16 2 gorand2
  /*
17
    wrtval=1 if valres needs to be stored in register.
18
    cjmpinstr=1 if compare and jump instruction
19
    cjmp=1 if jump taken 0 otherwise (only valid if cjmpinstr=1)
20
  */
21
 
22
  //assign const1={{16{instr[31]}},instr[31:21],instr[15:11]};
23
  assign code=instr[5:0];
24
 
25
  assign valres=(code==0) ? {const1[15:0],val1[15:0]}    : 32'bz;
26
  assign valres=(code==1) ? const1        : 32'bz;
27
  assign valres=(code==2) ? val1 & val2            : 32'bz;
28
  assign valres=(code==3) ? val1 & const1 : 32'bz;
29
  assign valres=(code==4) ? val1 | val2            : 32'bz;
30
  assign valres=(code==5) ? val1 | const1 : 32'bz;
31
  assign valres=(code==6) ? val1 ^ val2            : 32'bz;
32
  assign valres=(code==7) ? val1 ^ const1 : 32'bz;
33
  assign valres=(code==8) ? val1 + val2            : 32'bz;
34
  assign valres=(code==9) ? val1 + const1 : 32'bz;
35
  assign valres=(code==10)? val1 - val2            : 32'bz;
36
  assign valres=(code==11)? val1 - const1 : 32'bz;
37 8 gorand2
  assign valres=wrspec ? val1 : 32'bz;
38 2 gorand2
  assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
39
  assign valres=(code==46) ? retaddr : 32'bz;
40
  assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
41
  assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
42
  assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
43
  assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
44
  assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
45
  assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
46
 
47 8 gorand2
  assign valres=wrtval | wrspec ? 32'bz : 32'b0;
48 2 gorand2
 
49
  assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46));
50 8 gorand2
  assign wrspec=(code==12) && (instr[15:6]=10'd1);
51 2 gorand2
 
52
  //flags for compare &jump
53
  assign {CF,valcmp}=val1 - val2;
54
  assign NF=valcmp[31];
55
  assign ZF=(val1==val2);
56
  assign VF=(val1[31] & !val2[31] & !valcmp[31]) | (!val1[31] & val2[31] & valcmp[31]);
57
 
58
  assign cjmpinstr=((code>=32)&&(code<=45));
59
 
60
  assign cjmp= (code==32) ? (CF)              : 1'bz;
61
  assign cjmp= (code==33) ? (!CF)             : 1'bz;
62
  assign cjmp= (code==34) ? (ZF)              : 1'bz;
63
  assign cjmp= (code==35) ? (!ZF)             : 1'bz;
64
  assign cjmp= (code==36) ? (CF ^ ZF)         : 1'bz;
65
  assign cjmp= (code==37) ? !(CF ^ ZF)        : 1'bz;
66
  assign cjmp= (code==38) ? (NF)              : 1'bz;
67
  assign cjmp= (code==39) ? !(NF)             : 1'bz;
68
  assign cjmp= (code==40) ? (VF ^ NF)         : 1'bz;
69
  assign cjmp= (code==41) ? !(VF ^ NF)        : 1'bz;
70
  assign cjmp= (code==42) ? ((VF ^ NF) | ZF)  : 1'bz;
71
  assign cjmp= (code==43) ? !((VF ^ NF) | ZF) : 1'bz;
72
  assign cjmp= (code==44) ? (VF)              : 1'bz;
73
  assign cjmp= (code==45) ? (!VF)             : 1'bz;
74
 
75
  assign cjmp= cjmpinstr ? 1'bz : 1'b0;
76
 
77
endmodule
78
 
79
module subagu(input clk, input stall,input [4:0] stginhibit,input [31:0] baseOP,input [31:0] instr0,input [31:0] instr, input [31:0] instrprev,output wire [31:0] addr,output wire aguwrtval,output wire delayedstall, output reg [1:0] readsz, output wire readen,output wire writeen, input [31:0] offset);
80
  wire [4:0] instr_rA,instrprev_rF;
81
  wire writeinstrprev;
82
  wire [5:0] instrprev_code,instr_code,instr0_code;
83
  wire instr0_load,instr0_store,instr_load,instr_store;
84
  reg aguwrtval_reg;
85
  reg delayedstall_reg=0;
86
  //reg readen_reg;
87
  //wire [18:0] shortaddr;
88
 
89
  assign instr_rA=instr[10:6];
90
  assign instrprev_rF=instrprev[20:16];
91
  assign instrprev_code=instrprev[5:0];
92
  assign instr_code=instr[5:0];
93
  assign instr0_code=instr0[5:0];
94
 
95
  assign writereginstrprev=((instrprev_code<=11) || (instrprev_code==13) ||
96
    ((instrprev_code >= 56) && (instrprev_code <=58))) && !stginhibit[4] && !stall; //remove !stall ??
97
  assign delayedstall=writereginstrprev && (instr_load || instr_store) && ( instr_rA==instrprev_rF ) && (!stginhibit[3]); //add constant add stalless support
98
 
99
  assign instr_load=(instr_code >= 56) && (instr_code <=58);
100
  assign instr_store=(instr_code >= 60) && (instr_code <=62);
101
  assign instr0_load=(instr0_code >= 56) && (instr0_code <=58);
102
  assign instr0_store=(instr0_code >= 60) && (instr0_code <=62);
103
 
104
  assign addr=baseOP + offset;
105
  //assign shortaddr=baseOP[18:0] + offset[18:0];
106
 
107
  assign readen=instr_load && !stall && !stginhibit[3];
108
  assign writeen=instr_store && !stall && !stginhibit[3] && !delayedstall_reg;
109
  assign aguwrtval=!stall && !stginhibit[4] && aguwrtval_reg;
110
 
111
  always @(posedge clk)
112
    begin
113
      if (!stall && !stginhibit[3]) aguwrtval_reg<=instr_load;
114
      ///*if (!stall && !stginhibit[2]) */readen_reg<=instr0_load;
115
      if (!stall && !stginhibit[2])
116
        case (instr0_code)
117
          56: readsz<=2;
118
          57: readsz<=1;
119
          58: readsz<=0;
120
          60: readsz<=2;
121
          61: readsz<=1;
122
          62: readsz<=0;
123
          default: readsz<=0;
124
        endcase
125
      delayedstall_reg<=delayedstall;
126
    end
127
 
128
endmodule
129
 
130
 
131
module regfileint0(clk,we,rA,rB,rC,rF,dataA,dataB,dataC,dataF);
132
  input [4:0] rA,rB,rC,rF;
133
  output wire [31:0] dataA,dataB,dataC;
134
  input [31:0] dataF;
135
  input clk,we;
136
  reg [31:0] regs [31:0];
137
 
138
  regram ram0(clk,we,rA,rF,dataA,dataF);
139
  regram ram1(clk,we,rB,rF,dataB,dataF);
140
  regram ram2(clk,we,rC,rF,dataC,dataF);
141
 
142
endmodule
143
 
144
module regram(input clk,input we,input [4:0] rA, input [4:0] rF, output reg [31:0] dataA, input [31:0] dataF);
145
  reg [31:0] regs[31:0];
146
  always @(posedge clk)
147
    begin
148
      dataA<=regs[rA];
149
      if (we) regs[rF]<=dataF;
150
    end
151
endmodule
152
 
153
module ioinstr(input clk,input stall, input [4:0] stginhibit,input [31:0] instr,input [31:0] val1,input [31:0] val2, output [31:0] valres, input multiCycleStall,
154
               output wire wrtVal, output wire doStall, output wire keepStalling,
155
               output wire [31:0] ioBusAddr,output reg [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
156
               output wire ioBusWr,output wire ioBusRd);
157
 
158
wire [5:0] code;
159
wire [5:0] auxCode;
160
reg keepStalling_reg=0;
161
reg [31:0] inputValue;
162
assign code=instr[5:0];
163
assign auxCode=instr[26:21];
164
assign doStall=(code==31) && !multiCycleStall && !stall && !stginhibit[4];
165
assign wrtVal=multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2)) && !stall && !stginhibit[4];
166
assign ioBusAddr=val1;
167
assign ioBusOut=val2;
168
 
169
assign ioBusOut=val2;
170
assign ioBusAddr=val1;
171
assign ioBusWr=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==4) || (auxCode==5) || (auxCode==6));
172
assign ioBusRd=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2));
173
assign valres=inputValue;
174
 
175
assign keepStalling=keepStalling_reg;
176
 
177
always @(auxCode)
178
  begin
179
    case(auxCode)
180
      0,4: ioBusSize=0;
181
      1,5: ioBusSize=1;
182
      2,6: ioBusSize=2;
183
      default: ioBusSize=0;
184
    endcase
185
  end
186
 
187
always @(posedge clk)
188
  begin
189
    if (!stall && !stginhibit[4] && (code==31) && !multiCycleStall)
190
      begin
191
        keepStalling_reg<=1;
192
      end
193
    if (ioBusRdy)
194
      begin
195
        keepStalling_reg<=0;
196
      end
197
    if (ioBusRdy)
198
      begin
199
        inputValue<=ioBusIn;
200
      end
201
  end
202
 
203
endmodule
204
 
205
module brpred(input clk,input stall, input [4:0] stginhibit,input [31:0] fetchaddr, output wire hit, output wire [31:0] branchinstr,
206
              output wire [31:0] nextaddr,output wire branchtaken,
207
              input [31:0] insertaddr, input [31:0] insertinstr,input [31:0] inserttargetnext,input inserttaken,input jumpinstr,output wire addrMismatch);
208
  wire wen;
209
  wire [5:0] ramAddrB;
210
  wire [96:0] ramDataA;
211
  wire [96:0] ramDataB;
212
  wire [96:0] dataA;
213
  reg [31:0] fetchaddr_reg=0;
214
  reg branchtaken3;
215
  reg branchtaken4;
216
  reg branchtaken5;
217
  reg wen_reg=0;
218
  reg fwd;
219
  reg [96:0] fwdData;
220
  reg init=1;
221
  reg [5:0] initcount=63;
222
 
223
  reg [31:0] nextaddr3;
224
  reg [31:0] nextaddr4;
225
  reg [31:0] nextaddr5;
226
 
227
  brpred_ram ram0(clk,fetchaddr[7:2],ramAddrB,wen, ramDataA, ramDataB);
228
 
229
  assign dataA=fwd ? fwdData : ramDataA;
230
 
231
  assign hit=(dataA[63:32]==fetchaddr_reg);
232
  assign branchinstr=dataA[31:0];
233
  assign branchtaken=dataA[96];
234
  assign nextaddr=dataA[95:64];
235
 
236
  assign wen=((!stall && !stginhibit[4]) && (branchtaken5 ^ inserttaken) && jumpinstr) | init; //only write on failed prediction
237
  assign ramDataB=(!init) ? {inserttaken,inserttargetnext,insertaddr,insertinstr} : {1'b0,32'b0,32'b11,32'b0};
238
  assign ramAddrB= init ? initcount : insertaddr[7:2];
239
 
240
  assign addrMismatch=jumpinstr && (inserttargetnext != nextaddr5) && branchtaken5;
241
 
242
  always @(posedge clk)
243
    begin
244
      wen_reg<=wen;
245
      fwd<=wen && (ramAddrB == fetchaddr[7:2]);
246
      fwdData<=ramDataB;
247
 
248
      if (init)
249
        begin
250
          initcount<=initcount-1;
251
          if (initcount==0) init<=0;
252
        end
253
 
254
      if (!stall)
255
        begin
256
          fetchaddr_reg<=fetchaddr;
257
        end
258
      if (!stall && !stginhibit[1])
259
        begin
260
          branchtaken3<=hit && branchtaken;
261
          nextaddr3<=nextaddr;
262
        end
263
      if (!stall && !stginhibit[2])
264
        begin
265
          branchtaken4<=branchtaken3;
266
          nextaddr4<=nextaddr3;
267
        end
268
      if (!stall && !stginhibit[3])
269
        begin
270
          branchtaken5<=branchtaken4;
271
          nextaddr5<=nextaddr4;
272
        end
273
      if (!stall && !stginhibit[4])
274
        begin
275
        end
276
    end
277
endmodule
278
 
279
module brpred_ram(input clk, input [5:0] addrA, input [5:0] addrB, input wen, output reg [96:0] dataA, input [96:0] dataB);
280
  reg [96:0] ram[63:0];
281
  always @(posedge clk)
282
    begin
283
      dataA<=ram[addrA];
284
      if (wen) ram[addrB]<=dataB;
285
    end
286
endmodule
287
 
288
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
289
              input [511:0] busInput,output wire [511:0] busOutput,
290
              output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
291 8 gorand2
              output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy, input [15:0] irq);
292 2 gorand2
  wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
293
  reg [31:0] readaddr_reg;
294
  reg [4:0] stginhibit=5'b11110;
295
  reg [4:0] stginhibit_wrt;
296
  reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
297
  reg stall0=0;
298
  wor stall;
299
  wire [4:0] rA0,rB0,rC,rF0,rFprev,rFprevprev;
300
  //reg [31:0] cjmpoff;
301
  reg [4:0] rA,rB,rF,rAprev,rBprev;
302
  wire intregwe;
303
  wire [31:0] intregdataF;
304
  wire [31:0] intregdataA,intregdataB,intregdataC;
305
  wire [31:0] opA,opB,opC,opF;
306
  reg rAfwd,rBfwd,rCfwd,rAfwd0,rBfwd0,rCfwd0;
307
  reg cycle1prev=0;
308
  reg [31:0] instr0=0;
309
  //reg [31:0] reg_instr0;
310
  wire aluwrtval,alucjmpinstr,alucjmp;
311
  //reg regfwrt=0;
312
  reg [31:0] regfwd;
313
  wire [31:0] aguaddr;
314
  wire agustall,aguwrtval;
315
  wire [1:0] agureadsz;
316
  wire agureaden;
317
  wire aguwriteen;
318
  reg agureaden_reg;
319
  reg aguwriteen_reg;
320
  reg agustall_reg=0;
321
  //aguwrtval ignores exceptions for now
322
  reg [31:0] cjmpoffset;
323
  reg [31:0] cjmpoffset0;
324
  reg [31:0] cjmpaddr;
325
  wire brpred_hit;
326
  wire [31:0] brpred_instr;
327
  wire [31:0] brpred_nextaddr;
328
  wire brpred_taken;
329
  wire [31:0] brpred_instertaddr;
330
  wire [31:0] brpred_instertinstr;
331
  wire [31:0] brpred_insertnextaddr;
332
  wire brpred_inserttaken;
333
  wire brpred_jumpinstr;
334
  wire brpred_addrMismatch;
335
 
336
  reg brtaken3,brtaken4,brtaken5;
337
 
338
  reg init=1;
339
  reg ccInit=1;
340
  reg dcInit=1;
341
  reg [6:0] initcount=66;
342
  reg [5:0] ccInitCount=63;
343
  reg [5:0] dcInitCount=63;
344
  reg [4:0] codeMiss=0;
345
  wire [31:0] ccFetchAddr;
346
  //wire [511:0] cacheLineInput;
347
  wire ccHit,ccReadEn,ccInsert;
348
  reg ccInsertInProgress_tsk=0;
349
  reg ccInsertRamReq_tsk=0;
350
  reg ccInsertInsert_tsk=0;
351
  reg ccInsertWait1_tsk=0;
352
  reg ccInsertWait2_tsk=0;
353
 
354
  wire [31:0] dcAddr;
355
  wire [511:0] dcDataA;
356
  wire [511:0] dcDataWriteBack;
357
  reg  [511:0] dcDataWriteBack_reg;
358
  wire dcHit;
359
  wire dcReadEn,dcWriteEn,dcInsert,dcInitEntry;
360
  reg dcInsertInProgress_tsk=0;
361
  reg dcInsertRamReq_tsk=0;
362
  reg dcInsertInsert_tsk=0;
363
  reg dcInsertCheckDirty_tsk=0;
364
  reg dcInsertWriteBack_tsk=0;
365
  reg [31:0] dcReadAddr;
366
  reg [31:0] dcOldAddr_reg;
367
  wire [31:0] dcOldAddr;
368
 
369
  reg [31:0] constBits; // contains the constant bits
370
  reg [31:0] constBits4;
371
  reg prevUpperBits=0; //bit 0 set => constBits countains the upper constant bits of the next instruction
372
 
373
  wire [31:0] retAddr;
374
  wire uJmpInstr;
375
  reg [31:0] aguaddr_reg;
376
 
377
  reg [4:0] multiCycleStall=0;
378
 
379
  wire [31:0] ioInstrResult;
380
  wire wasGlobalStall=multiCycleStall[4];
381
  wire ioInstrWrtVal;
382
  wire ioInstrDoStall;
383
  wire ioInstrKeepStalling;
384 8 gorand2
 
385
  reg [15:0] irq_bits=16'b0;
386
  reg [31:0] irq_handler=32'hffff_fff0;
387 2 gorand2
 
388 8 gorand2
  wire wrspec;
389 2 gorand2
 
390
  //dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
391
  datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
392
  regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
393 8 gorand2
  aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec);
394 2 gorand2
  ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
395
                   ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
396
  subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
397
  brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
398
                 brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
399
  codecache codecache0(clk,ccFetchAddr,fetchdata,busInput,ccHit,ccReadEn,ccInsert,ccInit);
400
 
401
  assign dummy=stginhibit[4:1];
402
  assign fetchaddr=!(!stall && !stginhibit[1] && brpred_hit&&brpred_taken) ? IP : brpred_nextaddr;
403
  assign stall=init || ccInsertInProgress_tsk || dcInsertInProgress_tsk || ioInstrKeepStalling;
404
 
405
  assign readdata=dcDataA[31:0];
406
  assign dcReadEn=agureaden && !agustall;
407
  assign dcWriteEn=aguwriteen && !agustall;
408
  assign dcInsert=dcInsertInsert_tsk && busDataReady;
409
  assign dcInitEntry=dcInit;
410
 
411
  assign dcAddr=dcInit ? { 20'b0,dcInitCount,6'b0} : 32'bz;
412
  assign dcAddr=(dcReadEn || dcWriteEn) ? readaddr : 32'bz;
413
  assign dcAddr=dcInsert ? dcReadAddr : 32'bz;
414
  assign dcAddr=(!dcInit && !dcReadEn && !dcWriteEn && !dcInsert) ? 32'b0 : 32'bz;
415
 
416
  assign ccFetchAddr=ccInit ? { 20'b0,ccInitCount,6'b0} : 32'bz;
417
  assign ccFetchAddr=(!ccInit && !ccInsertInsert_tsk)? fetchaddr : 32'bz; //that should change to accomodate cache line insert
418
  assign ccFetchAddr=ccInsertInsert_tsk ? IP & 32'hffff_ffc0 : 32'bz;
419
 
420
  assign ccReadEn=!stall && !codeMiss[1] && !ccInit && !init;
421
  assign ccInsert=ccInsertInsert_tsk && busDataReady;
422
 
423
  assign busAddr=ccInsertRamReq_tsk ? IP & 32'hffff_ffc0 :32'bz;
424
  assign busAddr=dcInsertRamReq_tsk ? dcReadAddr & 32'hffff_ffc0: 32'bz;
425
  assign busAddr=dcInsertWriteBack_tsk ? dcOldAddr_reg : 32'bz;
426
  assign busAddr=(!ccInsertRamReq_tsk && !dcInsertRamReq_tsk && !dcInsertWriteBack_tsk) ? 32'b0 : 32'bz;
427
 
428
  assign busRead=(ccInsertRamReq_tsk || dcInsertRamReq_tsk) && busEnRead;
429
  assign busWrite=dcInsertWriteBack_tsk && busEnWrite;
430
 
431
  assign dcDataWriteBack=dcDataA;
432
  assign busOutput=dcDataWriteBack_reg;
433
 
434
  assign rA0=instr0[10:6];
435
  assign rB0=instr0[15:11];
436
  assign rF0=instr0[20:16];
437
  assign rC=instr0[10:6];
438
 
439
  assign intregwe=!stall && !stginhibit[4] && (aluwrtval || aguwrtval) && (!agustall_reg) && !((agureaden_reg || aguwriteen_reg) && !dcHit); // adjust for other cases ie mem read-done;
440
  assign intregdataF= aguwrtval ? readdata : opF; //adjust for ie mem read-done
441
  assign opA=rAfwd ? regfwd : intregdataA;
442
  assign opB=rBfwd ? regfwd : intregdataB;
443
  assign opC=rCfwd ? regfwd : intregdataC;
444
 
445
  //assign instr0=fetchdata; //change for branch prediction
446
 
447
  assign rFprev=instr[20:16];
448
  assign rFprevprev=instr4[20:16];
449
  //assign rAfwd=(rA==rFprev);
450
  //assign rBfwd=(rB==rFprev);
451
  //assign intregdataF=opF;
452
 
453
  assign readaddr=aguaddr;
454
 
455
  assign brpred_jumpinstr=alucjmpinstr || uJmpInstr;
456
  assign brpred_inserttaken=alucjmp || uJmpInstr;
457
  assign brpred_instertinstr=instr4;
458
  assign brpred_instertaddr=IP5;
459
  assign brpred_insertnextaddr=alucjmpinstr ? cjmpaddr : aguaddr_reg ;
460
 
461
  assign retAddr=IP5+4;
462
  assign uJmpInstr=(instr4[5:0]==46 || instr4[5:0]==47);
463
 
464
  //regfwrt<=0;
465
  always @(posedge clk)
466
    begin
467
      if (init)
468
        begin
469
          initcount<=initcount-1;
470
          if (initcount==0) init<=0;
471
        end
472
      if (ccInit)
473
        begin
474
          ccInitCount<=ccInitCount-1;
475
          if (ccInitCount==0) ccInit<=0;
476
        end
477
      if (dcInit)
478
        begin
479
          dcInitCount<=dcInitCount-1;
480
          if (dcInitCount==0) dcInit<=0;
481
        end
482
      if (ccInsertRamReq_tsk && busEnRead)
483
        begin
484
          ccInsertRamReq_tsk<=0;
485
          ccInsertInsert_tsk<=1;
486
        end
487
      if (ccInsertInsert_tsk && busDataReady)
488
        begin
489
          ccInsertInsert_tsk<=0;
490
          ccInsertWait1_tsk<=1;
491
        end
492
      if (ccInsertWait1_tsk)
493
        begin
494
          ccInsertWait1_tsk<=0;
495
          ccInsertWait2_tsk<=1;
496
        end
497
      if (ccInsertWait2_tsk)
498
        begin
499
          ccInsertWait2_tsk<=0;
500
          ccInsertInProgress_tsk<=0;
501
        end
502
      if (dcInsertRamReq_tsk && busEnRead)
503
        begin
504
          dcInsertRamReq_tsk<=0;
505
          dcInsertInsert_tsk<=1;
506
        end
507
      if (dcInsertInsert_tsk && busDataReady)
508
        begin
509
          dcInsertInsert_tsk<=0;
510
          dcInsertCheckDirty_tsk<=1;
511
        end
512
      if (dcInsertCheckDirty_tsk)
513
        begin
514
          dcInsertCheckDirty_tsk<=0;
515
          if (dcHit)
516
            begin
517
              dcInsertWriteBack_tsk<=1;
518
              dcOldAddr_reg<=dcOldAddr;
519
              dcDataWriteBack_reg<=dcDataWriteBack;
520
            end
521
          else
522
            begin
523
              dcInsertInProgress_tsk<=0;
524
            end
525
        end
526
      if (dcInsertWriteBack_tsk && busEnWrite)
527
        begin
528
          dcInsertWriteBack_tsk<=0;
529
          dcInsertInProgress_tsk<=0;
530
        end
531
      //stginhibit_wrt=stginhibit;
532
      if (stginhibit[1]) stginhibit_wrt[2]=1;
533
      if (stginhibit[2]) stginhibit_wrt[3]=1;
534
      if (stginhibit[3]) stginhibit_wrt[4]=1;
535
      agustall_reg<=agustall;
536
      agureaden_reg<=agureaden;
537
      aguwriteen_reg<=aguwriteen;
538
      readaddr_reg<=readaddr;
539
      //cycle 1
540
      if (!stall)
541
        begin
542 8 gorand2
          stginhibit[1]<=0;
543
          cycle1prev<=1;
544
          IP<=fetchaddr+4;
545
          IP2<=fetchaddr;
546
          multiCycleStall[1]<=multiCycleStall[0];
547
          multiCycleStall[0]<=0;
548
          if (irq)
549
            begin
550
              stginhibit<=5'b11110;
551
              codeMiss<=0;
552
              IP<=irq_handler;
553
              irq_bits<=irq;
554
            end
555 2 gorand2
        end
556
      else  cycle1prev<=0;
557
 
558
      //cycle 2
559
      if (!stall && !stginhibit[1])
560
        begin
561
          stginhibit[2]<=0;
562
          IP3<=IP2;
563
          multiCycleStall[2]<=multiCycleStall[1];
564
          if (!(brpred_hit&&brpred_taken)) instr0<=ccHit ? fetchdata : 32'b01100;
565
            else instr0<=brpred_instr;
566
          brtaken3<=(brpred_hit&&brpred_taken);
567
          if (!ccHit)
568
            begin
569
              codeMiss[1]<=1;
570
              codeMiss[2]<=1;
571
            end
572
          if (codeMiss[1]) codeMiss[2]<=1;
573
 
574
        end
575
      //cycle 3
576
      if (!stall && !stginhibit[2])
577
        begin
578
          instr<=instr0;
579
          //reg_instr0<=fetchdata;
580
          stginhibit[3]<=0;
581
          multiCycleStall[3]<=multiCycleStall[2];
582
          IP4<=IP3;
583
          rA<=instr0[10:6];
584
          rB<=instr0[15:11];
585
          brtaken4<=brtaken3;
586
          codeMiss[3]<=codeMiss[2];
587
          cjmpoffset0<={ {14{instr0[31]}}, instr0[31:16],2'b0 };
588
          if (instr0[5:0]==30) //upper bits instr
589
            begin
590
              prevUpperBits<=1;
591
              constBits[31:16]<=instr0[31:16];
592
            end
593
          else
594
            begin
595
              prevUpperBits<=0;
596
            end
597
          if (instr0[5:0]==60 || instr0[5:0]==61 || instr0[5:0]==62) //store instr
598
            begin
599
              constBits[15:0]<=instr0[31:16];
600
            end
601
          else  //non-store instr
602
            begin
603
              constBits[15:0]<={instr0[31:21],instr0[15:11]};
604
            end
605
          if (!prevUpperBits) constBits[31:16]<={16{instr0[31]}};
606
        end
607
      //cycle 4
608
      if (!stall && !stginhibit[3])
609
        begin
610
          constBits4<=constBits;
611
          stginhibit[4]<=0;
612
          IP5<=IP4;
613
          multiCycleStall[4]<=multiCycleStall[3];
614
          rAfwd0<=(rA0==rFprev);
615
          rBfwd0<=(rB0==rFprev);
616
          instr4<=instr;
617
          rF<=instr[20:16];
618
          cjmpoffset<={ {14{instr[31]}}, instr[31:16],2'b0 };
619
          cjmpaddr<=IP4+cjmpoffset0;
620
          brtaken5<=brtaken4;
621
          codeMiss[4]<=codeMiss[3];
622
          aguaddr_reg<=aguaddr;
623
        end
624
      //cycle 5
625
 
626
      if (!stall && !stginhibit[4]) //remove !stall ??
627
        begin
628
          rAfwd<=rAfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //adjust for other sources of data
629
          rBfwd<=rBfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //these 2 indicate forwarding of operands from regfwd
630
          rCfwd<=(rA0==rFprevprev) && (aluwrtval || aguwrtval) && (!agustall_reg);
631
 
632
          regfwd<=aguwrtval ? readdata : opF;
633
          if (codeMiss[4])
634
            begin
635
              stginhibit<=5'b11110;
636
              codeMiss<=0;
637
              IP<=IP5;
638
              ccInsertInProgress_tsk<=1;
639
              ccInsertRamReq_tsk<=1;
640
            end
641
          else if ((agureaden_reg || aguwriteen_reg) && !dcHit && !agustall_reg)
642
            begin
643
              stginhibit<=5'b11110;
644
              codeMiss<=0;
645
              IP<=IP5;
646
              dcInsertInProgress_tsk<=1;
647
              dcInsertRamReq_tsk<=1;
648
              dcReadAddr<=readaddr_reg;
649
            end
650
          else if ((((alucjmpinstr && alucjmp) || uJmpInstr) ^ brtaken5) || brpred_addrMismatch)
651
            begin
652
              stginhibit<=5'b11110;
653
              codeMiss<=0;
654
              IP<=(alucjmp || uJmpInstr) ? (alucjmpinstr ? (IP5+cjmpoffset) : (opA+constBits4) ): IP5+4;
655
            end
656
          else if (agustall_reg)
657
            begin
658
              stginhibit<=5'b11110;
659
              codeMiss<=0;
660
              IP<=IP5;
661
            end
662
          else if (ioInstrDoStall)
663
            begin
664
              stginhibit<=5'b11110;
665
              codeMiss<=0;
666
              IP<=IP5;
667
              multiCycleStall[0]<=1;
668
            end
669 8 gorand2
          else if (wrspec)
670
            begin
671
              case (instr4[31:16])
672
                16'd0: irq_handler<=opF;
673
              endcase
674
            end
675 2 gorand2
        end
676
      else
677
        begin
678
          rAfwd<=0;
679
          rBfwd<=0;
680
          rCfwd<=0;
681
        end
682
      //
683
    end
684
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.