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[/] [suslik/] [trunk/] [rtl/] [cpu.v] - Blame information for rev 9

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1 2 gorand2
 
2 9 gorand2
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec,irq_bits);
3 2 gorand2
 
4
  input [31:0] instr, val1, val2;
5
  output [31:0] valres;
6
  output wire wrtval,cjmpinstr;
7
  output cjmp;
8
  input [31:0] const1;
9
  input [31:0] retaddr;
10 8 gorand2
  output wrspec;
11 9 gorand2
  input [15:0] irq_bits;
12 8 gorand2
 
13 2 gorand2
  wire [5:0] code;
14
  wire [31:0] valcmp;
15
  wire CF,NF,VF,ZF;
16 8 gorand2
 
17 2 gorand2
  /*
18
    wrtval=1 if valres needs to be stored in register.
19
    cjmpinstr=1 if compare and jump instruction
20
    cjmp=1 if jump taken 0 otherwise (only valid if cjmpinstr=1)
21
  */
22
 
23
  //assign const1={{16{instr[31]}},instr[31:21],instr[15:11]};
24
  assign code=instr[5:0];
25
 
26
  assign valres=(code==0) ? {const1[15:0],val1[15:0]}    : 32'bz;
27
  assign valres=(code==1) ? const1        : 32'bz;
28
  assign valres=(code==2) ? val1 & val2            : 32'bz;
29
  assign valres=(code==3) ? val1 & const1 : 32'bz;
30
  assign valres=(code==4) ? val1 | val2            : 32'bz;
31
  assign valres=(code==5) ? val1 | const1 : 32'bz;
32
  assign valres=(code==6) ? val1 ^ val2            : 32'bz;
33
  assign valres=(code==7) ? val1 ^ const1 : 32'bz;
34
  assign valres=(code==8) ? val1 + val2            : 32'bz;
35
  assign valres=(code==9) ? val1 + const1 : 32'bz;
36
  assign valres=(code==10)? val1 - val2            : 32'bz;
37
  assign valres=(code==11)? val1 - const1 : 32'bz;
38 8 gorand2
  assign valres=wrspec ? val1 : 32'bz;
39 9 gorand2
  assign valres=(code==12 && instr[15:11]==5'd2 && instr[31:24]=8'hff) ? irq_bits : 32'bz;
40 2 gorand2
  assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz;
41
  assign valres=(code==46) ? retaddr : 32'bz;
42
  assign valres=(code==14)? val1 << val2[5:0] : 32'bz;
43
  assign valres=(code==15)? val1 << const1[5:0] : 32'bz;
44
  assign valres=(code==16)? val1 >> val2[5:0] : 32'bz;
45
  assign valres=(code==17)? val1 >> const1[5:0] : 32'bz;
46
  assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz;
47
  assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz;
48
 
49 8 gorand2
  assign valres=wrtval | wrspec ? 32'bz : 32'b0;
50 2 gorand2
 
51 9 gorand2
  assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46)) || (code==12 && instr[15:11]==5'd2 && instr[31:24]=8'hff);
52
  assign wrspec=(code==12) && (instr[15:11]=5'd1);
53 2 gorand2
 
54
  //flags for compare &jump
55
  assign {CF,valcmp}=val1 - val2;
56
  assign NF=valcmp[31];
57
  assign ZF=(val1==val2);
58
  assign VF=(val1[31] & !val2[31] & !valcmp[31]) | (!val1[31] & val2[31] & valcmp[31]);
59
 
60
  assign cjmpinstr=((code>=32)&&(code<=45));
61
 
62
  assign cjmp= (code==32) ? (CF)              : 1'bz;
63
  assign cjmp= (code==33) ? (!CF)             : 1'bz;
64
  assign cjmp= (code==34) ? (ZF)              : 1'bz;
65
  assign cjmp= (code==35) ? (!ZF)             : 1'bz;
66
  assign cjmp= (code==36) ? (CF ^ ZF)         : 1'bz;
67
  assign cjmp= (code==37) ? !(CF ^ ZF)        : 1'bz;
68
  assign cjmp= (code==38) ? (NF)              : 1'bz;
69
  assign cjmp= (code==39) ? !(NF)             : 1'bz;
70
  assign cjmp= (code==40) ? (VF ^ NF)         : 1'bz;
71
  assign cjmp= (code==41) ? !(VF ^ NF)        : 1'bz;
72
  assign cjmp= (code==42) ? ((VF ^ NF) | ZF)  : 1'bz;
73
  assign cjmp= (code==43) ? !((VF ^ NF) | ZF) : 1'bz;
74
  assign cjmp= (code==44) ? (VF)              : 1'bz;
75
  assign cjmp= (code==45) ? (!VF)             : 1'bz;
76
 
77
  assign cjmp= cjmpinstr ? 1'bz : 1'b0;
78
 
79
endmodule
80
 
81
module subagu(input clk, input stall,input [4:0] stginhibit,input [31:0] baseOP,input [31:0] instr0,input [31:0] instr, input [31:0] instrprev,output wire [31:0] addr,output wire aguwrtval,output wire delayedstall, output reg [1:0] readsz, output wire readen,output wire writeen, input [31:0] offset);
82
  wire [4:0] instr_rA,instrprev_rF;
83
  wire writeinstrprev;
84
  wire [5:0] instrprev_code,instr_code,instr0_code;
85
  wire instr0_load,instr0_store,instr_load,instr_store;
86
  reg aguwrtval_reg;
87
  reg delayedstall_reg=0;
88
  //reg readen_reg;
89
  //wire [18:0] shortaddr;
90
 
91
  assign instr_rA=instr[10:6];
92
  assign instrprev_rF=instrprev[20:16];
93
  assign instrprev_code=instrprev[5:0];
94
  assign instr_code=instr[5:0];
95
  assign instr0_code=instr0[5:0];
96
 
97
  assign writereginstrprev=((instrprev_code<=11) || (instrprev_code==13) ||
98
    ((instrprev_code >= 56) && (instrprev_code <=58))) && !stginhibit[4] && !stall; //remove !stall ??
99
  assign delayedstall=writereginstrprev && (instr_load || instr_store) && ( instr_rA==instrprev_rF ) && (!stginhibit[3]); //add constant add stalless support
100
 
101
  assign instr_load=(instr_code >= 56) && (instr_code <=58);
102
  assign instr_store=(instr_code >= 60) && (instr_code <=62);
103
  assign instr0_load=(instr0_code >= 56) && (instr0_code <=58);
104
  assign instr0_store=(instr0_code >= 60) && (instr0_code <=62);
105
 
106
  assign addr=baseOP + offset;
107
  //assign shortaddr=baseOP[18:0] + offset[18:0];
108
 
109
  assign readen=instr_load && !stall && !stginhibit[3];
110
  assign writeen=instr_store && !stall && !stginhibit[3] && !delayedstall_reg;
111
  assign aguwrtval=!stall && !stginhibit[4] && aguwrtval_reg;
112
 
113
  always @(posedge clk)
114
    begin
115
      if (!stall && !stginhibit[3]) aguwrtval_reg<=instr_load;
116
      ///*if (!stall && !stginhibit[2]) */readen_reg<=instr0_load;
117
      if (!stall && !stginhibit[2])
118
        case (instr0_code)
119
          56: readsz<=2;
120
          57: readsz<=1;
121
          58: readsz<=0;
122
          60: readsz<=2;
123
          61: readsz<=1;
124
          62: readsz<=0;
125
          default: readsz<=0;
126
        endcase
127
      delayedstall_reg<=delayedstall;
128
    end
129
 
130
endmodule
131
 
132
 
133
module regfileint0(clk,we,rA,rB,rC,rF,dataA,dataB,dataC,dataF);
134
  input [4:0] rA,rB,rC,rF;
135
  output wire [31:0] dataA,dataB,dataC;
136
  input [31:0] dataF;
137
  input clk,we;
138
  reg [31:0] regs [31:0];
139
 
140
  regram ram0(clk,we,rA,rF,dataA,dataF);
141
  regram ram1(clk,we,rB,rF,dataB,dataF);
142
  regram ram2(clk,we,rC,rF,dataC,dataF);
143
 
144
endmodule
145
 
146
module regram(input clk,input we,input [4:0] rA, input [4:0] rF, output reg [31:0] dataA, input [31:0] dataF);
147
  reg [31:0] regs[31:0];
148
  always @(posedge clk)
149
    begin
150
      dataA<=regs[rA];
151
      if (we) regs[rF]<=dataF;
152
    end
153
endmodule
154
 
155
module ioinstr(input clk,input stall, input [4:0] stginhibit,input [31:0] instr,input [31:0] val1,input [31:0] val2, output [31:0] valres, input multiCycleStall,
156
               output wire wrtVal, output wire doStall, output wire keepStalling,
157
               output wire [31:0] ioBusAddr,output reg [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
158
               output wire ioBusWr,output wire ioBusRd);
159
 
160
wire [5:0] code;
161
wire [5:0] auxCode;
162
reg keepStalling_reg=0;
163
reg [31:0] inputValue;
164
assign code=instr[5:0];
165
assign auxCode=instr[26:21];
166
assign doStall=(code==31) && !multiCycleStall && !stall && !stginhibit[4];
167
assign wrtVal=multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2)) && !stall && !stginhibit[4];
168
assign ioBusAddr=val1;
169
assign ioBusOut=val2;
170
 
171
assign ioBusOut=val2;
172
assign ioBusAddr=val1;
173
assign ioBusWr=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==4) || (auxCode==5) || (auxCode==6));
174
assign ioBusRd=!stall && !stginhibit[4] && !multiCycleStall && (code==31) && ((auxCode==0) || (auxCode==1) || (auxCode==2));
175
assign valres=inputValue;
176
 
177
assign keepStalling=keepStalling_reg;
178
 
179
always @(auxCode)
180
  begin
181
    case(auxCode)
182
      0,4: ioBusSize=0;
183
      1,5: ioBusSize=1;
184
      2,6: ioBusSize=2;
185
      default: ioBusSize=0;
186
    endcase
187
  end
188
 
189
always @(posedge clk)
190
  begin
191
    if (!stall && !stginhibit[4] && (code==31) && !multiCycleStall)
192
      begin
193
        keepStalling_reg<=1;
194
      end
195
    if (ioBusRdy)
196
      begin
197
        keepStalling_reg<=0;
198
      end
199
    if (ioBusRdy)
200
      begin
201
        inputValue<=ioBusIn;
202
      end
203
  end
204
 
205
endmodule
206
 
207
module brpred(input clk,input stall, input [4:0] stginhibit,input [31:0] fetchaddr, output wire hit, output wire [31:0] branchinstr,
208
              output wire [31:0] nextaddr,output wire branchtaken,
209
              input [31:0] insertaddr, input [31:0] insertinstr,input [31:0] inserttargetnext,input inserttaken,input jumpinstr,output wire addrMismatch);
210
  wire wen;
211
  wire [5:0] ramAddrB;
212
  wire [96:0] ramDataA;
213
  wire [96:0] ramDataB;
214
  wire [96:0] dataA;
215
  reg [31:0] fetchaddr_reg=0;
216
  reg branchtaken3;
217
  reg branchtaken4;
218
  reg branchtaken5;
219
  reg wen_reg=0;
220
  reg fwd;
221
  reg [96:0] fwdData;
222
  reg init=1;
223
  reg [5:0] initcount=63;
224
 
225
  reg [31:0] nextaddr3;
226
  reg [31:0] nextaddr4;
227
  reg [31:0] nextaddr5;
228
 
229
  brpred_ram ram0(clk,fetchaddr[7:2],ramAddrB,wen, ramDataA, ramDataB);
230
 
231
  assign dataA=fwd ? fwdData : ramDataA;
232
 
233
  assign hit=(dataA[63:32]==fetchaddr_reg);
234
  assign branchinstr=dataA[31:0];
235
  assign branchtaken=dataA[96];
236
  assign nextaddr=dataA[95:64];
237
 
238
  assign wen=((!stall && !stginhibit[4]) && (branchtaken5 ^ inserttaken) && jumpinstr) | init; //only write on failed prediction
239
  assign ramDataB=(!init) ? {inserttaken,inserttargetnext,insertaddr,insertinstr} : {1'b0,32'b0,32'b11,32'b0};
240
  assign ramAddrB= init ? initcount : insertaddr[7:2];
241
 
242
  assign addrMismatch=jumpinstr && (inserttargetnext != nextaddr5) && branchtaken5;
243
 
244
  always @(posedge clk)
245
    begin
246
      wen_reg<=wen;
247
      fwd<=wen && (ramAddrB == fetchaddr[7:2]);
248
      fwdData<=ramDataB;
249
 
250
      if (init)
251
        begin
252
          initcount<=initcount-1;
253
          if (initcount==0) init<=0;
254
        end
255
 
256
      if (!stall)
257
        begin
258
          fetchaddr_reg<=fetchaddr;
259
        end
260
      if (!stall && !stginhibit[1])
261
        begin
262
          branchtaken3<=hit && branchtaken;
263
          nextaddr3<=nextaddr;
264
        end
265
      if (!stall && !stginhibit[2])
266
        begin
267
          branchtaken4<=branchtaken3;
268
          nextaddr4<=nextaddr3;
269
        end
270
      if (!stall && !stginhibit[3])
271
        begin
272
          branchtaken5<=branchtaken4;
273
          nextaddr5<=nextaddr4;
274
        end
275
      if (!stall && !stginhibit[4])
276
        begin
277
        end
278
    end
279
endmodule
280
 
281
module brpred_ram(input clk, input [5:0] addrA, input [5:0] addrB, input wen, output reg [96:0] dataA, input [96:0] dataB);
282
  reg [96:0] ram[63:0];
283
  always @(posedge clk)
284
    begin
285
      dataA<=ram[addrA];
286
      if (wen) ram[addrB]<=dataB;
287
    end
288
endmodule
289
 
290
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr,
291
              input [511:0] busInput,output wire [511:0] busOutput,
292
              output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy,
293 8 gorand2
              output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy, input [15:0] irq);
294 2 gorand2
  wire [31:0] fetchaddr,fetchdata,readaddr,readdata;
295
  reg [31:0] readaddr_reg;
296
  reg [4:0] stginhibit=5'b11110;
297
  reg [4:0] stginhibit_wrt;
298
  reg [31:0] IP=32'b0,IP2,IP3,IP4,IP5,instr=0,instr4=0;
299
  reg stall0=0;
300
  wor stall;
301
  wire [4:0] rA0,rB0,rC,rF0,rFprev,rFprevprev;
302
  //reg [31:0] cjmpoff;
303
  reg [4:0] rA,rB,rF,rAprev,rBprev;
304
  wire intregwe;
305
  wire [31:0] intregdataF;
306
  wire [31:0] intregdataA,intregdataB,intregdataC;
307
  wire [31:0] opA,opB,opC,opF;
308
  reg rAfwd,rBfwd,rCfwd,rAfwd0,rBfwd0,rCfwd0;
309
  reg cycle1prev=0;
310
  reg [31:0] instr0=0;
311
  //reg [31:0] reg_instr0;
312
  wire aluwrtval,alucjmpinstr,alucjmp;
313
  //reg regfwrt=0;
314
  reg [31:0] regfwd;
315
  wire [31:0] aguaddr;
316
  wire agustall,aguwrtval;
317
  wire [1:0] agureadsz;
318
  wire agureaden;
319
  wire aguwriteen;
320
  reg agureaden_reg;
321
  reg aguwriteen_reg;
322
  reg agustall_reg=0;
323
  //aguwrtval ignores exceptions for now
324
  reg [31:0] cjmpoffset;
325
  reg [31:0] cjmpoffset0;
326
  reg [31:0] cjmpaddr;
327
  wire brpred_hit;
328
  wire [31:0] brpred_instr;
329
  wire [31:0] brpred_nextaddr;
330
  wire brpred_taken;
331
  wire [31:0] brpred_instertaddr;
332
  wire [31:0] brpred_instertinstr;
333
  wire [31:0] brpred_insertnextaddr;
334
  wire brpred_inserttaken;
335
  wire brpred_jumpinstr;
336
  wire brpred_addrMismatch;
337
 
338
  reg brtaken3,brtaken4,brtaken5;
339
 
340
  reg init=1;
341
  reg ccInit=1;
342
  reg dcInit=1;
343
  reg [6:0] initcount=66;
344
  reg [5:0] ccInitCount=63;
345
  reg [5:0] dcInitCount=63;
346
  reg [4:0] codeMiss=0;
347
  wire [31:0] ccFetchAddr;
348
  //wire [511:0] cacheLineInput;
349
  wire ccHit,ccReadEn,ccInsert;
350
  reg ccInsertInProgress_tsk=0;
351
  reg ccInsertRamReq_tsk=0;
352
  reg ccInsertInsert_tsk=0;
353
  reg ccInsertWait1_tsk=0;
354
  reg ccInsertWait2_tsk=0;
355
 
356
  wire [31:0] dcAddr;
357
  wire [511:0] dcDataA;
358
  wire [511:0] dcDataWriteBack;
359
  reg  [511:0] dcDataWriteBack_reg;
360
  wire dcHit;
361
  wire dcReadEn,dcWriteEn,dcInsert,dcInitEntry;
362
  reg dcInsertInProgress_tsk=0;
363
  reg dcInsertRamReq_tsk=0;
364
  reg dcInsertInsert_tsk=0;
365
  reg dcInsertCheckDirty_tsk=0;
366
  reg dcInsertWriteBack_tsk=0;
367
  reg [31:0] dcReadAddr;
368
  reg [31:0] dcOldAddr_reg;
369
  wire [31:0] dcOldAddr;
370
 
371
  reg [31:0] constBits; // contains the constant bits
372
  reg [31:0] constBits4;
373
  reg prevUpperBits=0; //bit 0 set => constBits countains the upper constant bits of the next instruction
374
 
375
  wire [31:0] retAddr;
376
  wire uJmpInstr;
377
  reg [31:0] aguaddr_reg;
378
 
379
  reg [4:0] multiCycleStall=0;
380
 
381
  wire [31:0] ioInstrResult;
382
  wire wasGlobalStall=multiCycleStall[4];
383
  wire ioInstrWrtVal;
384
  wire ioInstrDoStall;
385
  wire ioInstrKeepStalling;
386 8 gorand2
 
387
  reg [15:0] irq_bits=16'b0;
388
  reg [31:0] irq_handler=32'hffff_fff0;
389 2 gorand2
 
390 8 gorand2
  wire wrspec;
391 9 gorand2
  reg [31:0] sys_flags=32'b0;
392
  reg [15:0] irq_mask;
393 2 gorand2
 
394
  //dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB);
395
  datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr);
396
  regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF);
397 9 gorand2
  aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec,irq_bits);
398 2 gorand2
  ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling,
399
                   ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd);
400
  subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits);
401
  brpred brpred0(clk,stall,stginhibit,fetchaddr,brpred_hit,brpred_instr,brpred_nextaddr,brpred_taken,
402
                 brpred_instertaddr,brpred_instertinstr,brpred_insertnextaddr,brpred_inserttaken,brpred_jumpinstr,brpred_addrMismatch);
403
  codecache codecache0(clk,ccFetchAddr,fetchdata,busInput,ccHit,ccReadEn,ccInsert,ccInit);
404
 
405
  assign dummy=stginhibit[4:1];
406
  assign fetchaddr=!(!stall && !stginhibit[1] && brpred_hit&&brpred_taken) ? IP : brpred_nextaddr;
407
  assign stall=init || ccInsertInProgress_tsk || dcInsertInProgress_tsk || ioInstrKeepStalling;
408
 
409
  assign readdata=dcDataA[31:0];
410
  assign dcReadEn=agureaden && !agustall;
411
  assign dcWriteEn=aguwriteen && !agustall;
412
  assign dcInsert=dcInsertInsert_tsk && busDataReady;
413
  assign dcInitEntry=dcInit;
414
 
415
  assign dcAddr=dcInit ? { 20'b0,dcInitCount,6'b0} : 32'bz;
416
  assign dcAddr=(dcReadEn || dcWriteEn) ? readaddr : 32'bz;
417
  assign dcAddr=dcInsert ? dcReadAddr : 32'bz;
418
  assign dcAddr=(!dcInit && !dcReadEn && !dcWriteEn && !dcInsert) ? 32'b0 : 32'bz;
419
 
420
  assign ccFetchAddr=ccInit ? { 20'b0,ccInitCount,6'b0} : 32'bz;
421
  assign ccFetchAddr=(!ccInit && !ccInsertInsert_tsk)? fetchaddr : 32'bz; //that should change to accomodate cache line insert
422
  assign ccFetchAddr=ccInsertInsert_tsk ? IP & 32'hffff_ffc0 : 32'bz;
423
 
424
  assign ccReadEn=!stall && !codeMiss[1] && !ccInit && !init;
425
  assign ccInsert=ccInsertInsert_tsk && busDataReady;
426
 
427
  assign busAddr=ccInsertRamReq_tsk ? IP & 32'hffff_ffc0 :32'bz;
428
  assign busAddr=dcInsertRamReq_tsk ? dcReadAddr & 32'hffff_ffc0: 32'bz;
429
  assign busAddr=dcInsertWriteBack_tsk ? dcOldAddr_reg : 32'bz;
430
  assign busAddr=(!ccInsertRamReq_tsk && !dcInsertRamReq_tsk && !dcInsertWriteBack_tsk) ? 32'b0 : 32'bz;
431
 
432
  assign busRead=(ccInsertRamReq_tsk || dcInsertRamReq_tsk) && busEnRead;
433
  assign busWrite=dcInsertWriteBack_tsk && busEnWrite;
434
 
435
  assign dcDataWriteBack=dcDataA;
436
  assign busOutput=dcDataWriteBack_reg;
437
 
438
  assign rA0=instr0[10:6];
439
  assign rB0=instr0[15:11];
440
  assign rF0=instr0[20:16];
441
  assign rC=instr0[10:6];
442
 
443
  assign intregwe=!stall && !stginhibit[4] && (aluwrtval || aguwrtval) && (!agustall_reg) && !((agureaden_reg || aguwriteen_reg) && !dcHit); // adjust for other cases ie mem read-done;
444
  assign intregdataF= aguwrtval ? readdata : opF; //adjust for ie mem read-done
445
  assign opA=rAfwd ? regfwd : intregdataA;
446
  assign opB=rBfwd ? regfwd : intregdataB;
447
  assign opC=rCfwd ? regfwd : intregdataC;
448
 
449
  //assign instr0=fetchdata; //change for branch prediction
450
 
451
  assign rFprev=instr[20:16];
452
  assign rFprevprev=instr4[20:16];
453
  //assign rAfwd=(rA==rFprev);
454
  //assign rBfwd=(rB==rFprev);
455
  //assign intregdataF=opF;
456
 
457
  assign readaddr=aguaddr;
458
 
459
  assign brpred_jumpinstr=alucjmpinstr || uJmpInstr;
460
  assign brpred_inserttaken=alucjmp || uJmpInstr;
461
  assign brpred_instertinstr=instr4;
462
  assign brpred_instertaddr=IP5;
463
  assign brpred_insertnextaddr=alucjmpinstr ? cjmpaddr : aguaddr_reg ;
464
 
465
  assign retAddr=IP5+4;
466
  assign uJmpInstr=(instr4[5:0]==46 || instr4[5:0]==47);
467
 
468
  //regfwrt<=0;
469
  always @(posedge clk)
470
    begin
471
      if (init)
472
        begin
473
          initcount<=initcount-1;
474
          if (initcount==0) init<=0;
475
        end
476
      if (ccInit)
477
        begin
478
          ccInitCount<=ccInitCount-1;
479
          if (ccInitCount==0) ccInit<=0;
480
        end
481
      if (dcInit)
482
        begin
483
          dcInitCount<=dcInitCount-1;
484
          if (dcInitCount==0) dcInit<=0;
485
        end
486
      if (ccInsertRamReq_tsk && busEnRead)
487
        begin
488
          ccInsertRamReq_tsk<=0;
489
          ccInsertInsert_tsk<=1;
490
        end
491
      if (ccInsertInsert_tsk && busDataReady)
492
        begin
493
          ccInsertInsert_tsk<=0;
494
          ccInsertWait1_tsk<=1;
495
        end
496
      if (ccInsertWait1_tsk)
497
        begin
498
          ccInsertWait1_tsk<=0;
499
          ccInsertWait2_tsk<=1;
500
        end
501
      if (ccInsertWait2_tsk)
502
        begin
503
          ccInsertWait2_tsk<=0;
504
          ccInsertInProgress_tsk<=0;
505
        end
506
      if (dcInsertRamReq_tsk && busEnRead)
507
        begin
508
          dcInsertRamReq_tsk<=0;
509
          dcInsertInsert_tsk<=1;
510
        end
511
      if (dcInsertInsert_tsk && busDataReady)
512
        begin
513
          dcInsertInsert_tsk<=0;
514
          dcInsertCheckDirty_tsk<=1;
515
        end
516
      if (dcInsertCheckDirty_tsk)
517
        begin
518
          dcInsertCheckDirty_tsk<=0;
519
          if (dcHit)
520
            begin
521
              dcInsertWriteBack_tsk<=1;
522
              dcOldAddr_reg<=dcOldAddr;
523
              dcDataWriteBack_reg<=dcDataWriteBack;
524
            end
525
          else
526
            begin
527
              dcInsertInProgress_tsk<=0;
528
            end
529
        end
530
      if (dcInsertWriteBack_tsk && busEnWrite)
531
        begin
532
          dcInsertWriteBack_tsk<=0;
533
          dcInsertInProgress_tsk<=0;
534
        end
535
      //stginhibit_wrt=stginhibit;
536
      if (stginhibit[1]) stginhibit_wrt[2]=1;
537
      if (stginhibit[2]) stginhibit_wrt[3]=1;
538
      if (stginhibit[3]) stginhibit_wrt[4]=1;
539
      agustall_reg<=agustall;
540
      agureaden_reg<=agureaden;
541
      aguwriteen_reg<=aguwriteen;
542
      readaddr_reg<=readaddr;
543
      //cycle 1
544
      if (!stall)
545
        begin
546 8 gorand2
          stginhibit[1]<=0;
547
          cycle1prev<=1;
548
          IP<=fetchaddr+4;
549
          IP2<=fetchaddr;
550
          multiCycleStall[1]<=multiCycleStall[0];
551
          multiCycleStall[0]<=0;
552 9 gorand2
          if (irq&irq_mask)
553 8 gorand2
            begin
554
              stginhibit<=5'b11110;
555
              codeMiss<=0;
556
              IP<=irq_handler;
557
              irq_bits<=irq;
558
            end
559 2 gorand2
        end
560
      else  cycle1prev<=0;
561
 
562
      //cycle 2
563
      if (!stall && !stginhibit[1])
564
        begin
565
          stginhibit[2]<=0;
566
          IP3<=IP2;
567
          multiCycleStall[2]<=multiCycleStall[1];
568
          if (!(brpred_hit&&brpred_taken)) instr0<=ccHit ? fetchdata : 32'b01100;
569
            else instr0<=brpred_instr;
570
          brtaken3<=(brpred_hit&&brpred_taken);
571
          if (!ccHit)
572
            begin
573
              codeMiss[1]<=1;
574
              codeMiss[2]<=1;
575
            end
576
          if (codeMiss[1]) codeMiss[2]<=1;
577
 
578
        end
579
      //cycle 3
580
      if (!stall && !stginhibit[2])
581
        begin
582
          instr<=instr0;
583
          //reg_instr0<=fetchdata;
584
          stginhibit[3]<=0;
585
          multiCycleStall[3]<=multiCycleStall[2];
586
          IP4<=IP3;
587
          rA<=instr0[10:6];
588
          rB<=instr0[15:11];
589
          brtaken4<=brtaken3;
590
          codeMiss[3]<=codeMiss[2];
591
          cjmpoffset0<={ {14{instr0[31]}}, instr0[31:16],2'b0 };
592
          if (instr0[5:0]==30) //upper bits instr
593
            begin
594
              prevUpperBits<=1;
595
              constBits[31:16]<=instr0[31:16];
596
            end
597
          else
598
            begin
599
              prevUpperBits<=0;
600
            end
601
          if (instr0[5:0]==60 || instr0[5:0]==61 || instr0[5:0]==62) //store instr
602
            begin
603
              constBits[15:0]<=instr0[31:16];
604
            end
605
          else  //non-store instr
606
            begin
607
              constBits[15:0]<={instr0[31:21],instr0[15:11]};
608
            end
609
          if (!prevUpperBits) constBits[31:16]<={16{instr0[31]}};
610
        end
611
      //cycle 4
612
      if (!stall && !stginhibit[3])
613
        begin
614
          constBits4<=constBits;
615
          stginhibit[4]<=0;
616
          IP5<=IP4;
617
          multiCycleStall[4]<=multiCycleStall[3];
618
          rAfwd0<=(rA0==rFprev);
619
          rBfwd0<=(rB0==rFprev);
620
          instr4<=instr;
621
          rF<=instr[20:16];
622
          cjmpoffset<={ {14{instr[31]}}, instr[31:16],2'b0 };
623
          cjmpaddr<=IP4+cjmpoffset0;
624
          brtaken5<=brtaken4;
625
          codeMiss[4]<=codeMiss[3];
626
          aguaddr_reg<=aguaddr;
627
        end
628
      //cycle 5
629
 
630
      if (!stall && !stginhibit[4]) //remove !stall ??
631
        begin
632
          rAfwd<=rAfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //adjust for other sources of data
633
          rBfwd<=rBfwd0 && (aluwrtval || aguwrtval) && (!agustall_reg); //these 2 indicate forwarding of operands from regfwd
634
          rCfwd<=(rA0==rFprevprev) && (aluwrtval || aguwrtval) && (!agustall_reg);
635
 
636
          regfwd<=aguwrtval ? readdata : opF;
637
          if (codeMiss[4])
638
            begin
639
              stginhibit<=5'b11110;
640
              codeMiss<=0;
641
              IP<=IP5;
642
              ccInsertInProgress_tsk<=1;
643
              ccInsertRamReq_tsk<=1;
644
            end
645
          else if ((agureaden_reg || aguwriteen_reg) && !dcHit && !agustall_reg)
646
            begin
647
              stginhibit<=5'b11110;
648
              codeMiss<=0;
649
              IP<=IP5;
650
              dcInsertInProgress_tsk<=1;
651
              dcInsertRamReq_tsk<=1;
652
              dcReadAddr<=readaddr_reg;
653
            end
654
          else if ((((alucjmpinstr && alucjmp) || uJmpInstr) ^ brtaken5) || brpred_addrMismatch)
655
            begin
656
              stginhibit<=5'b11110;
657
              codeMiss<=0;
658
              IP<=(alucjmp || uJmpInstr) ? (alucjmpinstr ? (IP5+cjmpoffset) : (opA+constBits4) ): IP5+4;
659
            end
660
          else if (agustall_reg)
661
            begin
662
              stginhibit<=5'b11110;
663
              codeMiss<=0;
664
              IP<=IP5;
665
            end
666
          else if (ioInstrDoStall)
667
            begin
668
              stginhibit<=5'b11110;
669
              codeMiss<=0;
670
              IP<=IP5;
671
              multiCycleStall[0]<=1;
672
            end
673 8 gorand2
          else if (wrspec)
674
            begin
675 9 gorand2
              case (instr4[31:24])
676
                8'd0: irq_handler<=opF;
677
                8'd1: sys_flags<=opF;
678
                8'd2: irq_mask<=opF;
679 8 gorand2
              endcase
680
            end
681 2 gorand2
        end
682
      else
683
        begin
684
          rAfwd<=0;
685
          rBfwd<=0;
686
          rCfwd<=0;
687
        end
688
      //
689
    end
690
endmodule

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