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gorand2 |
`include "config.v"
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module datacache(input clk,input stall,input [4:0] stginhibit,input [4:0] codemiss,input [31:0] addrA,output `muxnet [511:0] dataA,input [511:0] cacheLine,input [31:0] writeData,output `muxnet cacheHit,input readen,input writeen,input insert,input initEntry,input [1:0] readsz,output `muxnet [31:0] oldAddr);
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wire tagwe;
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wire [31:0] tagAddrA;
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wire [31:0] tagAddrW;
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wire [119:0] tagDataA;
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`muxnet [119:0] tagDataW;
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reg [31:0] tagAddrA_reg;
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reg readen_reg=0;
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reg writeen_reg=0;
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reg insert_reg=0;
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reg initEntry_reg=0;
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reg [119:0] tagDataA_fwd;
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wire [119:0] ramTagDataA;
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reg tag_fwd=0;
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wire [31:0] pad0;
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wire [31:0] pad1;
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wire [31:0] pad2;
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wire [31:0] pad3;
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wire [1:0] pos0;
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wire [1:0] pos1;
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wire [1:0] pos2;
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wire [1:0] pos3;
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wire val0;
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wire val1;
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wire val2;
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wire val3;
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wire dir0;
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wire dir1;
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wire dir2;
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wire dir3;
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wire [1:0] newPos0;
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wire [1:0] newPos1;
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wire [1:0] newPos2;
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wire [1:0] newPos3;
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`muxnet hit3,hit2,hit1,hit0;
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wire hit;
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wire ram0We,ram1We,ram2We,ram3We;
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wire [31:0] ramAddrW;
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wire [31:0] ramAddrA;
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wire [511:0] ramDataR0;
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wire [511:0] ramDataR1;
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wire [511:0] ramDataR2;
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wire [511:0] ramDataR3;
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wire [511:0] ramDataW0;
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wire [511:0] ramDataW1;
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wire [511:0] ramDataW2;
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wire [511:0] ramDataW3;
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wire [511:0] ramDataWA0;
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wire [511:0] ramDataWA1;
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wire [511:0] ramDataWA2;
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wire [511:0] ramDataWA3;
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reg [511:0] cacheLine_reg;
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wire [31:0] dataA0;
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wire [31:0] dataA1;
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wire [31:0] dataA2;
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wire [31:0] dataA3;
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reg [1:0] readsz_reg;
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datacacheramtag tag0(clk,tagwe,tagAddrA[11:6],tagAddrW[11:6],ramTagDataA,tagDataW);
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datacache_get_new_pos newpos0(pos0,pos1,pos2,pos3,hit0,hit1,hit2,hit3,newPos0,newPos1,newPos2,newPos3);
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datacacheramfwd ram0(clk,ram0We,ramAddrA,ramAddrW,ramDataR0,ramDataW0);
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datacacheramfwd ram1(clk,ram1We,ramAddrA,ramAddrW,ramDataR1,ramDataW1);
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datacacheramfwd ram2(clk,ram2We,ramAddrA,ramAddrW,ramDataR2,ramDataW2);
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datacacheramfwd ram3(clk,ram3We,ramAddrA,ramAddrW,ramDataR3,ramDataW3);
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datacache_data_sel data_sel0(ramDataR0,tagAddrA_reg[5:0],readsz_reg,dataA0);
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datacache_data_sel data_sel1(ramDataR1,tagAddrA_reg[5:0],readsz_reg,dataA1);
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datacache_data_sel data_sel2(ramDataR2,tagAddrA_reg[5:0],readsz_reg,dataA2);
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datacache_data_sel data_sel3(ramDataR3,tagAddrA_reg[5:0],readsz_reg,dataA3);
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datacache_get_write_data wrtdat0 (ramDataR0,writeData,tagAddrA_reg,readsz_reg,ramDataWA0);
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datacache_get_write_data wrtdat1 (ramDataR1,writeData,tagAddrA_reg,readsz_reg,ramDataWA1);
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datacache_get_write_data wrtdat2 (ramDataR2,writeData,tagAddrA_reg,readsz_reg,ramDataWA2);
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datacache_get_write_data wrtdat3 (ramDataR3,writeData,tagAddrA_reg,readsz_reg,ramDataWA3);
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assign tagAddrA=addrA;
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assign tagDataA=tag_fwd ? tagDataA_fwd : ramTagDataA;
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assign tagwe=((readen_reg || writeen_reg) && !stall && !stginhibit[4] && !codemiss[4] ) || insert_reg || initEntry_reg;
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assign tagAddrW=tagAddrA_reg;
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assign { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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pos3,pos2,pos1,pos0,
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val3,val2,val1,val0,
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dir3,dir2,dir1,dir0 } = tagDataA;
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assign pad3[5:0]=6'b0;
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assign pad2[5:0]=6'b0;
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assign pad1[5:0]=6'b0;
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assign pad0[5:0]=6'b0;
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assign hit3=(readen_reg || writeen_reg) ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
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assign hit2=(readen_reg || writeen_reg) ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
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assign hit1=(readen_reg || writeen_reg) ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
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assign hit0=(readen_reg || writeen_reg) ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval;
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assign hit3=insert_reg ? (pos3==2'b11) : 1'b`muxval;
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assign hit2=insert_reg ? (pos2==2'b11) : 1'b`muxval;
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assign hit1=insert_reg ? (pos1==2'b11) : 1'b`muxval;
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assign hit0=insert_reg ? (pos0==2'b11) : 1'b`muxval;
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assign hit3=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
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assign hit2=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
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assign hit1=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
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assign hit0=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval;
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assign hit=hit3 || hit2 || hit1 || hit0;
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assign cacheHit= (insert_reg && hit0) ? val0 && dir0 : 1'b`muxval;
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assign cacheHit= (insert_reg && hit1) ? val1 && dir1 : 1'b`muxval;
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assign cacheHit= (insert_reg && hit2) ? val2 && dir2 : 1'b`muxval;
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assign cacheHit= (insert_reg && hit3) ? val3 && dir3 : 1'b`muxval;
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assign cacheHit= insert_reg ? 1'b`muxval : hit;
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assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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dir3,dir2,dir1,dir0 } : 120'b`muxval;
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assign tagDataW=(writeen_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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dir3,dir2,dir1,1'b1 } : 120'b`muxval;
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assign tagDataW=(writeen_reg && hit1) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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dir3,dir2,1'b1,dir0 } : 120'b`muxval;
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assign tagDataW=(writeen_reg && hit2) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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dir3,1'b1,dir1,dir0 } : 120'b`muxval;
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assign tagDataW=(writeen_reg && hit3) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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1'b1,dir2,dir1,dir0 } : 120'b`muxval;
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assign tagDataW=(writeen_reg && !hit) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,val0,
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dir3,dir2,dir1,dir0 } : 120'b`muxval;
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assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,val1,1'b1,
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dir3,dir2,dir1,1'b0 } : 120'b`muxval;
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assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,val2,1'b1,val0,
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dir3,dir2,1'b0,dir0 } : 120'b`muxval;
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assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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val3,1'b1,val1,val0,
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dir3,1'b0,dir1,dir0 } : 120'b`muxval;
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assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6],
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newPos3,newPos2,newPos1,newPos0,
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1'b1,val2,val1,val0,
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1'b0,dir2,dir1,dir0 } : 120'b`muxval;
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// assign tagDataW=(insert_reg && !hit) ? 120'b0 : 120'bz;
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assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0,
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2'b11,2'b10,2'b01,2'b00,
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1'b0,1'b0,1'b0,1'b0,
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1'b0,1'b0,1'b0,1'b0} : 120'b`muxval;
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assign tagDataW=(!insert_reg && !readen_reg && !writeen_reg && !initEntry_reg) ? 120'b0 : 120'b`muxval;
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assign dataA=(!insert_reg && hit0) ? {480'b0,dataA0} : 512'b`muxval;
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assign dataA=(!insert_reg && hit1) ? {480'b0,dataA1} : 512'b`muxval;
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assign dataA=(!insert_reg && hit2) ? {480'b0,dataA2} : 512'b`muxval;
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assign dataA=(!insert_reg && hit3) ? {480'b0,dataA3} : 512'b`muxval;
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assign dataA=(insert_reg && hit0) ? ramDataR0 : 512'b`muxval;
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assign dataA=(insert_reg && hit1) ? ramDataR1 : 512'b`muxval;
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assign dataA=(insert_reg && hit2) ? ramDataR2 : 512'b`muxval;
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assign dataA=(insert_reg && hit3) ? ramDataR3 : 512'b`muxval;
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assign dataA= hit ? 512'b`muxval : 512'b0; //change to accomodate non-read ops
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assign ramDataW0=insert_reg ? cacheLine_reg : ramDataWA0;
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assign ramDataW1=insert_reg ? cacheLine_reg : ramDataWA1;
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assign ramDataW2=insert_reg ? cacheLine_reg : ramDataWA2;
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assign ramDataW3=insert_reg ? cacheLine_reg : ramDataWA3;
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assign ram0We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit0;
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assign ram1We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit1;
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assign ram2We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit2;
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assign ram3We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit3;
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assign oldAddr=(insert_reg && hit0) ? pad0 : 32'b`muxval;
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assign oldAddr=(insert_reg && hit1) ? pad1 : 32'b`muxval;
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assign oldAddr=(insert_reg && hit2) ? pad2 : 32'b`muxval;
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assign oldAddr=(insert_reg && hit3) ? pad3 : 32'b`muxval;
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assign oldAddr=(!insert_reg) ? 32'b0 : 32'b`muxval;
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assign ramAddrA={tagAddrA[31:6],6'b0};
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assign ramAddrW={tagAddrA_reg[31:6],6'b0};
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| 203 |
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always @(posedge clk)
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| 204 |
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begin
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| 205 |
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tagDataA_fwd<=tagDataW;
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tag_fwd<=tagwe && (addrA[11:6]==tagAddrA_reg[11:6]);
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| 207 |
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tagAddrA_reg<=tagAddrA;
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readen_reg<=readen;
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writeen_reg<=writeen;
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| 210 |
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insert_reg<=insert;
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| 211 |
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initEntry_reg<=initEntry;
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| 212 |
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cacheLine_reg<=cacheLine;
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| 213 |
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readsz_reg<=readsz;
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| 214 |
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end
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| 215 |
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| 216 |
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endmodule
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| 217 |
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| 218 |
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module datacacheram(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [511:0] dataA,input [511:0] dataW);
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| 219 |
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reg [511:0] ram [63:0];
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| 220 |
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| 221 |
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always @(posedge clk)
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| 222 |
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begin
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| 223 |
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dataA<=ram[addrA];
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| 224 |
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if (we) ram[addrW]<=dataW;
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| 225 |
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end
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| 226 |
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| 227 |
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endmodule
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| 228 |
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| 229 |
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module datacacheramfwd(input clk,input we,input [31:0] addrA,input [31:0] addrW,output wire [511:0] dataA,input [511:0] dataW);
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| 230 |
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wire [511:0] ramDataA;
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| 231 |
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reg we_reg;
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| 232 |
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reg [511:0] dataW_reg;
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| 233 |
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reg [31:0] addrW_reg;
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| 234 |
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reg fwd=0;
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| 235 |
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| 236 |
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datacacheram ram0(clk,we,addrA[11:6],addrW[11:6],ramDataA,dataW);
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| 237 |
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| 238 |
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| 239 |
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assign dataA=fwd ? dataW_reg : ramDataA;
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| 240 |
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| 241 |
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always@(posedge clk)
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| 242 |
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begin
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| 243 |
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we_reg<=we;
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| 244 |
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dataW_reg<=dataW;
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| 245 |
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addrW_reg<=addrW;
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| 246 |
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fwd<=we && (addrW[11:6]==addrA[11:6]);
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| 247 |
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end
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| 248 |
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| 249 |
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endmodule
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| 250 |
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| 251 |
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/*
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| 252 |
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tag for 4 way set-asociative LRU data cache
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| 253 |
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{
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| 254 |
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{pad3,pad2,pad1,pad0}, //4x 26 bit physical address
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| 255 |
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{pos3,pos2,pos1,pos0}, //4xeach 2 bit LRU position, 8 bit
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| 256 |
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{val3,val2,val1,val0} //4x 1 bit valid entry, 4 bit
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| 257 |
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{dir3,dir2,dir1,dir0} //4x dirty bit
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| 258 |
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}
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| 259 |
|
|
length =30*4=120 bit tag
|
| 260 |
|
|
*/
|
| 261 |
|
|
|
| 262 |
|
|
module datacacheramtag(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [119:0] dataA,input [119:0] dataW);
|
| 263 |
|
|
reg [119:0] ram [63:0];
|
| 264 |
|
|
|
| 265 |
|
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always @(posedge clk)
|
| 266 |
|
|
begin
|
| 267 |
|
|
dataA<=ram[addrA];
|
| 268 |
|
|
if (we) ram[addrW]<=dataW;
|
| 269 |
|
|
end
|
| 270 |
|
|
|
| 271 |
|
|
endmodule
|
| 272 |
|
|
|
| 273 |
|
|
module datacache_get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3,
|
| 274 |
|
|
input hit0,input hit1,input hit2,input hit3,
|
| 275 |
|
|
output `muxnet [1:0] newPos0,output `muxnet [1:0] newPos1,output `muxnet [1:0] newPos2,output `muxnet [1:0] newPos3);
|
| 276 |
|
|
wire hit;
|
| 277 |
|
|
|
| 278 |
|
|
assign hit=hit0 || hit1 || hit2 || hit3;
|
| 279 |
|
|
|
| 280 |
|
|
assign newPos0=hit0 ? 0 : 2'b`muxval;
|
| 281 |
|
|
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'b`muxval;
|
| 282 |
|
|
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'b`muxval;
|
| 283 |
|
|
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'b`muxval;
|
| 284 |
|
|
|
| 285 |
|
|
assign newPos1=hit1 ? 0 : 2'b`muxval;
|
| 286 |
|
|
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'b`muxval;
|
| 287 |
|
|
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'b`muxval;
|
| 288 |
|
|
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'b`muxval;
|
| 289 |
|
|
|
| 290 |
|
|
assign newPos2=hit2 ? 0 : 2'b`muxval;
|
| 291 |
|
|
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'b`muxval;
|
| 292 |
|
|
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'b`muxval;
|
| 293 |
|
|
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'b`muxval;
|
| 294 |
|
|
|
| 295 |
|
|
assign newPos3=hit3 ? 0 : 2'b`muxval;
|
| 296 |
|
|
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'b`muxval;
|
| 297 |
|
|
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'b`muxval;
|
| 298 |
|
|
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'b`muxval;
|
| 299 |
|
|
|
| 300 |
|
|
assign newPos0=hit ? 2'b`muxval : pos0;
|
| 301 |
|
|
assign newPos1=hit ? 2'b`muxval : pos1;
|
| 302 |
|
|
assign newPos2=hit ? 2'b`muxval : pos2;
|
| 303 |
|
|
assign newPos3=hit ? 2'b`muxval : pos3;
|
| 304 |
|
|
|
| 305 |
|
|
endmodule
|
| 306 |
|
|
|
| 307 |
|
|
|
| 308 |
|
|
module datacache_data_sel(input [511:0] dataIn,input [5:0] sel, input [1:0] readsz, output `muxnet [31:0] dataOut);
|
| 309 |
|
|
wire [255:0] bit5Data;
|
| 310 |
|
|
wire [127:0] bit4Data;
|
| 311 |
|
|
wire [63:0] bit3Data;
|
| 312 |
|
|
wire [31:0] data32;
|
| 313 |
|
|
wire [15:0] data16;
|
| 314 |
|
|
wire [7:0] data8;
|
| 315 |
|
|
|
| 316 |
|
|
assign bit5Data=sel[5] ? dataIn[511:256] : dataIn[255:0];
|
| 317 |
|
|
assign bit4Data=sel[4] ? bit5Data[255:128] : bit5Data[127:0];
|
| 318 |
|
|
assign bit3Data=sel[3] ? bit4Data[127:64] : bit4Data[63:0];
|
| 319 |
|
|
|
| 320 |
|
|
assign data32 =sel[2] ? bit3Data[63:32] : bit3Data[31:0];
|
| 321 |
|
|
assign data16 =sel[1] ? data32[31:16] : data32[15:0];
|
| 322 |
|
|
assign data8 =sel[0] ? data16[15:8] : data16[7:0];
|
| 323 |
|
|
|
| 324 |
|
|
assign dataOut=(readsz==0) ? {24'b0,data8} : 32'b`muxval;
|
| 325 |
|
|
assign dataOut=(readsz==1) ? {16'b0,data16} : 32'b`muxval;
|
| 326 |
|
|
assign dataOut=(readsz==2) ? data32 : 32'b`muxval;
|
| 327 |
|
|
assign dataOut=(readsz==4) ? 32'b0 : 32'b`muxval;
|
| 328 |
|
|
|
| 329 |
|
|
endmodule
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
|
|
module datacache_write_shift(input [31:0] dataIn,input [1:0] writesz,input [31:0] addr, output wire [511:0] dataOut, output wire [63:0] byteEnable);
|
| 333 |
|
|
`muxnet [511:0] data6;
|
| 334 |
|
|
wire [511:0] data5;
|
| 335 |
|
|
wire [511:0] data4;
|
| 336 |
|
|
wire [511:0] data3;
|
| 337 |
|
|
wire [511:0] data2;
|
| 338 |
|
|
wire [511:0] data1;
|
| 339 |
|
|
wire [511:0] data0;
|
| 340 |
|
|
|
| 341 |
|
|
`muxnet [63:0] byteEnable6;
|
| 342 |
|
|
wire [63:0] byteEnable5;
|
| 343 |
|
|
wire [63:0] byteEnable4;
|
| 344 |
|
|
wire [63:0] byteEnable3;
|
| 345 |
|
|
wire [63:0] byteEnable2;
|
| 346 |
|
|
wire [63:0] byteEnable1;
|
| 347 |
|
|
wire [63:0] byteEnable0;
|
| 348 |
|
|
|
| 349 |
|
|
// change data6 to explicit mux!
|
| 350 |
|
|
assign data6=(writesz==0) ? {504'b0,dataIn[7:0]} : 512'b`muxval;
|
| 351 |
|
|
assign data6=(writesz==1) ? {496'b0,dataIn[15:0]} : 512'b`muxval;
|
| 352 |
|
|
assign data6=(writesz==2) ? {480'b0,dataIn} : 512'b`muxval;
|
| 353 |
|
|
assign data6=(writesz==3) ? 512'b0 : 512'b`muxval;
|
| 354 |
|
|
|
| 355 |
|
|
assign data5=addr[5] ? { data6[255:0], 256'b0 }: data6;
|
| 356 |
|
|
assign data4=addr[4] ? { data5[383:0], 128'b0 }: data5;
|
| 357 |
|
|
assign data3=addr[3] ? { data4[447:0], 64'b0 }: data4;
|
| 358 |
|
|
assign data2=addr[2] ? { data3[479:0], 32'b0 }: data3;
|
| 359 |
|
|
assign data1=addr[1] ? { data2[495:0], 16'b0 }: data2;
|
| 360 |
|
|
assign data0=addr[0] ? { data1[503:0], 8'b0 }: data1;
|
| 361 |
|
|
|
| 362 |
|
|
assign dataOut=data0;
|
| 363 |
|
|
//change byteEnable6 to explicit mux!
|
| 364 |
|
|
assign byteEnable6=(writesz==0) ? 64'b0001 : 64'b`muxval;
|
| 365 |
|
|
assign byteEnable6=(writesz==1) ? 64'b0011 : 64'b`muxval;
|
| 366 |
|
|
assign byteEnable6=(writesz==2) ? 64'b1111 : 64'b`muxval;
|
| 367 |
|
|
assign byteEnable6=(writesz==3) ? 64'b0000 : 64'b`muxval;
|
| 368 |
|
|
|
| 369 |
|
|
assign byteEnable5=addr[5] ? { byteEnable6[31:0],32'b0 } : byteEnable6;
|
| 370 |
|
|
assign byteEnable4=addr[4] ? { byteEnable5[47:0],16'b0 } : byteEnable5;
|
| 371 |
|
|
assign byteEnable3=addr[3] ? { byteEnable4[55:0],8'b0 } : byteEnable4;
|
| 372 |
|
|
assign byteEnable2=addr[2] ? { byteEnable3[59:0],4'b0 } : byteEnable3;
|
| 373 |
|
|
assign byteEnable1=addr[1] ? { byteEnable2[61:0],2'b0 } : byteEnable2;
|
| 374 |
|
|
assign byteEnable0=addr[0] ? { byteEnable1[62:0],1'b0 } : byteEnable1;
|
| 375 |
|
|
|
| 376 |
|
|
assign byteEnable=byteEnable0;
|
| 377 |
|
|
|
| 378 |
|
|
endmodule
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
module datacache_get_write_data(input [511:0] prevCacheline, input [31:0] data, input [31:0] addr, input [1:0] writesz,output wire [511:0] newCacheline);
|
| 382 |
|
|
wire [511:0] cacheLine1;
|
| 383 |
|
|
wire [63:0] byteEnable;
|
| 384 |
|
|
datacache_write_shift shift0(data,writesz,addr,cacheLine1,byteEnable);
|
| 385 |
|
|
assign newCacheline=
|
| 386 |
|
|
{
|
| 387 |
|
|
byteEnable[63] ? cacheLine1[511:504] : prevCacheline[511:504],
|
| 388 |
|
|
byteEnable[62] ? cacheLine1[503:496] : prevCacheline[503:496],
|
| 389 |
|
|
byteEnable[61] ? cacheLine1[495:488] : prevCacheline[495:488],
|
| 390 |
|
|
byteEnable[60] ? cacheLine1[487:480] : prevCacheline[487:480],
|
| 391 |
|
|
byteEnable[59] ? cacheLine1[479:472] : prevCacheline[479:472],
|
| 392 |
|
|
byteEnable[58] ? cacheLine1[471:464] : prevCacheline[471:464],
|
| 393 |
|
|
byteEnable[57] ? cacheLine1[463:456] : prevCacheline[463:456],
|
| 394 |
|
|
byteEnable[56] ? cacheLine1[455:448] : prevCacheline[455:448],
|
| 395 |
|
|
byteEnable[55] ? cacheLine1[447:440] : prevCacheline[447:440],
|
| 396 |
|
|
byteEnable[54] ? cacheLine1[439:432] : prevCacheline[439:432],
|
| 397 |
|
|
byteEnable[53] ? cacheLine1[431:424] : prevCacheline[431:424],
|
| 398 |
|
|
byteEnable[52] ? cacheLine1[423:416] : prevCacheline[423:416],
|
| 399 |
|
|
byteEnable[51] ? cacheLine1[415:408] : prevCacheline[415:408],
|
| 400 |
|
|
byteEnable[50] ? cacheLine1[407:400] : prevCacheline[407:400],
|
| 401 |
|
|
byteEnable[49] ? cacheLine1[399:392] : prevCacheline[399:392],
|
| 402 |
|
|
byteEnable[48] ? cacheLine1[391:384] : prevCacheline[391:384],
|
| 403 |
|
|
byteEnable[47] ? cacheLine1[383:376] : prevCacheline[383:376],
|
| 404 |
|
|
byteEnable[46] ? cacheLine1[375:368] : prevCacheline[375:368],
|
| 405 |
|
|
byteEnable[45] ? cacheLine1[367:360] : prevCacheline[367:360],
|
| 406 |
|
|
byteEnable[44] ? cacheLine1[359:352] : prevCacheline[359:352],
|
| 407 |
|
|
byteEnable[43] ? cacheLine1[351:344] : prevCacheline[351:344],
|
| 408 |
|
|
byteEnable[42] ? cacheLine1[343:336] : prevCacheline[343:336],
|
| 409 |
|
|
byteEnable[41] ? cacheLine1[335:328] : prevCacheline[335:328],
|
| 410 |
|
|
byteEnable[40] ? cacheLine1[327:320] : prevCacheline[327:320],
|
| 411 |
|
|
byteEnable[39] ? cacheLine1[319:312] : prevCacheline[319:312],
|
| 412 |
|
|
byteEnable[38] ? cacheLine1[311:304] : prevCacheline[311:304],
|
| 413 |
|
|
byteEnable[37] ? cacheLine1[303:296] : prevCacheline[303:296],
|
| 414 |
|
|
byteEnable[36] ? cacheLine1[295:288] : prevCacheline[295:288],
|
| 415 |
|
|
byteEnable[35] ? cacheLine1[287:280] : prevCacheline[287:280],
|
| 416 |
|
|
byteEnable[34] ? cacheLine1[279:272] : prevCacheline[279:272],
|
| 417 |
|
|
byteEnable[33] ? cacheLine1[271:264] : prevCacheline[271:264],
|
| 418 |
|
|
byteEnable[32] ? cacheLine1[263:256] : prevCacheline[263:256],
|
| 419 |
|
|
byteEnable[31] ? cacheLine1[255:248] : prevCacheline[255:248],
|
| 420 |
|
|
byteEnable[30] ? cacheLine1[247:240] : prevCacheline[247:240],
|
| 421 |
|
|
byteEnable[29] ? cacheLine1[239:232] : prevCacheline[239:232],
|
| 422 |
|
|
byteEnable[28] ? cacheLine1[231:224] : prevCacheline[231:224],
|
| 423 |
|
|
byteEnable[27] ? cacheLine1[223:216] : prevCacheline[223:216],
|
| 424 |
|
|
byteEnable[26] ? cacheLine1[215:208] : prevCacheline[215:208],
|
| 425 |
|
|
byteEnable[25] ? cacheLine1[207:200] : prevCacheline[207:200],
|
| 426 |
|
|
byteEnable[24] ? cacheLine1[199:192] : prevCacheline[199:192],
|
| 427 |
|
|
byteEnable[23] ? cacheLine1[191:184] : prevCacheline[191:184],
|
| 428 |
|
|
byteEnable[22] ? cacheLine1[183:176] : prevCacheline[183:176],
|
| 429 |
|
|
byteEnable[21] ? cacheLine1[175:168] : prevCacheline[175:168],
|
| 430 |
|
|
byteEnable[20] ? cacheLine1[167:160] : prevCacheline[167:160],
|
| 431 |
|
|
byteEnable[19] ? cacheLine1[159:152] : prevCacheline[159:152],
|
| 432 |
|
|
byteEnable[18] ? cacheLine1[151:144] : prevCacheline[151:144],
|
| 433 |
|
|
byteEnable[17] ? cacheLine1[143:136] : prevCacheline[143:136],
|
| 434 |
|
|
byteEnable[16] ? cacheLine1[135:128] : prevCacheline[135:128],
|
| 435 |
|
|
byteEnable[15] ? cacheLine1[127:120] : prevCacheline[127:120],
|
| 436 |
|
|
byteEnable[14] ? cacheLine1[119:112] : prevCacheline[119:112],
|
| 437 |
|
|
byteEnable[13] ? cacheLine1[111:104] : prevCacheline[111:104],
|
| 438 |
|
|
byteEnable[12] ? cacheLine1[103:96] : prevCacheline[103:96],
|
| 439 |
|
|
byteEnable[11] ? cacheLine1[95:88] : prevCacheline[95:88],
|
| 440 |
|
|
byteEnable[10] ? cacheLine1[87:80] : prevCacheline[87:80],
|
| 441 |
|
|
byteEnable[9] ? cacheLine1[79:72] : prevCacheline[79:72],
|
| 442 |
|
|
byteEnable[8] ? cacheLine1[71:64] : prevCacheline[71:64],
|
| 443 |
|
|
byteEnable[7] ? cacheLine1[63:56] : prevCacheline[63:56],
|
| 444 |
|
|
byteEnable[6] ? cacheLine1[55:48] : prevCacheline[55:48],
|
| 445 |
|
|
byteEnable[5] ? cacheLine1[47:40] : prevCacheline[47:40],
|
| 446 |
|
|
byteEnable[4] ? cacheLine1[39:32] : prevCacheline[39:32],
|
| 447 |
|
|
byteEnable[3] ? cacheLine1[31:24] : prevCacheline[31:24],
|
| 448 |
|
|
byteEnable[2] ? cacheLine1[23:16] : prevCacheline[23:16],
|
| 449 |
|
|
byteEnable[1] ? cacheLine1[15:8] : prevCacheline[15:8],
|
| 450 |
|
|
byteEnable[0] ? cacheLine1[7:0] : prevCacheline[7:0]
|
| 451 |
|
|
};
|
| 452 |
|
|
|
| 453 |
|
|
endmodule
|
