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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [twoway/] [FT64.v] - Blame information for rev 66

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1 60 robfinch
// ============================================================================
2
//        __
3 61 robfinch
//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo
4 60 robfinch
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
8
//      FT64.v
9
//      Features include:
10
//  - 16/32/48 bit instructions
11
//  - vector instruction set,
12
//  - SIMD instructions
13
//  - data width of 64 bits
14
//      - 32 general purpose registers
15
//  - 32 floating point registers
16
//      - 32 vector registers, length 63
17
//  - powerful branch prediction
18
//  - branch target buffer (BTB)
19
//  - return address predictor (RSB)
20
//  - bus interface unit
21
//  - instruction and data caches
22
//      - fine-grained simultaneous multi-threading (SMT)
23
//  - bus randomizer on exceptional conditions
24
//
25
// This source file is free software: you can redistribute it and/or modify 
26
// it under the terms of the GNU Lesser General Public License as published 
27
// by the Free Software Foundation, either version 3 of the License, or     
28
// (at your option) any later version.                                      
29
//                                                                          
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// This source file is distributed in the hope that it will be useful,      
31
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
32
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
33
// GNU General Public License for more details.                             
34
//                                                                          
35
// You should have received a copy of the GNU General Public License        
36
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
37
//
38
// Approx 41,000 LUTs. 66,000 LC's.
39
// ============================================================================
40
//
41
`include "FT64_config.vh"
42
`include "FT64_defines.vh"
43
 
44
module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, bok_i, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,
45 61 robfinch
    ol_o, pcr_o, pcr2_o, pkeys_o, icl_o, sr_o, cr_o, rbi_i, signal_i, exc_o);
46 60 robfinch
input [63:0] hartid;
47
input rst;
48
input clk_i;
49
input clk4x;
50
input tm_clk_i;
51
input [3:0] irq_i;
52
input [7:0] vec_i;
53
output reg [1:0] bte_o;
54
output reg [2:0] cti_o;
55
input bok_i;
56
output cyc_o;
57
output reg stb_o;
58
input ack_i;
59
input err_i;
60
output we_o;
61
output reg [7:0] sel_o;
62
output [`ABITS] adr_o;
63
output reg [63:0] dat_o;
64
input [63:0] dat_i;
65
output reg [1:0] ol_o;
66
output [31:0] pcr_o;
67
output [63:0] pcr2_o;
68
output [63:0] pkeys_o;
69 66 robfinch
output icl_o;
70 60 robfinch
output reg cr_o;
71
output reg sr_o;
72
input rbi_i;
73
input [31:0] signal_i;
74 61 robfinch
(* mark_debug="true" *)
75
output [7:0] exc_o;
76 60 robfinch
 
77
parameter TM_CLKFREQ = 20000000;
78
parameter QENTRIES = `QENTRIES;
79
parameter RSTPC = 64'hFFFFFFFFFFFC0100;
80
parameter BRKPC = 64'hFFFFFFFFFFFC0000;
81
`ifdef SUPPORT_SMT
82
parameter PREGS = 256;   // number of physical registers - 1
83
parameter AREGS = 256;   // number of architectural registers
84
`else
85
parameter PREGS = 128;
86
parameter AREGS = 128;
87
`endif
88
parameter RBIT = 11;
89
parameter DEBUG = 1'b0;
90
parameter NMAP = QENTRIES;
91
parameter BRANCH_PRED = 1'b0;
92
parameter SUP_TXE = 1'b0;
93
`ifdef SUPPORT_VECTOR
94
parameter SUP_VECTOR = 1'b1;
95
`else
96
parameter SUP_VECTOR = 1'b0;
97
`endif
98
parameter DBW = 64;
99
parameter ABW = 64;
100
parameter AMSB = ABW-1;
101
parameter NTHREAD = 1;
102
reg [7:0] i;
103
integer n;
104
integer j, k;
105
genvar g, h;
106
parameter TRUE = 1'b1;
107
parameter FALSE = 1'b0;
108
// Memory access sizes
109
parameter byt = 3'd0;
110
parameter wyde = 3'd1;
111
parameter tetra = 3'd2;
112
parameter octa = 3'd3;
113 61 robfinch
parameter hexi = 3'd4;
114 60 robfinch
// IQ states
115
parameter IQS_INVALID = 3'd0;
116
parameter IQS_QUEUED = 3'd1;
117
parameter IQS_OUT = 3'd2;
118
parameter IQS_AGEN = 3'd3;
119
parameter IQS_MEM = 3'd4;
120
parameter IQS_DONE = 3'd5;
121
parameter IQS_CMT = 3'd6;
122
 
123 66 robfinch
`include "..\common\FT64_busStates.vh"
124
 
125 60 robfinch
wire clk;
126
//BUFG uclkb1
127
//(
128
//      .I(clk_i),
129
//      .O(clk)
130
//);
131
assign clk = clk_i;
132
 
133
wire exv_i;
134
wire rdv_i;
135
wire wrv_i;
136
reg [ABW-1:0] vadr;
137
reg cyc;
138
reg we;
139
 
140
wire dc_ack;
141
wire acki = ack_i|dc_ack;
142 66 robfinch
wire tlb_miss;
143 60 robfinch
wire [RBIT:0] Ra0, Ra1, Ra2;
144
wire [RBIT:0] Rb0, Rb1, Rb2;
145
wire [RBIT:0] Rc0, Rc1, Rc2;
146
wire [RBIT:0] Rt0, Rt1, Rt2;
147
wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a,rfot0;
148
wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a,rfot1;
149
wire [63:0] rfoa2,rfob2,rfoc2,rfoc2a,rfot2;
150
`ifdef SUPPORT_SMT
151
wire [7:0] Ra0s = {Ra0[7:0]};
152
wire [7:0] Ra1s = {Ra1[7:0]};
153
wire [7:0] Ra2s = {Ra2[7:0]};
154
wire [7:0] Rb0s = {Rb0[7:0]};
155
wire [7:0] Rb1s = {Rb1[7:0]};
156
wire [7:0] Rb2s = {Rb2[7:0]};
157
wire [7:0] Rc0s = {Rc0[7:0]};
158
wire [7:0] Rc1s = {Rc1[7:0]};
159
wire [7:0] Rc2s = {Rc2[7:0]};
160
wire [7:0] Rt0s = {Rt0[7:0]};
161
wire [7:0] Rt1s = {Rt1[7:0]};
162
wire [7:0] Rt2s = {Rt2[7:0]};
163
`else
164
wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};
165
wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};
166
wire [6:0] Ra2s = {Ra2[7],Ra2[5:0]};
167
wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};
168
wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};
169
wire [6:0] Rb2s = {Rb2[7],Rb2[5:0]};
170
wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};
171
wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};
172
wire [6:0] Rc2s = {Rc2[7],Rc2[5:0]};
173
wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};
174
wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};
175
wire [6:0] Rt2s = {Rt2[7],Rt2[5:0]};
176
/*
177
wire [5:0] Ra0s = {Ra0[5:0]};
178
wire [5:0] Ra1s = {Ra1[5:0]};
179
wire [5:0] Rb0s = {Rb0[5:0]};
180
wire [5:0] Rb1s = {Rb1[5:0]};
181
wire [5:0] Rc0s = {Rc0[5:0]};
182
wire [5:0] Rc1s = {Rc1[5:0]};
183
wire [5:0] Rt0s = {Rt0[5:0]};
184
wire [5:0] Rt1s = {Rt1[5:0]};
185
*/
186
`endif
187
 
188
reg [63:0] wbrcd;
189
wire [5:0] brgs;
190
`ifdef SUPPORT_BBMS
191
reg [15:0] thrd_handle [0:63];
192
reg [63:0] prg_base [0:63];
193
reg [63:0] prg_limit [0:63];
194
reg [63:0] en_barrier [0:63];                                     // environment bound
195
reg [63:0] cl_barrier [0:63];
196
reg [63:0] cu_barrier [0:63];
197
reg [63:0] ro_barrier [0:63];
198
reg [63:0] dl_barrier [0:63];
199
reg [63:0] du_barrier [0:63];
200
reg [63:0] sl_barrier [0:63];
201
reg [63:0] su_barrier [0:63];
202
reg [7:0] env_priv [0:63];
203
reg [7:0] cod_priv [0:63];
204
reg [7:0] rdo_priv [0:63];
205
reg [7:0] dat_priv [0:63];
206
reg [7:0] stk_priv [0:63];
207
reg [15:0] th;
208
reg [63:0] pb;
209
reg [63:0] cbl;
210
reg [63:0] cbu;
211
reg [63:0] ro;
212
reg [63:0] dbl;
213
reg [63:0] dbu;
214
reg [63:0] sbl;
215
reg [63:0] sbu;
216
reg [63:0] en;
217
reg [7:0] env_pl;
218
reg [7:0] cod_pl;
219
reg [7:0] rdo_pl;
220
reg [7:0] dat_pl;
221
reg [7:0] stk_pl;
222
initial begin
223
        for (n = 0; n < 64; n = n + 1)
224
        begin
225
                thrd_handle[n] <= 1'd0;
226
                prg_base[n] <= 1'd0;
227
                cl_barrier[n] <= 1'd0;
228
                cu_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
229
                ro_barrier[n] <= 1'd0;
230
                dl_barrier[n] <= 1'd0;
231
                du_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
232
                sl_barrier[n] <= 1'd0;
233
                su_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
234
                env_priv[n] <= 8'h00;
235
                cod_priv[n] <= 8'h00;
236
                rdo_priv[n] <= 8'h00;
237
                dat_priv[n] <= 8'h00;
238
                stk_priv[n] <= 8'h00;
239
        end
240
end
241
always @(posedge clk_i)
242
begin
243
        th <= thrd_handle[brgs];
244
        pb <= prg_base[brgs];
245
        cbl <= cl_barrier[brgs];
246
        cbu <= cu_barrier[brgs];
247
        ro <= ro_barrier[brgs];
248
        dbl <= dl_barrier[brgs];
249
        dbu <= du_barrier[brgs];
250
        sbl <= sl_barrier[brgs];
251
        sbu <= su_barrier[brgs];
252
        en <= en_barrier[brgs];
253
        env_pl <= env_priv[brgs];
254
        cod_pl <= cod_priv[brgs];
255
        rdo_pl <= rdo_priv[brgs];
256
        dat_pl <= dat_priv[brgs];
257
        stk_pl <= stk_priv[brgs];
258
end
259
//wire [23:0] currentPrgSelector = prg_selector[brgs];
260
`else
261
wire [63:0] pb = 1'd0;
262
wire [63:0] cbl = 1'd0;
263
wire [63:0] cbu = 64'hFFFFFFFFFFFFFFFF;
264
wire [63:0] ro = 1'd0;
265
wire [63:0] dbl = 1'd0;
266
wire [63:0] dbu = 64'hFFFFFFFFFFFFFFFF;
267
wire [63:0] sbl = 1'd0;
268
wire [63:0] sbu = 64'hFFFFFFFFFFFFFFFF;
269
wire [63:0] en = 1'd0;
270
wire [7:0] env_pl = 8'h00;
271
wire [7:0] cod_pl = 8'h00;
272
wire [7:0] rdo_pl = 8'h00;
273
wire [7:0] dat_pl = 8'h00;
274
wire [7:0] stk_pl = 8'h00;
275
`endif
276
 
277
reg  [PREGS-1:0] rf_v;
278
reg  [`QBITSP1] rf_source[0:AREGS-1];
279
reg  [15:0] prf_v;
280
reg  [`QBITSP1] prf_source[0:15];
281
initial begin
282
for (n = 0; n < AREGS; n = n + 1)
283
        rf_source[n] = 1'b0;
284
for (n = 0; n < 16; n = n + 1)
285
        prf_source[n] <= 1'b0;
286
end
287 66 robfinch
`ifdef SUPPORT_SMT
288
wire [1:0] ol [0:NTHREAD];
289
wire [1:0] dl [0:NTHREAD];
290
`else
291
wire [1:0] ol;
292
wire [1:0] dl;
293
`endif
294 60 robfinch
wire [`ABITS] pc0a;
295
wire [`ABITS] pc1a;
296
wire [`ABITS] pc2a;
297
`ifdef SUPPORT_BBMS
298 66 robfinch
wire [`ABITS] pc0 = (pc0a[47:40]==8'hFF||ol[0]==2'b00) ? pc0a : {pb[50:0],13'd0} + pc0a[47:0];
299
wire [`ABITS] pc1 = (pc1a[47:40]==8'hFF||ol[1]==2'b00) ? pc1a : {pb[50:0],13'd0} + pc1a[47:0];
300
wire [`ABITS] pc2 = (pc2a[47:40]==8'hFF||ol[2]==2'b00) ? pc2a : {pb[50:0],13'd0} + pc2a[47:0];
301 60 robfinch
`else
302
wire [`ABITS] pc0 = pc0a;
303
wire [`ABITS] pc1 = pc1a;
304
wire [`ABITS] pc2 = pc2a;
305
`endif
306
 
307
reg excmiss;
308
reg [`ABITS] excmisspc;
309
reg excthrd;
310
reg exception_set;
311
reg rdvq;               // accumulated read violation
312
reg errq;               // accumulated err_i input status
313
reg exvq;
314
 
315
// Vector
316
reg [5:0] vqe0, vqe1, vqe2;   // vector element being queued
317
reg [5:0] vqet0, vqet1, vqet2;
318
reg [7:0] vl;           // vector length
319
reg [63:0] vm [0:7];    // vector mask registers
320
reg [1:0] m2;
321
 
322
reg [31:0] wb_merges;
323
// CSR's
324
reg [63:0] cr0;
325
wire snr = cr0[17];             // sequence number reset
326
wire dce = cr0[30];     // data cache enable
327
wire bpe = cr0[32];     // branch predictor enable
328
wire wbm = cr0[34];
329
wire sple = cr0[35];            // speculative load enable
330
wire ctgtxe = cr0[33];
331
wire pred_on = 1'b0;
332
reg [63:0] pmr;
333
wire id1_available = pmr[0];
334
wire id2_available = pmr[1];
335
wire id3_available = pmr[2];
336
wire alu0_available = pmr[8];
337
wire alu1_available = pmr[9];
338
wire fpu1_available = pmr[16];
339
wire fpu2_available = pmr[17];
340
wire mem1_available = pmr[24];
341
wire mem2_available = pmr[25];
342
wire mem3_available = pmr[26];
343
wire fcu_available = pmr[32];
344
// Simply setting this flag to zero should strip out almost all the logic
345
// associated SMT.
346
`ifdef SUPPORT_SMT
347
wire thread_en = cr0[16];
348
`else
349
wire thread_en = 1'b0;
350
`endif
351
wire vechain = cr0[18];
352 61 robfinch
// Performance CSR's
353 60 robfinch
reg [39:0] iq_ctr;
354
reg [39:0] irq_ctr;                                      // count of number of interrupts
355
reg [39:0] bm_ctr;                                       // branch miss counter
356 61 robfinch
reg [39:0] br_ctr;                                       // branch counter
357 60 robfinch
reg [39:0] icl_ctr;                                      // instruction cache load counter
358
 
359
reg [7:0] fcu_timeout;
360
reg [63:0] tick;
361
reg [63:0] wc_time;
362
reg [31:0] pcr;
363
reg [63:0] pcr2;
364
assign pcr_o = pcr;
365
assign pcr2_o = pcr2;
366
reg [63:0] aec;
367 61 robfinch
(* mark_debug = "true" *)
368 60 robfinch
reg [15:0] cause[0:15];
369
`ifdef SUPPORT_SMT
370 66 robfinch
reg [31:0] im_stack [0:NTHREAD];
371
wire [3:0] im = im_stack[0][3:0];
372
reg [15:0] ol_stack [0:NTHREAD];
373
reg [15:0] dl_stack [0:NTHREAD];
374
assign ol[0] = ol_stack[0][1:0];
375
assign ol[1] = ol_stack[1][1:0];
376
assign ol[2] = ol_stack[2][1:0];
377
assign dl[0] = dl_stack[0][1:0];
378
assign dl[1] = dl_stack[1][1:0];
379
assign dl[2] = dl_stack[2][1:0];
380 60 robfinch
reg [`ABITS] epc [0:NTHREAD];
381
reg [`ABITS] epc0 [0:NTHREAD];
382
reg [`ABITS] epc1 [0:NTHREAD];
383
reg [`ABITS] epc2 [0:NTHREAD];
384
reg [`ABITS] epc3 [0:NTHREAD];
385
reg [`ABITS] epc4 [0:NTHREAD];
386
reg [`ABITS] epc5 [0:NTHREAD];
387
reg [`ABITS] epc6 [0:NTHREAD];
388
reg [`ABITS] epc7 [0:NTHREAD];
389
reg [`ABITS] epc8 [0:NTHREAD];                   // exception pc and stack
390
reg [63:0] mstatus [0:NTHREAD];           // machine status
391
assign ol[0] = mstatus[0][5:4];   // operating level
392
assign dl[0] = mstatus[0][21:20];
393
wire [7:0] cpl [0:NTHREAD];
394
assign cpl[0] = mstatus[0][13:6]; // current privilege level
395
wire [5:0] rgs [0:NTHREAD];
396
assign ol[1] = mstatus[1][5:4]; // operating level
397
assign cpl[1] = mstatus[1][13:6];       // current privilege level
398
assign dl[1] = mstatus[1][21:20];
399
wire [7:0] ASID = mstatus[0][47:40];
400
reg [63:0] pl_stack [0:NTHREAD];
401
reg [63:0] rs_stack [0:NTHREAD];
402
reg [63:0] brs_stack [0:NTHREAD];
403
reg [63:0] fr_stack [0:NTHREAD];
404
assign rgs[0] = rs_stack[0][5:0];
405
assign rgs[1] = rs_stack[1][5:0];
406
wire mprv = mstatus[0][55];
407
wire [5:0] fprgs = mstatus[0][25:20];
408
//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];
409
wire vca = mstatus[0][32];               // vector chaining active
410
`else
411 66 robfinch
reg [31:0] im_stack = 32'hFFFFFFFF;
412
wire [3:0] im = im_stack[3:0];
413 60 robfinch
reg [`ABITS] epc ;
414
reg [`ABITS] epc0 ;
415
reg [`ABITS] epc1 ;
416
reg [`ABITS] epc2 ;
417
reg [`ABITS] epc3 ;
418
reg [`ABITS] epc4 ;
419
reg [`ABITS] epc5 ;
420
reg [`ABITS] epc6 ;
421
reg [`ABITS] epc7 ;
422
reg [`ABITS] epc8 ;                     // exception pc and stack
423
reg [63:0] mstatus ;             // machine status
424 66 robfinch
reg [15:0] ol_stack;
425
reg [15:0] dl_stack;
426
assign ol = ol_stack[1:0];       // operating level
427
assign dl = dl_stack[1:0];
428 60 robfinch
wire [7:0] cpl ;
429
assign cpl = mstatus[13:6];     // current privilege level
430
wire [5:0] rgs ;
431
reg [63:0] pl_stack ;
432
reg [63:0] rs_stack ;
433
reg [63:0] brs_stack ;
434
reg [63:0] fr_stack ;
435
assign rgs = rs_stack[5:0];
436
assign brgs = brs_stack[5:0];
437
wire mprv = mstatus[55];
438
wire [7:0] ASID = mstatus[47:40];
439
wire [5:0] fprgs = mstatus[25:20];
440
//assign ol_o = mprv ? ol_stack[2:0] : ol;
441
wire vca = mstatus[32];         // vector chaining active
442
`endif
443
reg [63:0] keys;
444
assign pkeys_o = keys;
445
reg [63:0] tcb;
446
reg [47:0] bad_instr[0:15];
447
reg [`ABITS] badaddr[0:15];
448
reg [`ABITS] tvec[0:7];
449
reg [63:0] sema;
450
reg [63:0] vm_sema;
451
reg [63:0] cas;         // compare and swap
452
reg [63:0] ve_hold;
453
reg isCAS, isAMO, isInc, isSpt, isRMW;
454
reg [`QBITS] casid;
455
reg [4:0] regLR = 5'd29;
456
 
457
 
458
reg [2:0] fp_rm;
459
reg fp_inexe;
460
reg fp_dbzxe;
461
reg fp_underxe;
462
reg fp_overxe;
463
reg fp_invopxe;
464
reg fp_giopxe;
465
reg fp_nsfp = 1'b0;
466
reg fp_fractie;
467
reg fp_raz;
468
 
469
reg fp_neg;
470
reg fp_pos;
471
reg fp_zero;
472
reg fp_inf;
473
 
474
reg fp_inex;            // inexact exception
475
reg fp_dbzx;            // divide by zero exception
476
reg fp_underx;          // underflow exception
477
reg fp_overx;           // overflow exception
478
reg fp_giopx;           // global invalid operation exception
479
reg fp_sx;                      // summary exception
480
reg fp_swtx;        // software triggered exception
481
reg fp_gx;
482
reg fp_invopx;
483
 
484
reg fp_infzerox;
485
reg fp_zerozerox;
486
reg fp_subinfx;
487
reg fp_infdivx;
488
reg fp_NaNCmpx;
489
reg fp_cvtx;
490
reg fp_sqrtx;
491
reg fp_snanx;
492
 
493
wire [31:0] fp_status = {
494
 
495
        fp_rm,
496
        fp_inexe,
497
        fp_dbzxe,
498
        fp_underxe,
499
        fp_overxe,
500
        fp_invopxe,
501
        fp_nsfp,
502
 
503
        fp_fractie,
504
        fp_raz,
505
        1'b0,
506
        fp_neg,
507
        fp_pos,
508
        fp_zero,
509
        fp_inf,
510
 
511
        fp_swtx,
512
        fp_inex,
513
        fp_dbzx,
514
        fp_underx,
515
        fp_overx,
516
        fp_giopx,
517
        fp_gx,
518
        fp_sx,
519
 
520
        fp_cvtx,
521
        fp_sqrtx,
522
        fp_NaNCmpx,
523
        fp_infzerox,
524
        fp_zerozerox,
525
        fp_infdivx,
526
        fp_subinfx,
527
        fp_snanx
528
        };
529
 
530
reg [63:0] fpu_csr;
531
wire [5:0] fp_rgs = fpu_csr[37:32];
532
 
533
//reg [25:0] m[0:8191];
534
reg  [3:0] panic;                // indexes the message structure
535
reg [128:0] message [0:15];       // indexed by panic
536
 
537
wire int_commit;
538
reg StatusHWI;
539
(* mark_debug = "true" *)
540
reg [55:0] insn0, insn1, insn2;
541
wire [55:0] insn0a, insn1b, insn2b;
542
reg [55:0] insn1a, insn2a;
543
// Only need enough bits in the seqnence number to cover the instructions in
544
// the queue plus an extra count for skipping on branch misses. In this case
545
// that would be four bits minimum (count 0 to 8). 
546
wire [63:0] rdat0,rdat1,rdat2;
547 61 robfinch
reg [127:0] xdati;
548 60 robfinch
 
549
reg canq1, canq2, canq3;
550
(* mark_debug = "true" *)
551
reg queued1;
552
reg queued2;
553
reg queued3;
554
(* mark_debug = "true" *)
555
reg queuedNop;
556
 
557
reg [47:0] codebuf[0:63];
558
reg [QENTRIES-1:0] setpred;
559
 
560
// instruction queue (ROB)
561
// State and stqte decodes
562
reg [2:0] iqentry_state [0:QENTRIES-1];
563
reg [QENTRIES-1:0] iqentry_v;                    // entry valid?  -- this should be the first bit
564
reg [QENTRIES-1:0] iqentry_done;
565
reg [QENTRIES-1:0] iqentry_out;
566
reg [QENTRIES-1:0] iqentry_agen;
567
reg [`SNBITS] iqentry_sn [0:QENTRIES-1];  // instruction sequence number
568
reg [QENTRIES-1:0] iqentry_iv;           // instruction is valid
569
reg [`QBITSP1] iqentry_is [0:QENTRIES-1];        // source of instruction
570
reg [QENTRIES-1:0] iqentry_thrd;         // which thread the instruction is in
571
reg [QENTRIES-1:0] iqentry_pt;           // predict taken
572
reg [QENTRIES-1:0] iqentry_bt;           // update branch target buffer
573
reg [QENTRIES-1:0] iqentry_takb; // take branch record
574
reg [QENTRIES-1:0] iqentry_jal;
575
reg [2:0] iqentry_sz [0:QENTRIES-1];
576
reg [QENTRIES-1:0] iqentry_alu = 8'h00;  // alu type instruction
577
reg [QENTRIES-1:0] iqentry_alu0;  // only valid on alu #0
578
reg [QENTRIES-1:0] iqentry_fpu;  // floating point instruction
579
reg [QENTRIES-1:0] iqentry_fc;   // flow control instruction
580
reg [QENTRIES-1:0] iqentry_canex = 8'h00;        // true if it's an instruction that can exception
581
reg [QENTRIES-1:0] iqentry_oddball = 8'h00;      // writes to register file
582
reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction
583
reg [QENTRIES-1:0] iqentry_loadv;        // is a volatile memory load instruction
584 61 robfinch
reg [QENTRIES-1:0] iqentry_loadseg;
585 60 robfinch
reg [QENTRIES-1:0] iqentry_store;        // is a memory store instruction
586
reg [QENTRIES-1:0] iqentry_preload;      // is a memory preload instruction
587
reg [QENTRIES-1:0] iqentry_ldcmp;
588
reg [QENTRIES-1:0] iqentry_mem;  // touches memory: 1 if LW/SW
589
reg [QENTRIES-1:0] iqentry_memndx;  // indexed memory operation 
590
reg [2:0] iqentry_memsz [0:QENTRIES-1];   // size of memory op
591
reg [QENTRIES-1:0] iqentry_rmw;  // memory RMW op
592
reg [QENTRIES-1:0] iqentry_push;
593
reg [QENTRIES-1:0] iqentry_memdb;
594
reg [QENTRIES-1:0] iqentry_memsb;
595
reg [QENTRIES-1:0] iqentry_rtop;
596
reg [QENTRIES-1:0] iqentry_sei;
597
reg [QENTRIES-1:0] iqentry_aq;   // memory aquire
598
reg [QENTRIES-1:0] iqentry_rl;   // memory release
599
reg [QENTRIES-1:0] iqentry_shft;
600
reg [QENTRIES-1:0] iqentry_jmp;  // changes control flow: 1 if BEQ/JALR
601
reg [QENTRIES-1:0] iqentry_br;  // Bcc (for predictor)
602
reg [QENTRIES-1:0] iqentry_ret;
603
reg [QENTRIES-1:0] iqentry_irq;
604
reg [QENTRIES-1:0] iqentry_brk;
605
reg [QENTRIES-1:0] iqentry_rti;
606
reg [QENTRIES-1:0] iqentry_sync;  // sync instruction
607
reg [QENTRIES-1:0] iqentry_fsync;
608
reg [QENTRIES-1:0] iqentry_tlb;
609
reg [QENTRIES-1:0] iqentry_cmp;
610
reg [QENTRIES-1:0] iqentry_rfw = 1'b0;   // writes to register file
611
reg [QENTRIES-1:0] iqentry_prfw = 1'b0;
612
reg  [7:0] iqentry_we   [0:QENTRIES-1];   // enable strobe
613
reg [63:0] iqentry_res   [0:QENTRIES-1];  // instruction result
614 61 robfinch
reg [63:0] iqentry_seg_base      [0:QENTRIES-1];  //
615
reg [63:0] iqentry_seg_lb        [0:QENTRIES-1];  //
616
reg [63:0] iqentry_seg_ub        [0:QENTRIES-1];  //
617
reg [63:0] iqentry_seg_acr       [0:QENTRIES-1];  //
618 60 robfinch
reg [63:0] iqentry_ares  [0:QENTRIES-1];  // alternate instruction result
619
reg [47:0] iqentry_instr[0:QENTRIES-1];   // instruction opcode
620
reg  [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length
621
reg  [7:0] iqentry_exc   [0:QENTRIES-1];  // only for branches ... indicates a HALT instruction
622
reg [RBIT:0] iqentry_tgt[0:QENTRIES-1];   // Rt field or ZERO -- this is the instruction's target (if any)
623
reg  [7:0] iqentry_vl   [0:QENTRIES-1];
624
reg  [5:0] iqentry_ven  [0:QENTRIES-1];  // vector element number
625
reg [AMSB:0] iqentry_ma [0:QENTRIES-1];   // memory address
626
reg [63:0] iqentry_a0    [0:QENTRIES-1];  // argument 0 (immediate)
627
reg [63:0] iqentry_a1    [0:QENTRIES-1];  // argument 1
628
reg [QENTRIES-1:0] iqentry_a1_v; // arg1 valid
629
reg [`QBITSP1] iqentry_a1_s     [0:QENTRIES-1];  // arg1 source (iq entry # with top bit representing ALU/DRAM bus)
630
reg [63:0] iqentry_a2    [0:QENTRIES-1];  // argument 2
631
reg        iqentry_a2_v [0:QENTRIES-1];  // arg2 valid
632
reg  [`QBITSP1] iqentry_a2_s    [0:QENTRIES-1];  // arg2 source (iq entry # with top bit representing ALU/DRAM bus)
633
reg [63:0] iqentry_a3    [0:QENTRIES-1];  // argument 3
634
reg        iqentry_a3_v [0:QENTRIES-1];  // arg3 valid
635
reg  [`QBITSP1] iqentry_a3_s    [0:QENTRIES-1];  // arg3 source (iq entry # with top bit representing ALU/DRAM bus)
636
reg [`ABITS] iqentry_pc [0:QENTRIES-1];  // program counter for this instruction
637
reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];
638
reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];
639
reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];
640
 
641
// debugging
642
//reg  [4:0] iqentry_ra   [0:7];  // Ra
643
initial begin
644
for (n = 0; n < QENTRIES; n = n + 1)
645
        iqentry_a1_s[n] <= 5'd0;
646
        iqentry_a2_s[n] <= 5'd0;
647
        iqentry_a3_s[n] <= 5'd0;
648
end
649
 
650
reg [QENTRIES-1:0] iqentry_source = {QENTRIES{1'b0}};
651
reg [QENTRIES-1:0] iqentry_imm;
652
reg [QENTRIES-1:0] iqentry_memready;
653
reg [QENTRIES-1:0] iqentry_memopsvalid;
654
 
655
reg  [QENTRIES-1:0] memissue = {QENTRIES{1'b0}};
656
reg [1:0] missued;
657
reg [7:0] last_issue0, last_issue1, last_issue2;
658
reg  [QENTRIES-1:0] iqentry_memissue;
659
reg [QENTRIES-1:0] iqentry_stomp;
660
reg [3:0] stompedOnRets;
661
reg  [QENTRIES-1:0] iqentry_alu0_issue;
662
reg  [QENTRIES-1:0] iqentry_alu1_issue;
663
reg  [QENTRIES-1:0] iqentry_alu2_issue;
664
reg  [QENTRIES-1:0] iqentry_id1issue;
665
reg  [QENTRIES-1:0] iqentry_id2issue;
666
reg  [QENTRIES-1:0] iqentry_id3issue;
667
reg [1:0] iqentry_mem_islot [0:QENTRIES-1];
668
reg [QENTRIES-1:0] iqentry_fcu_issue;
669
reg [QENTRIES-1:0] iqentry_fpu1_issue;
670
reg [QENTRIES-1:0] iqentry_fpu2_issue;
671
 
672
reg [PREGS-1:1] livetarget;
673
reg [PREGS-1:1] iqentry_livetarget [0:QENTRIES-1];
674
reg [PREGS-1:1] iqentry_latestID [0:QENTRIES-1];
675
reg [PREGS-1:1] iqentry_cumulative [0:QENTRIES-1];
676
wire  [PREGS-1:1] iq_out [0:QENTRIES-1];
677
 
678
reg  [`QBITS] tail0;
679
reg  [`QBITS] tail1;
680
reg  [`QBITS] tail2;
681
reg  [`QBITS] heads[0:QENTRIES-1];
682
 
683
// To detect a head change at time of commit. Some values need to pulsed
684
// with a single pulse.
685
reg  [`QBITS] ohead[0:2];
686
reg ocommit0_v, ocommit1_v, ocommit2_v;
687
reg [11:0] cmt_timer;
688
 
689
wire take_branch0;
690
wire take_branch1;
691
 
692
reg [3:0] nop_fetchbuf;
693
wire        fetchbuf;   // determines which pair to read from & write to
694
wire [3:0] fb_panic;
695
 
696
wire [47:0] fetchbuf0_instr;
697
wire  [2:0] fetchbuf0_insln;
698
wire [`ABITS] fetchbuf0_pc;
699
(* mark_debug = "true" *)
700
wire        fetchbuf0_v;
701
wire            fetchbuf0_thrd;
702
wire            fetchbuf0_mem;
703
wire        fetchbuf0_rfw;
704
wire [47:0] fetchbuf1_instr;
705
wire  [2:0] fetchbuf1_insln;
706
wire [`ABITS] fetchbuf1_pc;
707
wire        fetchbuf1_v;
708
wire            fetchbuf1_thrd;
709
wire            fetchbuf1_mem;
710
wire        fetchbuf1_rfw;
711
wire [47:0] fetchbuf2_instr;
712
wire  [2:0] fetchbuf2_insln;
713
wire [`ABITS] fetchbuf2_pc;
714
wire        fetchbuf2_v;
715
wire            fetchbuf2_thrd;
716
wire            fetchbuf2_mem;
717
wire        fetchbuf2_rfw;
718
wire [47:0] fetchbufA_instr;
719
wire [`ABITS] fetchbufA_pc;
720
wire        fetchbufA_v;
721
wire [47:0] fetchbufB_instr;
722
wire [`ABITS] fetchbufB_pc;
723
wire        fetchbufB_v;
724
wire [47:0] fetchbufC_instr;
725
wire [`ABITS] fetchbufC_pc;
726
wire        fetchbufC_v;
727
wire [47:0] fetchbufD_instr;
728
wire [`ABITS] fetchbufD_pc;
729
wire        fetchbufD_v;
730
wire [47:0] fetchbufE_instr;
731
wire [`ABITS] fetchbufE_pc;
732
wire        fetchbufE_v;
733
wire [47:0] fetchbufF_instr;
734
wire [`ABITS] fetchbufF_pc;
735
wire        fetchbufF_v;
736
 
737
//reg        did_branchback0;
738
//reg        did_branchback1;
739
 
740
reg         id1_v;
741
reg   [`QBITSP1] id1_id;
742
reg  [47:0] id1_instr;
743
reg   [5:0] id1_ven;
744
reg   [7:0] id1_vl;
745
reg         id1_thrd;
746
reg         id1_pt;
747
reg   [4:0] id1_Rt;
748
wire [143:0] id1_bus;
749
 
750
reg         id2_v;
751
reg   [`QBITSP1] id2_id;
752
reg  [47:0] id2_instr;
753
reg   [5:0] id2_ven;
754
reg   [7:0] id2_vl;
755
reg         id2_thrd;
756
reg         id2_pt;
757
reg   [4:0] id2_Rt;
758
wire [143:0] id2_bus;
759
 
760
reg         id3_v;
761
reg   [`QBITSP1] id3_id;
762
reg  [47:0] id3_instr;
763
reg   [5:0] id3_ven;
764
reg   [7:0] id3_vl;
765
reg         id3_thrd;
766
reg         id3_pt;
767
reg   [4:0] id3_Rt;
768
wire [143:0] id3_bus;
769
 
770
reg [63:0] alu0_xs = 64'd0;
771
reg [63:0] alu1_xs = 64'd0;
772
 
773
reg [3:0]  alu0_pred;
774
reg                             alu0_cmt;
775
wire                            alu0_abort;
776
reg        alu0_ld;
777
reg        alu0_dataready;
778
wire       alu0_done;
779
wire       alu0_idle;
780
reg  [`QBITSP1] alu0_sourceid;
781
reg [47:0] alu0_instr;
782
reg                              alu0_tlb;
783
reg        alu0_mem;
784
reg        alu0_load;
785
reg        alu0_store;
786
reg                      alu0_push;
787
reg        alu0_shft;
788
reg [RBIT:0] alu0_Ra;
789
reg [63:0] alu0_argA;
790
reg [63:0] alu0_argB;
791
reg [63:0] alu0_argC;
792
reg [63:0] alu0_argT;
793
reg [63:0] alu0_argI;    // only used by BEQ
794
reg [2:0]  alu0_sz;
795
reg [RBIT:0] alu0_tgt;
796
reg [5:0]  alu0_ven;
797
reg        alu0_thrd;
798
reg [`ABITS] alu0_pc;
799
reg [63:0] alu0_bus;
800
wire [63:0] alu0b_bus;
801
wire [63:0] alu0_out;
802
wire  [`QBITSP1] alu0_id;
803 66 robfinch
(* mark_debug="true" *)
804 60 robfinch
wire  [`XBITS] alu0_exc;
805
wire        alu0_v;
806
wire        alu0_branchmiss;
807
wire [`ABITS] alu0_misspc;
808
 
809
reg [3:0]  alu1_pred;
810
reg                             alu1_cmt;
811
wire                            alu1_abort;
812
reg        alu1_ld;
813
reg        alu1_dataready;
814
wire       alu1_done;
815
wire       alu1_idle;
816
reg  [`QBITSP1] alu1_sourceid;
817
reg [47:0] alu1_instr;
818
reg        alu1_mem;
819
reg        alu1_load;
820
reg        alu1_store;
821
reg                      alu1_push;
822
reg        alu1_shft;
823
reg [RBIT:0] alu1_Ra;
824
reg [63:0] alu1_argA;
825
reg [63:0] alu1_argB;
826
reg [63:0] alu1_argC;
827
reg [63:0] alu1_argT;
828
reg [63:0] alu1_argI;    // only used by BEQ
829
reg [2:0]  alu1_sz;
830
reg [RBIT:0] alu1_tgt;
831
reg [5:0]  alu1_ven;
832
reg [`ABITS] alu1_pc;
833
reg        alu1_thrd;
834
reg [63:0] alu1_bus;
835
wire [63:0] alu1b_bus;
836
wire [63:0] alu1_out;
837
wire  [`QBITSP1] alu1_id;
838
wire  [`XBITS] alu1_exc;
839
wire        alu1_v;
840
wire        alu1_branchmiss;
841
wire [`ABITS] alu1_misspc;
842
 
843
wire [`XBITS] fpu_exc;
844
reg [3:0] fpu1_pred;
845
reg                             fpu1_cmt;
846
reg        fpu1_ld;
847
reg        fpu1_dataready = 1'b1;
848
wire       fpu1_done = 1'b1;
849
wire       fpu1_idle;
850
reg [`QBITSP1] fpu1_sourceid;
851
reg [47:0] fpu1_instr;
852
reg [63:0] fpu1_argA;
853
reg [63:0] fpu1_argB;
854
reg [63:0] fpu1_argC;
855
reg [63:0] fpu1_argT;
856
reg [63:0] fpu1_argI;    // only used by BEQ
857
reg [RBIT:0] fpu1_tgt;
858
reg [`ABITS] fpu1_pc;
859
wire [63:0] fpu1_out = 64'h0;
860
reg [63:0] fpu1_bus = 64'h0;
861
wire  [`QBITSP1] fpu1_id;
862
wire  [`XBITS] fpu1_exc = 9'h000;
863
wire        fpu1_v;
864
wire [31:0] fpu1_status;
865
 
866
reg [3:0] fpu2_pred;
867
reg                             fpu2_cmt;
868
reg        fpu2_ld;
869
reg        fpu2_dataready = 1'b1;
870
wire       fpu2_done = 1'b1;
871
wire       fpu2_idle;
872
reg [`QBITSP1] fpu2_sourceid;
873
reg [47:0] fpu2_instr;
874
reg [63:0] fpu2_argA;
875
reg [63:0] fpu2_argB;
876
reg [63:0] fpu2_argC;
877
reg [63:0] fpu2_argT;
878
reg [63:0] fpu2_argI;    // only used by BEQ
879
reg [RBIT:0] fpu2_tgt;
880
reg [`ABITS] fpu2_pc;
881
wire [63:0] fpu2_out = 64'h0;
882
reg [63:0] fpu2_bus = 64'h0;
883
wire  [`QBITSP1] fpu2_id;
884
wire  [`XBITS] fpu2_exc = 9'h000;
885
wire        fpu2_v;
886
wire [31:0] fpu2_status;
887
 
888
reg [7:0] fccnt;
889
reg [47:0] waitctr;
890
reg [3:0] fcu_pred;
891
reg                             fcu_cmt;
892
reg        fcu_ld;
893
reg        fcu_dataready;
894
reg        fcu_done;
895
reg         fcu_idle = 1'b1;
896
reg [`QBITSP1] fcu_sourceid;
897
reg [47:0] fcu_instr;
898
reg [47:0] fcu_prevInstr;
899
reg  [2:0] fcu_insln;
900
reg        fcu_pt;                      // predict taken
901
reg        fcu_branch;
902
reg        fcu_call;
903
reg        fcu_ret;
904
reg        fcu_jal;
905
reg        fcu_brk;
906
reg        fcu_rti;
907
reg [63:0] fcu_argA;
908
reg [63:0] fcu_argB;
909
reg [63:0] fcu_argC;
910
reg [63:0] fcu_argI;     // only used by BEQ
911
reg [63:0] fcu_argT;
912
reg [63:0] fcu_argT2;
913 61 robfinch
reg [63:0] fcu_epc;
914
reg [23:0] fcu_ecs;              // excepted code segment
915
reg [23:0] fcu_rs;               // return selector
916 60 robfinch
reg [`ABITS] fcu_pc;
917
reg [`ABITS] fcu_nextpc;
918
reg [`ABITS] fcu_brdisp;
919
wire [63:0] fcu_out;
920
reg [63:0] fcu_bus;
921
wire  [`QBITSP1] fcu_id;
922
reg   [`XBITS] fcu_exc;
923
wire        fcu_v;
924
reg        fcu_thrd;
925
reg        fcu_branchmiss;
926
reg  fcu_clearbm;
927
reg [`ABITS] fcu_misspc;
928
 
929
reg [63:0] rmw_argA;
930
reg [63:0] rmw_argB;
931
reg [63:0] rmw_argC;
932
wire [63:0] rmw_res;
933
reg [47:0] rmw_instr;
934
 
935
// write buffer
936
reg [63:0] wb_data [0:`WB_DEPTH-1];
937
reg [`ABITS] wb_addr [0:`WB_DEPTH-1];
938
reg [1:0] wb_ol [0:`WB_DEPTH-1];
939
reg [`WB_DEPTH-1:0] wb_v;
940
reg [`WB_DEPTH-1:0] wb_rmw;
941
reg [QENTRIES-1:0] wb_id [0:`WB_DEPTH-1];
942
reg [QENTRIES-1:0] wbo_id;
943
reg [7:0] wb_sel [0:`WB_DEPTH-1];
944
reg wb_en;
945
reg wb_shift;
946
 
947
reg branchmiss = 1'b0;
948
reg branchmiss_thrd = 1'b0;
949
reg [`ABITS] misspc;
950
reg  [`QBITS] missid;
951
 
952
wire take_branch;
953
wire take_branchA;
954
wire take_branchB;
955
wire take_branchC;
956
wire take_branchD;
957
 
958
wire        dram_avail;
959
reg      [2:0] dram0;    // state of the DRAM request (latency = 4; can have three in pipeline)
960
reg      [2:0] dram1;    // state of the DRAM request (latency = 4; can have three in pipeline)
961
reg      [2:0] dram2;    // state of the DRAM request (latency = 4; can have three in pipeline)
962
reg [63:0] dram0_data;
963
reg [`ABITS] dram0_addr;
964
reg [47:0] dram0_instr;
965
reg        dram0_rmw;
966
reg                dram0_preload;
967
reg [RBIT:0] dram0_tgt;
968
reg  [`QBITSP1] dram0_id;
969
reg        dram0_unc;
970
reg [2:0]  dram0_memsize;
971
reg        dram0_load;  // is a load operation
972 61 robfinch
reg                      dram0_loadseg;
973 60 robfinch
reg        dram0_store;
974
reg  [1:0] dram0_ol;
975
reg [63:0] dram1_data;
976
reg [`ABITS] dram1_addr;
977
reg [47:0] dram1_instr;
978
reg        dram1_rmw;
979
reg                dram1_preload;
980
reg [RBIT:0] dram1_tgt;
981
reg  [`QBITSP1] dram1_id;
982
reg        dram1_unc;
983
reg [2:0]  dram1_memsize;
984
reg        dram1_load;
985 61 robfinch
reg                      dram1_loadseg;
986 60 robfinch
reg        dram1_store;
987
reg  [1:0] dram1_ol;
988
reg [63:0] dram2_data;
989
reg [`ABITS] dram2_addr;
990
reg [47:0] dram2_instr;
991
reg        dram2_rmw;
992
reg                dram2_preload;
993
reg [RBIT:0] dram2_tgt;
994
reg  [`QBITSP1] dram2_id;
995
reg        dram2_unc;
996
reg [2:0]  dram2_memsize;
997
reg        dram2_load;
998 61 robfinch
reg                      dram2_loadseg;
999 60 robfinch
reg        dram2_store;
1000
reg  [1:0] dram2_ol;
1001
 
1002
reg        dramA_v;
1003
reg  [`QBITSP1] dramA_id;
1004
reg [63:0] dramA_bus;
1005
reg        dramB_v;
1006
reg  [`QBITSP1] dramB_id;
1007
reg [63:0] dramB_bus;
1008
reg        dramC_v;
1009
reg  [`QBITSP1] dramC_id;
1010
reg [63:0] dramC_bus;
1011
 
1012
wire        outstanding_stores;
1013
reg [63:0] I;            // instruction count
1014
reg [63:0] CC;   // commit count
1015
 
1016
reg        commit0_v;
1017
reg  [`QBITSP1] commit0_id;
1018
reg [RBIT:0] commit0_tgt;
1019
reg  [7:0] commit0_we = 8'h00;
1020
reg [63:0] commit0_bus;
1021
reg        commit1_v;
1022
reg  [`QBITSP1] commit1_id;
1023
reg [RBIT:0] commit1_tgt;
1024
reg  [7:0] commit1_we = 8'h00;
1025
reg [63:0] commit1_bus;
1026
reg        commit2_v;
1027
reg  [`QBITSP1] commit2_id;
1028
reg [RBIT:0] commit2_tgt;
1029
reg  [7:0] commit2_we = 8'h00;
1030
reg [63:0] commit2_bus;
1031
 
1032
reg StoreAck1;
1033 66 robfinch
reg [4:0] bstate = BIDLE;
1034
wire [3:0] icstate;
1035 61 robfinch
parameter SEG_IDLE = 2'd0;
1036
parameter SEG_CHK = 2'd1;
1037
parameter SEG_UPD = 2'd2;
1038
parameter SEG_DONE = 2'd3;
1039 60 robfinch
reg [1:0] bwhich;
1040
reg invic, invdc;
1041 66 robfinch
reg invicl;
1042
wire [1:0] icwhich;
1043
wire icnxt;
1044
wire L2_nxt;
1045 60 robfinch
wire ihit0,ihit1,ihit2,ihitL2;
1046
wire ihit = ihit0&ihit1&ihit2;
1047
reg phit;
1048
wire threadx;
1049
always @*
1050 66 robfinch
        phit <= (ihit&&icstate==IDLE) && !invicl;
1051 61 robfinch
(* mark_debug="true" *)
1052
reg icack;
1053 66 robfinch
wire L1_wr0,L1_wr1,L1_wr2;
1054
wire L1_invline;
1055 60 robfinch
wire [1:0] ic0_fault,ic1_fault,ic2_fault;
1056 66 robfinch
wire [9:0] L1_en;
1057
wire [71:0] L1_adr;
1058
wire [71:0] L2_adr;
1059 61 robfinch
wire [305:0] L2_dato;
1060 66 robfinch
wire selL2;
1061 60 robfinch
 
1062 66 robfinch
wire icclk;
1063
BUFH ucb1 (.I(clk), .O(icclk));
1064
 
1065 60 robfinch
generate begin : gRegfileInst
1066
if (`WAYS > 2) begin : gb1
1067
FT64_regfile2w9r_oc #(.RBIT(RBIT)) urf1
1068
(
1069
  .clk(clk),
1070
  .clk4x(clk4x),
1071
  .wr0(commit0_v),
1072
  .wr1(commit1_v),
1073
  .we0(commit0_we),
1074
  .we1(commit1_we),
1075
  .wa0(commit0_tgt),
1076
  .wa1(commit1_tgt),
1077
  .i0(commit0_bus),
1078
  .i1(commit1_bus),
1079
        .rclk(~clk),
1080
        .ra0(Ra0),
1081
        .ra1(Rb0),
1082
        .ra2(Rc0),
1083
        .o0(rfoa0),
1084
        .o1(rfob0),
1085
        .o2(rfoc0a),
1086
        .ra3(Ra1),
1087
        .ra4(Rb1),
1088
        .ra5(Rc1),
1089
        .o3(rfoa1),
1090
        .o4(rfob1),
1091
        .o5(rfoc1a),
1092
        .ra6(Ra2),
1093
        .ra7(Rb2),
1094
        .ra8(Rc2),
1095
        .o6(rfoa2),
1096
        .o7(rfob2),
1097
        .o8(rfoc2a)
1098
);
1099
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
1100
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
1101
assign rfoc2 = Rc2[11:6]==6'h3F ? vm[Rc2[2:0]] : rfoc2a;
1102
end
1103
else if (`WAYS > 1) begin : gb1
1104
FT64_regfile2w6r_oc #(.RBIT(RBIT)) urf1
1105
(
1106
  .clk(clk),
1107
  .clk4x(clk4x),
1108
  .wr0(commit0_v),
1109
  .wr1(commit1_v),
1110
  .we0(commit0_we),
1111
  .we1(commit1_we),
1112
  .wa0(commit0_tgt),
1113
  .wa1(commit1_tgt),
1114
  .i0(commit0_bus),
1115
  .i1(commit1_bus),
1116
        .rclk(~clk),
1117
        .ra0(Ra0),
1118
        .ra1(Rb0),
1119
        .ra2(Rc0),
1120
        .o0(rfoa0),
1121
        .o1(rfob0),
1122
        .o2(rfoc0a),
1123
        .ra3(Ra1),
1124
        .ra4(Rb1),
1125
        .ra5(Rc1),
1126
        .o3(rfoa1),
1127
        .o4(rfob1),
1128
        .o5(rfoc1a)
1129
);
1130
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
1131
assign rfoc1 = Rc1[11:6]==6'h3F ? vm[Rc1[2:0]] : rfoc1a;
1132
end
1133
else begin : gb1
1134
FT64_regfile1w4r_oc #(.RBIT(RBIT)) urf1
1135
(
1136
  .clk(clk),
1137
  .wr0(commit0_v),
1138
  .wa0(commit0_tgt),
1139
  .we0(8'hFF),
1140
  .i0(commit0_bus),
1141
  .rclk(~clk),
1142
        .ra0(Ra0),
1143
        .ra1(Rb0),
1144
        .ra2(Rc0),
1145
        .ra3(Rt0),
1146
        .o0(rfoa0),
1147
        .o1(rfob0),
1148
        .o2(rfoc0a),
1149
        .o3(rfot0)
1150
);
1151
end
1152
assign rfoc0 = Rc0[11:6]==6'h3F ? vm[Rc0[2:0]] : rfoc0a;
1153
end
1154
endgenerate
1155
 
1156
function [3:0] fnInsLength;
1157
input [47:0] ins;
1158
`ifdef SUPPORT_DCI
1159
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
1160
        fnInsLength = 4'd2 | pred_on;
1161
else
1162
`endif
1163
        case(ins[7:6])
1164
        2'd0:   fnInsLength = 4'd4 | pred_on;
1165
        2'd1:   fnInsLength = 4'd6 | pred_on;
1166
        default:        fnInsLength = 4'd2 | pred_on;
1167
        endcase
1168
endfunction
1169
 
1170
generate begin : gInsnVar
1171
        if (`WAYS > 1) begin
1172
                always @*
1173
                        if (thread_en)
1174
                                insn1a <= insn1b;
1175
                        else
1176
                                insn1a <= {insn1b,insn0a} >> {fnInsLength(insn0a),3'b0};
1177
        end
1178
        if (`WAYS > 2) begin
1179
                always @*
1180
                        if (thread_en)
1181
                                insn2a <= insn2b;
1182
                        else
1183
                                insn2a <= {insn2b,insn1b,insn0a} >> {fnInsLength(insn0a) + fnInsLength(insn1a),3'b0};
1184
        end
1185
end
1186
endgenerate
1187
 
1188 66 robfinch
wire L1_selpc;
1189
wire [2:0] icti;
1190
wire [1:0] ibte;
1191
wire icyc;
1192
wire istb;
1193
wire [7:0] isel;
1194
wire [71:0] iadr;
1195
wire L2_ld;
1196
wire [305:0] L1_dat;
1197
wire [2:0] L2_cnt;
1198
reg [71:0] invlineAddr;
1199
 
1200
FT64_ICController uL1ctrl
1201
(
1202
        .clk_i(clk),
1203
        .asid(ASID),
1204
        .pc0(pc0),
1205
        .pc1(pc1),
1206
        .pc2(pc2),
1207
        .hit0(ihit0),
1208
        .hit1(ihit1),
1209
        .hit2(ihit2),
1210
        .bstate(bstate),
1211
        .state(icstate),
1212
        .invline(invicl),
1213
        .invlineAddr(invlineAddr),
1214
        .thread_en(thread_en),
1215
        .L1_selpc(L1_selpc),
1216
        .L1_adr(L1_adr),
1217
        .L1_dat(L1_dat),
1218
        .L1_wr0(L1_wr0),
1219
        .L1_wr1(L1_wr1),
1220
        .L1_wr2(L1_wr2),
1221
        .L1_en(L1_en),
1222
        .L1_invline(L1_invline),
1223
        .ihitL2(ihitL2),
1224
        .selL2(selL2),
1225
        .L2_ld(L2_ld),
1226
        .L2_cnt(L2_cnt),
1227
        .L2_adr(L2_adr),
1228
        .L2_dato(L2_dato),
1229
        .L2_nxt(L2_nxt),
1230
        .icnxt(icnxt),
1231
        .icwhich(icwhich),
1232
        .icl_o(icl_o),
1233
        .cti_o(icti),
1234
        .bte_o(ibte),
1235
        .bok_i(bok_i),
1236
        .cyc_o(icyc),
1237
        .stb_o(istb),
1238
        .ack_i(acki),
1239
        .err_i(err_i),
1240
        .tlbmiss_i(tlb_miss),
1241
        .exv_i(exv_i),
1242
        .sel_o(isel),
1243
        .adr_o(iadr),
1244
        .dat_i(dat_i)
1245
);
1246
 
1247 60 robfinch
FT64_L1_icache #(.pSize(`L1_ICACHE_SIZE)) uic0
1248
(
1249
  .rst(rst),
1250
  .clk(clk),
1251
  .nxt(icnxt),
1252
  .wr(L1_wr0),
1253
  .wr_ack(),
1254
  .en(L1_en),
1255 66 robfinch
  .adr(L1_selpc ? {ASID,pc0} : L1_adr),
1256 60 robfinch
  .wadr(L1_adr),
1257 66 robfinch
  .i(L1_dat),
1258 60 robfinch
  .o(insn0a),
1259
  .fault(ic0_fault),
1260
  .hit(ihit0),
1261
  .invall(invic),
1262
  .invline(L1_invline)
1263
);
1264
generate begin : gICacheInst
1265
if (`WAYS > 1) begin
1266
FT64_L1_icache #(.pSize(`L1_ICACHE_SIZE)) uic1
1267
(
1268
  .rst(rst),
1269
  .clk(clk),
1270
  .nxt(icnxt),
1271
  .wr(L1_wr1),
1272
  .wr_ack(),
1273
  .en(L1_en),
1274 66 robfinch
  .adr(L1_selpc ? (thread_en ? {ASID,pc1}: {ASID,pc0plus6} ): L1_adr),
1275 60 robfinch
  .wadr(L1_adr),
1276 66 robfinch
  .i(L1_dat),
1277 60 robfinch
  .o(insn1b),
1278
  .fault(ic1_fault),
1279
  .hit(ihit1),
1280
  .invall(invic),
1281
  .invline(L1_invline)
1282
);
1283
end
1284
else begin
1285
assign ihit1 = 1'b1;
1286
end
1287
if (`WAYS > 2) begin
1288
FT64_L1_icache #(.pSize(`L1_ICACHE_SIZE)) uic2
1289
(
1290
  .rst(rst),
1291
  .clk(clk),
1292
  .nxt(icnxt),
1293
  .wr(L1_wr2),
1294
  .wr_ack(),
1295
  .en(L1_en),
1296 66 robfinch
  .adr(L1_selpc ? (thread_en ? {ASID,pc2} : {ASID,pc0plus12}) : L1_adr),
1297 60 robfinch
  .wadr(L1_adr),
1298 66 robfinch
  .i(L1_dat),
1299 60 robfinch
  .o(insn2b),
1300
  .fault(ic2_fault),
1301
  .hit(ihit2),
1302
  .invall(invic),
1303
  .invline(L1_invline)
1304
);
1305
end
1306
else
1307
assign ihit2 = 1'b1;
1308
end
1309
endgenerate
1310
 
1311
FT64_L2_icache uic2
1312
(
1313
  .rst(rst),
1314
  .clk(clk),
1315
  .nxt(L2_nxt),
1316 66 robfinch
  .wr(L2_ld),
1317
  .adr(selL2 ? L2_adr: L1_adr),
1318
  .cnt(L2_cnt),
1319 60 robfinch
  .exv_i(exvq),
1320
  .i(dat_i),
1321
  .err_i(errq),
1322
  .o(L2_dato),
1323
  .hit(ihitL2),
1324
  .invall(invic),
1325
  .invline()
1326
);
1327
 
1328
wire predict_taken;
1329
wire predict_taken0;
1330
wire predict_taken1;
1331
wire predict_taken2;
1332
wire predict_takenA;
1333
wire predict_takenB;
1334
wire predict_takenC;
1335
wire predict_takenD;
1336
wire predict_takenE;
1337
wire predict_takenF;
1338
wire predict_takenA1;
1339
wire predict_takenB1;
1340
wire predict_takenC1;
1341
wire predict_takenD1;
1342
 
1343
wire [`ABITS] btgtA, btgtB, btgtC, btgtD, btgtE, btgtF;
1344
wire btbwr0 = iqentry_v[heads[0]] && iqentry_state[heads[0]]==IQS_CMT &&
1345
        (iqentry_fc[heads[0]]);
1346
generate begin: gbtbvar
1347
if (`WAYS > 1) begin
1348
wire btbwr1 = iqentry_v[heads[1]] && iqentry_state[heads[1]]==IQS_CMT &&
1349
        (iqentry_fc[heads[1]]);
1350
end
1351
if (`WAYS > 2) begin
1352
wire btbwr2 = iqentry_v[heads[2]] && iqentry_state[heads[2]]==IQS_CMT &&
1353
        (iqentry_fc[heads[2]]);
1354
end
1355
end
1356
endgenerate
1357
 
1358
wire fcu_clk;
1359
`ifdef FCU_ENH
1360
//BUFGCE ufcuclk
1361
//(
1362
//      .I(clk_i),
1363
//      .CE(fcu_available),
1364
//      .O(fcu_clk)
1365
//);
1366
`endif
1367
assign fcu_clk = clk_i;
1368
 
1369
generate begin: gBTBInst
1370
if (`WAYS > 2) begin
1371
`ifdef FCU_ENH
1372
FT64_BTB #(.AMSB(AMSB)) ubtb1
1373
(
1374
  .rst(rst),
1375
  .wclk(fcu_clk),
1376
  .wr0(btbwr0),
1377
  .wadr0(iqentry_pc[heads[0]]),
1378
  .wdat0(iqentry_ma[heads[0]]),
1379
  .valid0((iqentry_br[heads[0]] ? iqentry_takb[heads[0]] : iqentry_bt[heads[0]]) & iqentry_v[heads[0]]),
1380
  .wr1(btbwr1),
1381
  .wadr1(iqentry_pc[heads[1]]),
1382
  .wdat1(iqentry_ma[heads[1]]),
1383
  .valid1((iqentry_br[heads[1]] ? iqentry_takb[heads[1]] : iqentry_bt[heads[1]]) & iqentry_v[heads[1]]),
1384
  .wr2(btbwr2),
1385
  .wadr2(iqentry_pc[heads[2]]),
1386
  .wdat2(iqentry_ma[heads[2]]),
1387
  .valid2((iqentry_br[heads[2]] ? iqentry_takb[heads[2]] : iqentry_bt[heads[2]]) & iqentry_v[heads[2]]),
1388
  .rclk(~clk),
1389
  .pcA(fetchbufA_pc),
1390
  .btgtA(btgtA),
1391
  .pcB(fetchbufB_pc),
1392
  .btgtB(btgtB),
1393
  .pcC(fetchbufC_pc),
1394
  .btgtC(btgtC),
1395
  .pcD(fetchbufD_pc),
1396
  .btgtD(btgtD),
1397
  .pcE(fetchbufE_pc),
1398
  .btgtE(btgtE),
1399
  .pcF(fetchbufF_pc),
1400
  .btgtF(btgtF),
1401
  .npcA(BRKPC),
1402
  .npcB(BRKPC),
1403
  .npcC(BRKPC),
1404
  .npcD(BRKPC),
1405
  .npcE(BRKPC),
1406
  .npcF(BRKPC)
1407
);
1408
`else
1409
// Branch tergets are picked up by fetchbuf logic and need to be present.
1410
// Without a target predictor they are just set to the reset address.
1411
// This virtually guarentees a miss.
1412
assign btgtA = RSTPC;
1413
assign btgtB = RSTPC;
1414
assign btgtC = RSTPC;
1415
assign btgtD = RSTPC;
1416
assign btgtE = RSTPC;
1417
assign btgtF = RSTPC;
1418
`endif
1419
end
1420
else if (`WAYS > 1) begin
1421
`ifdef FCU_ENH
1422
FT64_BTB #(.AMSB(AMSB)) ubtb1
1423
(
1424
  .rst(rst),
1425
  .wclk(fcu_clk),
1426
  .wr0(btbwr0),
1427
  .wadr0(iqentry_pc[heads[0]]),
1428
  .wdat0(iqentry_ma[heads[0]]),
1429
  .valid0((iqentry_br[heads[0]] ? iqentry_takb[heads[0]] : iqentry_bt[heads[0]]) & iqentry_v[heads[0]]),
1430
  .wr1(btbwr1),
1431
  .wadr1(iqentry_pc[heads[1]]),
1432
  .wdat1(iqentry_ma[heads[1]]),
1433
  .valid1((iqentry_br[heads[1]] ? iqentry_takb[heads[1]] : iqentry_bt[heads[1]]) & iqentry_v[heads[1]]),
1434
  .rclk(~clk),
1435
  .pcA(fetchbufA_pc),
1436
  .btgtA(btgtA),
1437
  .pcB(fetchbufB_pc),
1438
  .btgtB(btgtB),
1439
  .pcC(fetchbufC_pc),
1440
  .btgtC(btgtC),
1441
  .pcD(fetchbufD_pc),
1442
  .btgtD(btgtD),
1443
  .pcE(32'd0),
1444
  .btgtE(),
1445
  .pcF(32'd0),
1446
  .btgtF(),
1447
  .npcA(BRKPC),
1448
  .npcB(BRKPC),
1449
  .npcC(BRKPC),
1450
  .npcD(BRKPC),
1451
  .npcE(BRKPC),
1452
  .npcF(BRKPC)
1453
);
1454
`else
1455
// Branch tergets are picked up by fetchbuf logic and need to be present.
1456
// Without a target predictor they are just set to the reset address.
1457
// This virtually guarentees a miss.
1458
assign btgtA = RSTPC;
1459
assign btgtB = RSTPC;
1460
assign btgtC = RSTPC;
1461
assign btgtD = RSTPC;
1462
`endif
1463
end
1464
else begin
1465
`ifdef FCU_ENH
1466
FT64_BTB #(.AMSB(AMSB)) ubtb1
1467
(
1468
  .rst(rst),
1469
  .wclk(fcu_clk),
1470
  .wr0(btbwr0),
1471
  .wadr0(iqentry_pc[heads[0]]),
1472
  .wdat0(iqentry_ma[heads[0]]),
1473
  .valid0((iqentry_br[heads[0]] ? iqentry_takb[heads[0]] : iqentry_bt[heads[0]]) & iqentry_v[heads[0]]),
1474
  .wr1(1'b0);
1475
  .wadr1(RSTPC),
1476
  .wdat1(RSTPC),
1477
  .valid1(1'b0),
1478
  .wr2(1'b0);
1479
  .wadr2(RSTPC),
1480
  .wdat2(RSTPC),
1481
  .valid2(1'b0),
1482
  .rclk(~clk),
1483
  .pcA(fetchbufA_pc),
1484
  .btgtA(btgtA),
1485
  .pcB(fetchbufB_pc),
1486
  .btgtB(btgtB),
1487
  .pcC(32'd0),
1488
  .btgtC(),
1489
  .pcD(32'd0),
1490
  .btgtD(),
1491
  .pcE(32'd0),
1492
  .btgtE(),
1493
  .pcF(32'd0),
1494
  .btgtF(),
1495
  .hitA(),
1496
  .hitB(),
1497
  .hitC(),
1498
  .hitD(),
1499
  .hitE(),
1500
  .hitF(),
1501
  .npcA(BRKPC),
1502
  .npcB(BRKPC),
1503
  .npcC(BRKPC),
1504
  .npcD(BRKPC),
1505
  .npcE(BRKPC),
1506
  .npcF(BRKPC)
1507
);
1508
`else
1509
// Branch tergets are picked up by fetchbuf logic and need to be present.
1510
// Without a target predictor they are just set to the reset address.
1511
// This virtually guarentees a miss.
1512
assign btgtA = RSTPC;
1513
assign btgtB = RSTPC;
1514
`endif
1515
end
1516
end
1517
endgenerate
1518
 
1519
generate begin: gBPInst
1520
if (`WAYS > 2) begin
1521
`ifdef FCU_ENH
1522
FT64_BranchPredictor ubp1
1523
(
1524
  .rst(rst),
1525
  .clk(fcu_clk),
1526
  .en(bpe),
1527
  .xisBranch0(iqentry_br[heads[0]] & commit0_v),
1528
  .xisBranch1(iqentry_br[heads[1]] & commit1_v),
1529
  .xisBranch2(iqentry_br[heads[2]] & commit2_v),
1530
  .pcA(fetchbufA_pc),
1531
  .pcB(fetchbufB_pc),
1532
  .pcC(fetchbufC_pc),
1533
  .pcD(fetchbufD_pc),
1534
  .pcE(fetchbufE_pc),
1535
  .pcF(fetchbufF_pc),
1536
  .xpc0(iqentry_pc[heads[0]]),
1537
  .xpc1(iqentry_pc[heads[1]]),
1538
  .xpc2(iqentry_pc[heads[2]]),
1539
  .takb0(commit0_v & iqentry_takb[heads[0]]),
1540
  .takb1(commit1_v & iqentry_takb[heads[1]]),
1541
  .takb2(commit2_v & iqentry_takb[heads[2]]),
1542
  .predict_takenA(predict_takenA),
1543
  .predict_takenB(predict_takenB),
1544
  .predict_takenC(predict_takenC),
1545
  .predict_takenD(predict_takenD),
1546
  .predict_takenE(predict_takenE),
1547
  .predict_takenF(predict_takenF)
1548
);
1549
`else
1550
// Predict based on sign of displacement
1551
assign predict_takenA = fetchbufA_instr[6] ? fetchbufA_instr[47] : fetchbufA_instr[31];
1552
assign predict_takenB = fetchbufB_instr[6] ? fetchbufB_instr[47] : fetchbufB_instr[31];
1553
assign predict_takenC = fetchbufC_instr[6] ? fetchbufC_instr[47] : fetchbufC_instr[31];
1554
assign predict_takenD = fetchbufD_instr[6] ? fetchbufD_instr[47] : fetchbufD_instr[31];
1555
assign predict_takenE = fetchbufE_instr[6] ? fetchbufE_instr[47] : fetchbufE_instr[31];
1556
assign predict_takenF = fetchbufF_instr[6] ? fetchbufF_instr[47] : fetchbufF_instr[31];
1557
`endif
1558
end
1559
else if (`WAYS > 1) begin
1560
`ifdef FCU_ENH
1561
FT64_BranchPredictor ubp1
1562
(
1563
  .rst(rst),
1564
  .clk(fcu_clk),
1565
  .en(bpe),
1566
  .xisBranch0(iqentry_br[heads[0]] & commit0_v),
1567
  .xisBranch1(iqentry_br[heads[1]] & commit1_v),
1568
  .xisBranch2(iqentry_br[heads[2]] & commit2_v),
1569
  .pcA(fetchbufA_pc),
1570
  .pcB(fetchbufB_pc),
1571
  .pcC(fetchbufC_pc),
1572
  .pcD(fetchbufD_pc),
1573
  .pcE(32'd0),
1574
  .pcF(32'd0),
1575
  .xpc0(iqentry_pc[heads[0]]),
1576
  .xpc1(iqentry_pc[heads[1]]),
1577
  .xpc2(iqentry_pc[heads[2]]),
1578
  .takb0(commit0_v & iqentry_takb[heads[0]]),
1579
  .takb1(commit1_v & iqentry_takb[heads[1]]),
1580
  .takb2(commit2_v & iqentry_takb[heads[2]]),
1581
  .predict_takenA(predict_takenA),
1582
  .predict_takenB(predict_takenB),
1583
  .predict_takenC(predict_takenC),
1584
  .predict_takenD(predict_takenD),
1585
  .predict_takenE(),
1586
  .predict_takenF()
1587
);
1588
`else
1589
// Predict based on sign of displacement
1590
assign predict_takenA = fetchbufA_instr[6] ? fetchbufA_instr[47] : fetchbufA_instr[31];
1591
assign predict_takenB = fetchbufB_instr[6] ? fetchbufB_instr[47] : fetchbufB_instr[31];
1592
assign predict_takenC = fetchbufC_instr[6] ? fetchbufC_instr[47] : fetchbufC_instr[31];
1593
assign predict_takenD = fetchbufD_instr[6] ? fetchbufD_instr[47] : fetchbufD_instr[31];
1594
`endif
1595
end
1596
else begin
1597
`ifdef FCU_ENH
1598
FT64_BranchPredictor ubp1
1599
(
1600
  .rst(rst),
1601
  .clk(fcu_clk),
1602
  .en(bpe),
1603
  .xisBranch0(iqentry_br[heads[0]] & commit0_v),
1604
  .xisBranch1(iqentry_br[heads[1]] & commit1_v),
1605
  .xisBranch2(iqentry_br[heads[2]] & commit2_v),
1606
  .pcA(fetchbufA_pc),
1607
  .pcB(fetchbufB_pc),
1608
  .pcC(32'd0),
1609
  .pcD(32'd0),
1610
  .pcE(32'd0),
1611
  .pcF(32'd0),
1612
  .xpc0(iqentry_pc[heads[0]]),
1613
  .xpc1(iqentry_pc[heads[1]]),
1614
  .xpc2(iqentry_pc[heads[2]]),
1615
  .takb0(commit0_v & iqentry_takb[heads[0]]),
1616
  .takb1(commit1_v & iqentry_takb[heads[1]]),
1617
  .takb2(commit2_v & iqentry_takb[heads[2]]),
1618
  .predict_takenA(predict_takenA),
1619
  .predict_takenB(predict_takenB),
1620
  .predict_takenC(),
1621
  .predict_takenD(),
1622
  .predict_takenE(),
1623
  .predict_takenF()
1624
);
1625
`else
1626
// Predict based on sign of displacement
1627
assign predict_takenA = fetchbufA_instr[6] ? fetchbufA_instr[47] : fetchbufA_instr[31];
1628
assign predict_takenB = fetchbufB_instr[6] ? fetchbufB_instr[47] : fetchbufB_instr[31];
1629
`endif
1630
end
1631
end
1632
endgenerate
1633
 
1634
//-----------------------------------------------------------------------------
1635
// Debug
1636
//-----------------------------------------------------------------------------
1637
`ifdef SUPPORT_DBG
1638
 
1639
wire [DBW-1:0] dbg_stat1x;
1640
reg [DBW-1:0] dbg_stat;
1641
reg [DBW-1:0] dbg_ctrl;
1642
reg [ABW-1:0] dbg_adr0;
1643
reg [ABW-1:0] dbg_adr1;
1644
reg [ABW-1:0] dbg_adr2;
1645
reg [ABW-1:0] dbg_adr3;
1646
reg dbg_imatchA0,dbg_imatchA1,dbg_imatchA2,dbg_imatchA3,dbg_imatchA;
1647
reg dbg_imatchB0,dbg_imatchB1,dbg_imatchB2,dbg_imatchB3,dbg_imatchB;
1648
 
1649
wire dbg_lmatch00 =
1650
                        dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram0_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1651
                                ((dbg_ctrl[19:18]==2'b00 && dram0_addr[2:0]==dbg_adr0[2:0]) ||
1652
                                 (dbg_ctrl[19:18]==2'b01 && dram0_addr[2:1]==dbg_adr0[2:1]) ||
1653
                                 (dbg_ctrl[19:18]==2'b10 && dram0_addr[2]==dbg_adr0[2]) ||
1654
                                 dbg_ctrl[19:18]==2'b11)
1655
                                 ;
1656
wire dbg_lmatch01 =
1657
             dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram1_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1658
                 ((dbg_ctrl[19:18]==2'b00 && dram1_addr[2:0]==dbg_adr0[2:0]) ||
1659
                  (dbg_ctrl[19:18]==2'b01 && dram1_addr[2:1]==dbg_adr0[2:1]) ||
1660
                  (dbg_ctrl[19:18]==2'b10 && dram1_addr[2]==dbg_adr0[2]) ||
1661
                  dbg_ctrl[19:18]==2'b11)
1662
                  ;
1663
wire dbg_lmatch02 =
1664
           dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram2_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1665
               ((dbg_ctrl[19:18]==2'b00 && dram2_addr[2:0]==dbg_adr0[2:0]) ||
1666
                (dbg_ctrl[19:18]==2'b01 && dram2_addr[2:1]==dbg_adr0[2:1]) ||
1667
                (dbg_ctrl[19:18]==2'b10 && dram2_addr[2]==dbg_adr0[2]) ||
1668
                dbg_ctrl[19:18]==2'b11)
1669
                ;
1670
wire dbg_lmatch10 =
1671
             dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram0_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1672
                 ((dbg_ctrl[23:22]==2'b00 && dram0_addr[2:0]==dbg_adr1[2:0]) ||
1673
                  (dbg_ctrl[23:22]==2'b01 && dram0_addr[2:1]==dbg_adr1[2:1]) ||
1674
                  (dbg_ctrl[23:22]==2'b10 && dram0_addr[2]==dbg_adr1[2]) ||
1675
                  dbg_ctrl[23:22]==2'b11)
1676
                  ;
1677
wire dbg_lmatch11 =
1678
           dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram1_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1679
               ((dbg_ctrl[23:22]==2'b00 && dram1_addr[2:0]==dbg_adr1[2:0]) ||
1680
                (dbg_ctrl[23:22]==2'b01 && dram1_addr[2:1]==dbg_adr1[2:1]) ||
1681
                (dbg_ctrl[23:22]==2'b10 && dram1_addr[2]==dbg_adr1[2]) ||
1682
                dbg_ctrl[23:22]==2'b11)
1683
                ;
1684
wire dbg_lmatch12 =
1685
           dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram2_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1686
               ((dbg_ctrl[23:22]==2'b00 && dram2_addr[2:0]==dbg_adr1[2:0]) ||
1687
                (dbg_ctrl[23:22]==2'b01 && dram2_addr[2:1]==dbg_adr1[2:1]) ||
1688
                (dbg_ctrl[23:22]==2'b10 && dram2_addr[2]==dbg_adr1[2]) ||
1689
                dbg_ctrl[23:22]==2'b11)
1690
                ;
1691
wire dbg_lmatch20 =
1692
               dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram0_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1693
                   ((dbg_ctrl[27:26]==2'b00 && dram0_addr[2:0]==dbg_adr2[2:0]) ||
1694
                    (dbg_ctrl[27:26]==2'b01 && dram0_addr[2:1]==dbg_adr2[2:1]) ||
1695
                    (dbg_ctrl[27:26]==2'b10 && dram0_addr[2]==dbg_adr2[2]) ||
1696
                    dbg_ctrl[27:26]==2'b11)
1697
                    ;
1698
wire dbg_lmatch21 =
1699
               dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram1_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1700
                   ((dbg_ctrl[27:26]==2'b00 && dram1_addr[2:0]==dbg_adr2[2:0]) ||
1701
                    (dbg_ctrl[27:26]==2'b01 && dram1_addr[2:1]==dbg_adr2[2:1]) ||
1702
                    (dbg_ctrl[27:26]==2'b10 && dram1_addr[2]==dbg_adr2[2]) ||
1703
                    dbg_ctrl[27:26]==2'b11)
1704
                    ;
1705
wire dbg_lmatch22 =
1706
               dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram2_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1707
                   ((dbg_ctrl[27:26]==2'b00 && dram2_addr[2:0]==dbg_adr2[2:0]) ||
1708
                    (dbg_ctrl[27:26]==2'b01 && dram2_addr[2:1]==dbg_adr2[2:1]) ||
1709
                    (dbg_ctrl[27:26]==2'b10 && dram2_addr[2]==dbg_adr2[2]) ||
1710
                    dbg_ctrl[27:26]==2'b11)
1711
                    ;
1712
wire dbg_lmatch30 =
1713
                 dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram0_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1714
                     ((dbg_ctrl[31:30]==2'b00 && dram0_addr[2:0]==dbg_adr3[2:0]) ||
1715
                      (dbg_ctrl[31:30]==2'b01 && dram0_addr[2:1]==dbg_adr3[2:1]) ||
1716
                      (dbg_ctrl[31:30]==2'b10 && dram0_addr[2]==dbg_adr3[2]) ||
1717
                      dbg_ctrl[31:30]==2'b11)
1718
                      ;
1719
wire dbg_lmatch31 =
1720
               dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram1_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1721
                   ((dbg_ctrl[31:30]==2'b00 && dram1_addr[2:0]==dbg_adr3[2:0]) ||
1722
                    (dbg_ctrl[31:30]==2'b01 && dram1_addr[2:1]==dbg_adr3[2:1]) ||
1723
                    (dbg_ctrl[31:30]==2'b10 && dram1_addr[2]==dbg_adr3[2]) ||
1724
                    dbg_ctrl[31:30]==2'b11)
1725
                    ;
1726
wire dbg_lmatch32 =
1727
               dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram2_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1728
                   ((dbg_ctrl[31:30]==2'b00 && dram2_addr[2:0]==dbg_adr3[2:0]) ||
1729
                    (dbg_ctrl[31:30]==2'b01 && dram2_addr[2:1]==dbg_adr3[2:1]) ||
1730
                    (dbg_ctrl[31:30]==2'b10 && dram2_addr[2]==dbg_adr3[2]) ||
1731
                    dbg_ctrl[31:30]==2'b11)
1732
                    ;
1733
wire dbg_lmatch0 = dbg_lmatch00|dbg_lmatch10|dbg_lmatch20|dbg_lmatch30;
1734
wire dbg_lmatch1 = dbg_lmatch01|dbg_lmatch11|dbg_lmatch21|dbg_lmatch31;
1735
wire dbg_lmatch2 = dbg_lmatch02|dbg_lmatch12|dbg_lmatch22|dbg_lmatch32;
1736
wire dbg_lmatch = dbg_lmatch00|dbg_lmatch10|dbg_lmatch20|dbg_lmatch30|
1737
                  dbg_lmatch01|dbg_lmatch11|dbg_lmatch21|dbg_lmatch31|
1738
                  dbg_lmatch02|dbg_lmatch12|dbg_lmatch22|dbg_lmatch32
1739
                    ;
1740
 
1741
wire dbg_smatch00 =
1742
                        dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram0_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1743
                                ((dbg_ctrl[19:18]==2'b00 && dram0_addr[2:0]==dbg_adr0[2:0]) ||
1744
                                 (dbg_ctrl[19:18]==2'b01 && dram0_addr[2:1]==dbg_adr0[2:1]) ||
1745
                                 (dbg_ctrl[19:18]==2'b10 && dram0_addr[2]==dbg_adr0[2]) ||
1746
                                 dbg_ctrl[19:18]==2'b11)
1747
                                 ;
1748
wire dbg_smatch01 =
1749
             dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram1_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1750
                 ((dbg_ctrl[19:18]==2'b00 && dram1_addr[2:0]==dbg_adr0[2:0]) ||
1751
                  (dbg_ctrl[19:18]==2'b01 && dram1_addr[2:1]==dbg_adr0[2:1]) ||
1752
                  (dbg_ctrl[19:18]==2'b10 && dram1_addr[2]==dbg_adr0[2]) ||
1753
                  dbg_ctrl[19:18]==2'b11)
1754
                  ;
1755
wire dbg_smatch02 =
1756
           dbg_ctrl[0] && dbg_ctrl[17:16]==2'b11 && dram2_addr[AMSB:3]==dbg_adr0[AMSB:3] &&
1757
               ((dbg_ctrl[19:18]==2'b00 && dram2_addr[2:0]==dbg_adr0[2:0]) ||
1758
                (dbg_ctrl[19:18]==2'b01 && dram2_addr[2:1]==dbg_adr0[2:1]) ||
1759
                (dbg_ctrl[19:18]==2'b10 && dram2_addr[2]==dbg_adr0[2]) ||
1760
                dbg_ctrl[19:18]==2'b11)
1761
                ;
1762
wire dbg_smatch10 =
1763
             dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram0_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1764
                 ((dbg_ctrl[23:22]==2'b00 && dram0_addr[2:0]==dbg_adr1[2:0]) ||
1765
                  (dbg_ctrl[23:22]==2'b01 && dram0_addr[2:1]==dbg_adr1[2:1]) ||
1766
                  (dbg_ctrl[23:22]==2'b10 && dram0_addr[2]==dbg_adr1[2]) ||
1767
                  dbg_ctrl[23:22]==2'b11)
1768
                  ;
1769
wire dbg_smatch11 =
1770
           dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram1_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1771
               ((dbg_ctrl[23:22]==2'b00 && dram1_addr[2:0]==dbg_adr1[2:0]) ||
1772
                (dbg_ctrl[23:22]==2'b01 && dram1_addr[2:1]==dbg_adr1[2:1]) ||
1773
                (dbg_ctrl[23:22]==2'b10 && dram1_addr[2]==dbg_adr1[2]) ||
1774
                dbg_ctrl[23:22]==2'b11)
1775
                ;
1776
wire dbg_smatch12 =
1777
           dbg_ctrl[1] && dbg_ctrl[21:20]==2'b11 && dram2_addr[AMSB:3]==dbg_adr1[AMSB:3] &&
1778
               ((dbg_ctrl[23:22]==2'b00 && dram2_addr[2:0]==dbg_adr1[2:0]) ||
1779
                (dbg_ctrl[23:22]==2'b01 && dram2_addr[2:1]==dbg_adr1[2:1]) ||
1780
                (dbg_ctrl[23:22]==2'b10 && dram2_addr[2]==dbg_adr1[2]) ||
1781
                dbg_ctrl[23:22]==2'b11)
1782
                ;
1783
wire dbg_smatch20 =
1784
               dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram0_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1785
                   ((dbg_ctrl[27:26]==2'b00 && dram0_addr[2:0]==dbg_adr2[2:0]) ||
1786
                    (dbg_ctrl[27:26]==2'b01 && dram0_addr[2:1]==dbg_adr2[2:1]) ||
1787
                    (dbg_ctrl[27:26]==2'b10 && dram0_addr[2]==dbg_adr2[2]) ||
1788
                    dbg_ctrl[27:26]==2'b11)
1789
                    ;
1790
wire dbg_smatch21 =
1791
           dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram1_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1792
                    ((dbg_ctrl[27:26]==2'b00 && dram1_addr[2:0]==dbg_adr2[2:0]) ||
1793
                     (dbg_ctrl[27:26]==2'b01 && dram1_addr[2:1]==dbg_adr2[2:1]) ||
1794
                     (dbg_ctrl[27:26]==2'b10 && dram1_addr[2]==dbg_adr2[2]) ||
1795
                     dbg_ctrl[27:26]==2'b11)
1796
                     ;
1797
wire dbg_smatch22 =
1798
            dbg_ctrl[2] && dbg_ctrl[25:24]==2'b11 && dram2_addr[AMSB:3]==dbg_adr2[AMSB:3] &&
1799
                     ((dbg_ctrl[27:26]==2'b00 && dram2_addr[2:0]==dbg_adr2[2:0]) ||
1800
                      (dbg_ctrl[27:26]==2'b01 && dram2_addr[2:1]==dbg_adr2[2:1]) ||
1801
                      (dbg_ctrl[27:26]==2'b10 && dram2_addr[2]==dbg_adr2[2]) ||
1802
                      dbg_ctrl[27:26]==2'b11)
1803
                      ;
1804
wire dbg_smatch30 =
1805
                 dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram0_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1806
                     ((dbg_ctrl[31:30]==2'b00 && dram0_addr[2:0]==dbg_adr3[2:0]) ||
1807
                      (dbg_ctrl[31:30]==2'b01 && dram0_addr[2:1]==dbg_adr3[2:1]) ||
1808
                      (dbg_ctrl[31:30]==2'b10 && dram0_addr[2]==dbg_adr3[2]) ||
1809
                      dbg_ctrl[31:30]==2'b11)
1810
                      ;
1811
wire dbg_smatch31 =
1812
               dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram1_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1813
                   ((dbg_ctrl[31:30]==2'b00 && dram1_addr[2:0]==dbg_adr3[2:0]) ||
1814
                    (dbg_ctrl[31:30]==2'b01 && dram1_addr[2:1]==dbg_adr3[2:1]) ||
1815
                    (dbg_ctrl[31:30]==2'b10 && dram1_addr[2]==dbg_adr3[2]) ||
1816
                    dbg_ctrl[31:30]==2'b11)
1817
                    ;
1818
wire dbg_smatch32 =
1819
               dbg_ctrl[3] && dbg_ctrl[29:28]==2'b11 && dram2_addr[AMSB:3]==dbg_adr3[AMSB:3] &&
1820
                   ((dbg_ctrl[31:30]==2'b00 && dram2_addr[2:0]==dbg_adr3[2:0]) ||
1821
                    (dbg_ctrl[31:30]==2'b01 && dram2_addr[2:1]==dbg_adr3[2:1]) ||
1822
                    (dbg_ctrl[31:30]==2'b10 && dram2_addr[2]==dbg_adr3[2]) ||
1823
                    dbg_ctrl[31:30]==2'b11)
1824
                    ;
1825
wire dbg_smatch0 = dbg_smatch00|dbg_smatch10|dbg_smatch20|dbg_smatch30;
1826
wire dbg_smatch1 = dbg_smatch01|dbg_smatch11|dbg_smatch21|dbg_smatch31;
1827
wire dbg_smatch2 = dbg_smatch02|dbg_smatch12|dbg_smatch22|dbg_smatch32;
1828
 
1829
wire dbg_smatch =   dbg_smatch00|dbg_smatch10|dbg_smatch20|dbg_smatch30|
1830
                    dbg_smatch01|dbg_smatch11|dbg_smatch21|dbg_smatch31|
1831
                    dbg_smatch02|dbg_smatch12|dbg_smatch22|dbg_smatch32
1832
                    ;
1833
 
1834
wire dbg_stat0 = dbg_imatchA0 | dbg_imatchB0 | dbg_lmatch00 | dbg_lmatch01 | dbg_lmatch02 | dbg_smatch00 | dbg_smatch01 | dbg_smatch02;
1835
wire dbg_stat1 = dbg_imatchA1 | dbg_imatchB1 | dbg_lmatch10 | dbg_lmatch11 | dbg_lmatch12 | dbg_smatch10 | dbg_smatch11 | dbg_smatch12;
1836
wire dbg_stat2 = dbg_imatchA2 | dbg_imatchB2 | dbg_lmatch20 | dbg_lmatch21 | dbg_lmatch22 | dbg_smatch20 | dbg_smatch21 | dbg_smatch22;
1837
wire dbg_stat3 = dbg_imatchA3 | dbg_imatchB3 | dbg_lmatch30 | dbg_lmatch31 | dbg_lmatch32 | dbg_smatch30 | dbg_smatch31 | dbg_smatch32;
1838
assign dbg_stat1x = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
1839
wire debug_on = |dbg_ctrl[3:0]|dbg_ctrl[7]|dbg_ctrl[63];
1840
 
1841
always @*
1842
begin
1843
    if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf0_pc==dbg_adr0)
1844
        dbg_imatchA0 = `TRUE;
1845
    if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf0_pc==dbg_adr1)
1846
        dbg_imatchA1 = `TRUE;
1847
    if (dbg_ctrl[2] && dbg_ctrl[25:24]==2'b00 && fetchbuf0_pc==dbg_adr2)
1848
        dbg_imatchA2 = `TRUE;
1849
    if (dbg_ctrl[3] && dbg_ctrl[29:28]==2'b00 && fetchbuf0_pc==dbg_adr3)
1850
        dbg_imatchA3 = `TRUE;
1851
    if (dbg_imatchA0|dbg_imatchA1|dbg_imatchA2|dbg_imatchA3)
1852
        dbg_imatchA = `TRUE;
1853
end
1854
 
1855
always @*
1856
begin
1857
    if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf1_pc==dbg_adr0)
1858
        dbg_imatchB0 = `TRUE;
1859
    if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf1_pc==dbg_adr1)
1860
        dbg_imatchB1 = `TRUE;
1861
    if (dbg_ctrl[2] && dbg_ctrl[25:24]==2'b00 && fetchbuf1_pc==dbg_adr2)
1862
        dbg_imatchB2 = `TRUE;
1863
    if (dbg_ctrl[3] && dbg_ctrl[29:28]==2'b00 && fetchbuf1_pc==dbg_adr3)
1864
        dbg_imatchB3 = `TRUE;
1865
    if (dbg_imatchB0|dbg_imatchB1|dbg_imatchB2|dbg_imatchB3)
1866
        dbg_imatchB = `TRUE;
1867
end
1868
`endif
1869
 
1870
//-----------------------------------------------------------------------------
1871
//-----------------------------------------------------------------------------
1872
 
1873
// freezePC squashes the pc increment if there's an irq.
1874
// If there is a segment prefix present then defer the freezing of the pc.
1875
// If a hardware interrupt instruction is encountered in the instruction stream
1876
// flag it as a privilege violation.
1877
wire freezePC = (irq_i > im) && !int_commit;
1878
always @*
1879
if (freezePC) begin
1880 61 robfinch
        insn0 <= {32'h00,6'd0,5'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
1881 60 robfinch
end
1882
else if (phit) begin
1883
//      if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[25:21]==5'd0 && insn0a[`INSTRUCTION_L2]==2'b00)
1884
//              insn0 <= {6'd1,5'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
1885
//      else
1886
                insn0 <= insn0a;
1887 61 robfinch
                if (insn0a[15:0]==16'hFF00) begin        // BRK #255
1888
                        if (~|irq_i)
1889
                                insn0 <= {8'h00,`NOP_INSN};
1890
                        else
1891
                                insn0[20:0] <= {irq_i,1'b0,vec_i,2'b00,`BRK};
1892
                end
1893 66 robfinch
                else if (insn0a[15:0]==16'h0000)
1894 61 robfinch
                        insn0 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_IBE,2'b00,`BRK};
1895 66 robfinch
                else
1896
                        case(ic0_fault)
1897
                        2'd0:   ;       // no fault, don't alter instruction
1898
                        2'd1:   insn0 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_TLB,2'b00,`BRK};
1899
                        2'd2:   insn0 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_EXF,2'b00,`BRK};
1900
                        2'd3:   insn0 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_IBE,2'b00,`BRK};
1901
                        endcase
1902 60 robfinch
end
1903
else begin
1904
        insn0 <= {8'h00,`NOP_INSN};
1905
end
1906 61 robfinch
 
1907 60 robfinch
generate begin : gInsnMux
1908
if (`WAYS > 1) begin
1909
always @*
1910
if (freezePC && !thread_en) begin
1911
        insn1 <= {8'h00,6'd0,5'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
1912
end
1913
else if (phit) begin
1914
//      if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[25:21]==5'd0 && insn1a[`INSTRUCTION_L2]==2'b00)
1915
//              insn1 <= {6'd1,5'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
1916
//      else
1917
                insn1 <= insn1a;
1918 61 robfinch
                if (insn1a[15:0]==16'hFF00) begin
1919
                        if (~|irq_i)
1920
                                insn1 <= {8'h00,`NOP_INSN};
1921
                        else
1922
                                insn1[20:0] <= {irq_i,1'b0,vec_i,2'b00,`BRK};
1923
                end
1924 66 robfinch
                        case(ic1_fault)
1925
                        2'd0:   ;       // no fault, don't alter instruction
1926
                        2'd1:   insn1 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_TLB,2'b00,`BRK};
1927
                        2'd2:   insn1 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_EXF,2'b00,`BRK};
1928
                        2'd3:   insn1 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_IBE,2'b00,`BRK};
1929
                        endcase
1930 60 robfinch
end
1931
else begin
1932
        insn1 <= {8'h00,`NOP_INSN};
1933
end
1934
end
1935
if (`WAYS > 2) begin
1936
always @*
1937
if (freezePC && !thread_en)
1938
        insn2 <= {6'd0,5'd0,irq_i,1'b0,vec_i,2'b00,`BRK};
1939
else if (phit) begin
1940
//      if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[25:21]==5'd0 && insn2a[`INSTRUCTION_L2]==2'b00)
1941
//              insn2 <= {6'd1,5'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK};
1942
//      else
1943
                insn2 <= insn2a;
1944 61 robfinch
                if (insn2a[15:0]==16'hFF00) begin
1945
                        if (~|irq_i)
1946
                                insn2 <= {8'h00,`NOP_INSN};
1947
                        else
1948
                                insn2[20:0] <= {irq_i,1'b0,vec_i,2'b00,`BRK};
1949
                end
1950 66 robfinch
                        case(ic2_fault)
1951
                        2'd0:   ;       // no fault, don't alter instruction
1952
                        2'd1:   insn2 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_TLB,2'b00,`BRK};
1953
                        2'd2:   insn2 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_EXF,2'b00,`BRK};
1954
                        2'd3:   insn2 <= {32'h00,6'd0,5'd0,4'h0,1'b0,`FLT_IBE,2'b00,`BRK};
1955
                        endcase
1956 60 robfinch
end
1957
else
1958
        insn2 <= `NOP_INSN;
1959
end
1960
end
1961
endgenerate
1962
 
1963
wire [63:0] dc0_out, dc1_out, dc2_out;
1964 61 robfinch
assign rdat0 = dram0_unc ? xdati[63:0] : dc0_out;
1965
assign rdat1 = dram1_unc ? xdati[63:0] : dc1_out;
1966
assign rdat2 = dram2_unc ? xdati[63:0] : dc2_out;
1967 60 robfinch
 
1968
reg preload;
1969
reg [1:0] dccnt;
1970 66 robfinch
reg [3:0] dcwait = 4'd3;
1971
reg [3:0] dcwait_ctr = 4'd3;
1972 60 robfinch
wire dhit0, dhit1, dhit2;
1973
wire dhit0a, dhit1a, dhit2a;
1974
wire dhit00, dhit10, dhit20;
1975
wire dhit01, dhit11, dhit21;
1976
reg [`ABITS] dc_wadr;
1977
reg [63:0] dc_wdat;
1978
reg isStore;
1979 66 robfinch
reg [31:0] dcsel;
1980
reg [255:0] dcbuf;
1981
reg dcwr;
1982 60 robfinch
 
1983
// If the data is in the write buffer, give the buffer a chance to
1984
// write out the data before trying to load from the cache.
1985
reg wb_hit0, wb_hit1, wb_hit2;
1986
always @*
1987
begin
1988
        wb_hit0 <= FALSE;
1989
        wb_hit1 <= FALSE;
1990
        wb_hit2 <= FALSE;
1991
        for (n = 0; n < `WB_DEPTH; n = n + 1) begin
1992
                if (wb_v[n] && wb_addr[n][AMSB:3]==dram0_addr[AMSB:3])
1993
                        wb_hit0 <= TRUE;
1994
                if (`NUM_MEM > 1 && wb_v[n] && wb_addr[n][AMSB:3]==dram1_addr[AMSB:3])
1995
                        wb_hit1 <= TRUE;
1996
                if (`NUM_MEM > 2 && wb_v[n] && wb_addr[n][AMSB:3]==dram2_addr[AMSB:3])
1997
                        wb_hit2 <= TRUE;
1998
        end
1999
end
2000
 
2001
assign dhit0 = dhit0a && !wb_hit0;
2002
assign dhit1 = dhit1a && !wb_hit1;
2003
assign dhit2 = dhit2a && !wb_hit2;
2004
wire whit0, whit1, whit2;
2005
 
2006 66 robfinch
wire wr_dcache0 = (dcwr)||(((bstate==B_StoreAck && StoreAck1) || (bstate==B_LSNAck && isStore)) && whit0);
2007
wire wr_dcache1 = (dcwr)||(((bstate==B_StoreAck && StoreAck1) || (bstate==B_LSNAck && isStore)) && whit1);
2008
wire wr_dcache2 = (dcwr)||(((bstate==B_StoreAck && StoreAck1) || (bstate==B_LSNAck && isStore)) && whit2);
2009 60 robfinch
 
2010
FT64_dcache udc0
2011
(
2012
  .rst(rst),
2013
  .wclk(clk),
2014
  .dce(dce),
2015
  .wr(wr_dcache0),
2016 66 robfinch
  .sel(dcsel),
2017
  .wadr({ASID,vadr}),
2018 60 robfinch
  .whit(whit0),
2019 66 robfinch
  .i(dcbuf),
2020 60 robfinch
  .rclk(clk),
2021
  .rdsize(dram0_memsize),
2022 66 robfinch
  .radr({ASID,dram0_addr}),
2023 60 robfinch
  .o(dc0_out),
2024
  .rhit(dhit0a)
2025
);
2026
generate begin : gDCacheInst
2027
if (`NUM_MEM > 1) begin
2028
FT64_dcache udc1
2029
(
2030
  .rst(rst),
2031
  .wclk(clk),
2032
  .dce(dce),
2033
  .wr(wr_dcache1),
2034 66 robfinch
  .sel(dcsel),
2035
  .wadr({ASID,vadr}),
2036 60 robfinch
  .whit(whit1),
2037 66 robfinch
  .i(dcbuf),
2038 60 robfinch
  .rclk(clk),
2039
  .rdsize(dram1_memsize),
2040 66 robfinch
  .radr({ASID,dram1_addr}),
2041 60 robfinch
  .o(dc1_out),
2042
  .rhit(dhit1a)
2043
);
2044
end
2045
if (`NUM_MEM > 2) begin
2046
FT64_dcache udc2
2047
(
2048
  .rst(rst),
2049
  .wclk(clk),
2050
  .dce(dce),
2051
  .wr(wr_dcache2),
2052 66 robfinch
  .sel(dcsel),
2053
  .wadr({ASID,vadr}),
2054 60 robfinch
  .whit(whit2),
2055 66 robfinch
  .i(dcbuf),
2056 60 robfinch
  .rclk(clk),
2057
  .rdsize(dram2_memsize),
2058 66 robfinch
  .radr({ASID,dram2_addr}),
2059 60 robfinch
  .o(dc2_out),
2060
  .rhit(dhit2a)
2061
);
2062
end
2063
end
2064
endgenerate
2065
 
2066
`ifdef SUPPORT_SMT
2067
function [RBIT:0] fnRa;
2068
input [47:0] isn;
2069
input [5:0] vqei;
2070
input [5:0] vli;
2071
input thrd;
2072
case(isn[`INSTRUCTION_OP])
2073
`IVECTOR:
2074
        case(isn[`INSTRUCTION_S2])
2075
        `VCIDX,`VSCAN:  fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
2076
        `VMxx:
2077
                case(isn[25:23])
2078
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP,`VMFIRST,`VMLAST:
2079
                    fnRa = {6'h3F,1'b1,2'b0,isn[10:8]};
2080
            `VMFILL:fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
2081
            default:fnRa = {6'h3F,1'b1,2'b0,isn[10:8]};
2082
            endcase
2083
        `VSHLV:     fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
2084
        `VSHRV:     fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
2085
        `VSxx,`VSxxU,`VSxxS,`VSxxSU:    fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
2086
        default:    fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
2087
        endcase
2088
`R2:    casez(isn[`INSTRUCTION_S2])
2089
                `MOV:
2090
                        case(isn[25:23])
2091
                        3'd0:   fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2092
                        3'd1:   fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
2093
                        3'd2:   fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2094
                        3'd3:   fnRa = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RA]};
2095
                        3'd4:   fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2096
                        3'd5:   fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2097
                        3'd6:   fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2098
                        default:fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2099
                        endcase
2100
        `VMOV:
2101
            case (isn[`INSTRUCTION_S1])
2102
            5'h0:   fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2103
            5'h1:   fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
2104
            endcase
2105
        default:    fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2106
        endcase
2107
`FLOAT:         fnRa = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2108
default:    fnRa = {rgs[thrd],1'b0,isn[`INSTRUCTION_RA]};
2109
endcase
2110
endfunction
2111
 
2112
function [RBIT:0] fnRb;
2113
input [47:0] isn;
2114
input fb;
2115
input [5:0] vqei;
2116
input [5:0] rfoa0i;
2117
input [5:0] rfoa1i;
2118
input thrd;
2119
case(isn[`INSTRUCTION_OP])
2120
`R2:        case(isn[`INSTRUCTION_S2])
2121
            `VEX:       fnRb = fb ? {rfoa1i,1'b1,isn[`INSTRUCTION_RB]} : {rfoa0i,1'b1,isn[`INSTRUCTION_RB]};
2122
            `LVX,`SVX:  fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2123
            default:    fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
2124
            endcase
2125
`IVECTOR:
2126
                        case(isn[`INSTRUCTION_S2])
2127
                        `VMxx:
2128
                                case(isn[25:23])
2129
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
2130
                        fnRb = {6'h3F,1'b1,2'b0,isn[20:18]};
2131
                default:        fnRb = 12'h000;
2132
                endcase
2133
            `VXCHG:     fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2134
            `VSxx,`VSxxU:   fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2135
                `VSxxS,`VSxxSU:    fnRb = {vqei,1'b0,isn[`INSTRUCTION_RB]};
2136
            `VADDS,`VSUBS,`VMULS,`VANDS,`VORS,`VXORS,`VXORS:
2137
                fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
2138
            `VSHL,`VSHR,`VASR:
2139
                fnRb = {isn[25],isn[22]}==2'b00 ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
2140
            default:    fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2141
            endcase
2142
`FLOAT:         fnRb = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
2143
default:    fnRb = {rgs[thrd],1'b0,isn[`INSTRUCTION_RB]};
2144
endcase
2145
endfunction
2146
 
2147
function [RBIT:0] fnRc;
2148
input [47:0] isn;
2149
input [5:0] vqei;
2150
input thrd;
2151
case(isn[`INSTRUCTION_OP])
2152
`R2:    fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
2153
`MEMNDX:        fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};   // SVX not implemented
2154
`IVECTOR:
2155
                        case(isn[`INSTRUCTION_S2])
2156
            `VSxx,`VSxxS,`VSxxU,`VSxxSU:    fnRc = {6'h3F,1'b1,2'b0,isn[25:23]};
2157
            default:    fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
2158
            endcase
2159
`FLOAT:         fnRc = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
2160
default:    fnRc = {rgs[thrd],1'b0,isn[`INSTRUCTION_RC]};
2161
endcase
2162
endfunction
2163
 
2164
function [RBIT:0] fnRt;
2165
input [47:0] isn;
2166
input [5:0] vqei;
2167
input [5:0] vli;
2168
input thrd;
2169
casez(isn[`INSTRUCTION_OP])
2170
`IVECTOR:
2171
                case(isn[`INSTRUCTION_S2])
2172
                `VMxx:
2173
                        case(isn[25:23])
2174
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
2175
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2176
            `VMPOP:     fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2177
            default:
2178
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2179
            endcase
2180
        `VSxx,`VSxxU,`VSxxS,`VSxxSU:    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2181
        `VSHLV:     fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RT]};
2182
        `VSHRV:     fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RT]};
2183
        `VEINS:     fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};    // ToDo: add element # from Ra
2184
        `V2BITS:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2185
        default:    fnRt = {vqei,1'b1,isn[`INSTRUCTION_Rt]};
2186
        endcase
2187
 
2188
`R2:
2189
        if (isn[`INSTRUCTION_L2]==2'b01)
2190
                case(isn[47:42])
2191
          `CMOVEZ:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2192
        `CMOVNZ:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2193
        default:                fnRt = 12'd0;
2194
                endcase
2195
        else
2196
    casez(isn[`INSTRUCTION_S2])
2197
                `MOV:
2198
                        case(isn[25:23])
2199
                        3'd0:   fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RT]};
2200
                        3'd1:   fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2201
                        3'd2:   fnRt = {rs_stack[thrd][5:0],1'b0,isn[`INSTRUCTION_RT]};
2202
                        3'd3:   fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2203
                        3'd4:   fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2204
                        3'd5:   fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2205
                        3'd6:   fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2206
                        default:fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2207
                        endcase
2208
        `VMOV:
2209
            case (isn[`INSTRUCTION_S1])
2210
            5'h0:   fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RT]};
2211
            5'h1:   fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2212
            default:    fnRt = 12'h000;
2213
            endcase
2214
        `R1:
2215
                case(isn[22:18])
2216
                `CNTLO,`CNTLZ,`CNTPOP,`ABS,`NOT,`NEG,`REDOR,`ZXB,`ZXC,`ZXH,`SXB,`SXC,`SXH:
2217
                        fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2218
                `MEMDB,`MEMSB,`SYNC:
2219
                        fnRt = 12'd0;
2220
                default:        fnRt = 12'd0;
2221
                endcase
2222
        `CMOVEZ:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2223
        `CMOVNZ:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2224
        `MUX:       fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2225
        `MIN:       fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2226
        `MAX:       fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2227
        `LVX:       fnRt = {vqei,1'b1,isn[20:16]};
2228
        `SHIFTR:        fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2229
        `SHIFT31,`SHIFT63:
2230
                                fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2231
        `SEI:           fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2232
        `WAIT,`RTI,`CHK:
2233
                        fnRt = 12'd0;
2234
                default:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2235
        endcase
2236
`MEMNDX:
2237
        begin
2238
                if (!isn[31])
2239
                        case({isn[31:28],isn[22:21]})
2240
                        `LVX,
2241
                        `CACHEX,
2242
                        `LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
2243
                        `LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,`LWRX:
2244
                                fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2245
                        default: fnRt = 12'd0;
2246
                        endcase
2247
                else
2248
                        case({isn[31:28],isn[17:16]})
2249
                        `PUSH:  fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2250
                  `SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
2251
                                        fnRt = 12'd0;
2252
                  default:    fnRt = 12'd0;
2253
                  endcase
2254
        end
2255
`FLOAT:
2256
                case(isn[31:26])
2257
                `FTX,`FCX,`FEX,`FDX,`FRM:
2258
                                        fnRt = 12'd0;
2259
                `FSYNC:         fnRt = 12'd0;
2260
                default:        fnRt = {fp_rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2261
                endcase
2262
`BRK:   fnRt = 12'd0;
2263
`REX:   fnRt = 12'd0;
2264
`CHK:   fnRt = 12'd0;
2265 61 robfinch
//`EXEC:        fnRt = 12'd0;
2266 60 robfinch
`Bcc:   fnRt = 12'd0;
2267 61 robfinch
`BLcc:  fnRt = 12'd0;
2268 60 robfinch
`BBc:   fnRt = 12'd0;
2269
`NOP:  fnRt = 12'd0;
2270
`BEQI:  fnRt = 12'd0;
2271 61 robfinch
`BNEI:  fnRt = 12'd0;
2272 60 robfinch
`SB,`Sx,`SWC,`CACHE:
2273
                fnRt = 12'd0;
2274
`JMP:   fnRt = 12'd0;
2275
`CALL:  fnRt = {rgs[thrd],1'b0,5'd29};  // regLR
2276
`LV:    fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};
2277
`AMO:   fnRt = isn[31] ? {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]} : {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2278
`AUIPC,`LUI:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2279
default:    fnRt = {rgs[thrd],1'b0,isn[`INSTRUCTION_RT]};
2280
endcase
2281
endfunction
2282
`else
2283
function [RBIT:0] fnRa;
2284
input [47:0] isn;
2285
input [5:0] vqei;
2286
input [5:0] vli;
2287
input thrd;
2288
case(isn[`INSTRUCTION_OP])
2289
`IVECTOR:
2290
        case(isn[`INSTRUCTION_S2])
2291
  `VCIDX,`VSCAN:  fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
2292
  `VMxx:
2293
        case(isn[25:23])
2294
        `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP,`VMFIRST,`VMLAST:
2295
              fnRa = {6'h3F,1'b1,2'b0,isn[10:8]};
2296
      `VMFILL:fnRa = {6'd0,1'b1,isn[`INSTRUCTION_RA]};
2297
      default:fnRa = {6'h3F,1'b1,2'b0,isn[10:8]};
2298
      endcase
2299
  `VSHLV:     fnRa = (vqei+1+isn[15:11] >= vli) ? 11'h000 : {vli-vqei-isn[15:11]-1,1'b1,isn[`INSTRUCTION_RA]};
2300
  `VSHRV:     fnRa = (vqei+isn[15:11] >= vli) ? 11'h000 : {vqei+isn[15:11],1'b1,isn[`INSTRUCTION_RA]};
2301
  `VSxx,`VSxxU,`VSxxS,`VSxxSU:    fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
2302
  default:    fnRa = {vqei,1'b1,isn[`INSTRUCTION_RA]};
2303
  endcase
2304
`R2:
2305
        casez(isn[`INSTRUCTION_S2])
2306
        `MOV:
2307
                case(isn[25:23])
2308
                3'd0:   fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2309
                3'd1:   fnRa = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RA]};
2310
                3'd2:   fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2311
                3'd3:   fnRa = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RA]};
2312
                3'd4:   fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2313
                3'd5:   fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
2314
                3'd6:   fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
2315
                default:fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2316
                endcase
2317
  `VMOV:
2318
    case (isn[`INSTRUCTION_S1])
2319
    5'h0:   fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2320
    5'h1:   fnRa = {6'h3F,1'b1,isn[`INSTRUCTION_RA]};
2321
    default:    fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2322
    endcase
2323
  default:    fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2324
  endcase
2325
`FLOAT:         fnRa = {fp_rgs,1'b0,isn[`INSTRUCTION_RA]};
2326
default:    fnRa = {rgs,1'b0,isn[`INSTRUCTION_RA]};
2327
endcase
2328
endfunction
2329
 
2330
function [RBIT:0] fnRb;
2331
input [47:0] isn;
2332
input fb;
2333
input [5:0] vqei;
2334
input [5:0] rfoa0i;
2335
input [5:0] rfoa1i;
2336
input thrd;
2337
case(isn[`INSTRUCTION_OP])
2338
`RR:        case(isn[`INSTRUCTION_S2])
2339
            `VEX:       fnRb = fb ? {rfoa1i,1'b1,isn[`INSTRUCTION_RB]} : {rfoa0i,1'b1,isn[`INSTRUCTION_RB]};
2340
            `LVX,`SVX:  fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2341
            default:    fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
2342
            endcase
2343
`IVECTOR:
2344
                        case(isn[`INSTRUCTION_S2])
2345
                        `VMxx:
2346
                                case(isn[25:23])
2347
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
2348
                        fnRb = {6'h3F,1'b1,2'b0,isn[20:18]};
2349
                default:        fnRb = 12'h000;
2350
                endcase
2351
            `VXCHG:     fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2352
            `VSxx,`VSxxU:   fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2353
                `VSxxS,`VSxxSU:    fnRb = {vqei,1'b0,isn[`INSTRUCTION_RB]};
2354
            `VADDS,`VSUBS,`VMULS,`VANDS,`VORS,`VXORS,`VXORS:
2355
                fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
2356
            `VSHL,`VSHR,`VASR:
2357
                fnRb = {isn[25],isn[22]}==2'b00 ? {rgs,1'b0,isn[`INSTRUCTION_RB]} : {vqei,1'b1,isn[`INSTRUCTION_RB]};
2358
            default:    fnRb = {vqei,1'b1,isn[`INSTRUCTION_RB]};
2359
            endcase
2360
`FLOAT:         fnRb = {fp_rgs,1'b0,isn[`INSTRUCTION_RB]};
2361
default:    fnRb = {rgs,1'b0,isn[`INSTRUCTION_RB]};
2362
endcase
2363
endfunction
2364
 
2365
function [RBIT:0] fnRc;
2366
input [47:0] isn;
2367
input [5:0] vqei;
2368
input thrd;
2369
case(isn[`INSTRUCTION_OP])
2370
`R2:    fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
2371
`MEMNDX:        fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]}; // SVX not implemented
2372
`IVECTOR:
2373
                        case(isn[`INSTRUCTION_S2])
2374
            `VSxx,`VSxxS,`VSxxU,`VSxxSU:    fnRc = {6'h3F,1'b1,2'b0,isn[25:23]};
2375
            default:    fnRc = {vqei,1'b1,isn[`INSTRUCTION_RC]};
2376
            endcase
2377
`FLOAT:         fnRc = {fp_rgs,1'b0,isn[`INSTRUCTION_RC]};
2378
default:    fnRc = {rgs,1'b0,isn[`INSTRUCTION_RC]};
2379
endcase
2380
endfunction
2381
 
2382
function [RBIT:0] fnRt;
2383
input [47:0] isn;
2384
input [5:0] vqei;
2385
input [5:0] vli;
2386
input thrd;
2387
casez(isn[`INSTRUCTION_OP])
2388
`IVECTOR:
2389
                case(isn[`INSTRUCTION_S2])
2390
                `VMxx:
2391
                        case(isn[25:23])
2392
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
2393
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2394
            `VMPOP:     fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2395
            default:
2396
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2397
            endcase
2398
        `VSxx,`VSxxU,`VSxxS,`VSxxSU:    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2399
        `VSHLV:     fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RT]};
2400
        `VSHRV:     fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RT]};
2401
        `VEINS:     fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};    // ToDo: add element # from Ra
2402
        `V2BITS:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2403
        default:    fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};
2404
        endcase
2405
 
2406
`FVECTOR:
2407
                case(isn[`INSTRUCTION_S2])
2408
                `VMxx:
2409
                        case(isn[25:23])
2410
                `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMFILL:
2411
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2412
            `VMPOP:     fnRt = {rgs,1'b0,isn[`INSTRUCTION_RB]};
2413
            default:
2414
                    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2415
            endcase
2416
        `VSxx,`VSxxU,`VSxxS,`VSxxSU:    fnRt = {6'h3F,1'b1,2'b0,isn[15:13]};
2417
        `VSHLV:     fnRt = (vqei+1 >= vli) ? 11'h000 : {vli-vqei-1,1'b1,isn[`INSTRUCTION_RT]};
2418
        `VSHRV:     fnRt = (vqei >= vli) ? 11'h000 : {vqei,1'b1,isn[`INSTRUCTION_RT]};
2419
        `VEINS:     fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};    // ToDo: add element # from Ra
2420
        `V2BITS:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2421
        default:    fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};
2422
        endcase
2423
 
2424
`R2:
2425
        if (isn[`INSTRUCTION_L2]==2'b01)
2426
                case(isn[47:42])
2427
          `CMOVEZ:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2428
        `CMOVNZ:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2429
        default:                fnRt = 12'd0;
2430
                endcase
2431
        else
2432
        casez(isn[`INSTRUCTION_S2])
2433
        `MOV:
2434
                case(isn[25:23])
2435
                3'd0:   fnRt = {isn[26],isn[22:18],1'b0,isn[`INSTRUCTION_RT]};
2436
                3'd1:   fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2437
                3'd2:   fnRt = {rs_stack[5:0],1'b0,isn[`INSTRUCTION_RT]};
2438
                3'd3:   fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2439
                3'd4:   fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RT]};
2440
                3'd5:   fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2441
                3'd6:   fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RT]};
2442
                default:fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2443
                endcase
2444
  `VMOV:
2445
    case (isn[`INSTRUCTION_S1])
2446
    5'h0:   fnRt = {6'h3F,1'b1,isn[`INSTRUCTION_RT]};
2447
    5'h1:   fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2448
    default:    fnRt = 12'h000;
2449
    endcase
2450
  `R1:
2451
        case(isn[22:18])
2452
        `CNTLO,`CNTLZ,`CNTPOP,`ABS,`NOT,`NEG,`REDOR,`ZXB,`ZXC,`ZXH,`SXB,`SXC,`SXH:
2453
                fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2454
        `MEMDB,`MEMSB,`SYNC:
2455
                fnRt = 12'd0;
2456
        default:        fnRt = 12'd0;
2457
        endcase
2458
  `MUX:       fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2459
  `MIN:       fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2460
  `MAX:       fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2461
  `LVX:       fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};
2462
  `SHIFTR:      fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2463
  `SHIFT31,`SHIFT63:
2464
                        fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2465
  `SEI:         fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2466
  `WAIT,`RTI,`CHK:
2467
                        fnRt = 12'd0;
2468
  default:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2469
  endcase
2470
`MEMNDX:
2471
        begin
2472
                if (!isn[31])
2473
                        case({isn[31:28],isn[22:21]})
2474
                        `LVX,
2475
                        `CACHEX,
2476
                        `LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
2477
                        `LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,`LWRX:
2478
                                fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2479
                        default: fnRt = 12'd0;
2480
                        endcase
2481
                else
2482
                        case({isn[31:28],isn[17:16]})
2483
                        `PUSH:  fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2484
                  `SBX,`SCX,`SHX,`SWX,`SWCX,`CACHEX:
2485
                                        fnRt = 12'd0;
2486
                  default:    fnRt = 12'd0;
2487
                  endcase
2488
        end
2489
`FLOAT:
2490
                case(isn[31:26])
2491
                `FTX,`FCX,`FEX,`FDX,`FRM:
2492
                                        fnRt = 12'd0;
2493
                `FSYNC:         fnRt = 12'd0;
2494
                default:        fnRt = {fp_rgs,1'b0,isn[`INSTRUCTION_RT]};
2495
                endcase
2496
`BRK:   fnRt = 12'd0;
2497
`REX:   fnRt = 12'd0;
2498
`CHK:   fnRt = 12'd0;
2499 61 robfinch
//`EXEC:        fnRt = 12'd0;
2500 60 robfinch
`Bcc:   fnRt = 12'd0;
2501 61 robfinch
`BLcc:  fnRt = 12'd0;
2502 60 robfinch
`BBc:   fnRt = 12'd0;
2503
`NOP:  fnRt = 12'd0;
2504
`BEQI:  fnRt = 12'd0;
2505 61 robfinch
`BNEI:  fnRt = 12'd0;
2506 60 robfinch
`SB,`Sx,`SWC,`CACHE:
2507
                fnRt = 12'd0;
2508
`JMP:   fnRt = 12'd0;
2509
`CALL:  fnRt = {rgs,1'b0,5'd29};        // regLR
2510
`LV:    fnRt = {vqei,1'b1,isn[`INSTRUCTION_RT]};
2511
`AMO:   fnRt = isn[31] ? {rgs,1'b0,isn[`INSTRUCTION_RT]} : {rgs,1'b0,isn[`INSTRUCTION_RT]};
2512
`AUIPC,`LUI:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2513
default:    fnRt = {rgs,1'b0,isn[`INSTRUCTION_RT]};
2514
endcase
2515
endfunction
2516
`endif
2517
 
2518
// Determines which lanes of the target register get updated.
2519
// Duh, all the lanes.
2520
function [7:0] fnWe;
2521
input [47:0] isn;
2522
casez(isn[`INSTRUCTION_OP])
2523
`R2:
2524
        case(isn[`INSTRUCTION_S2])
2525
        `CMP:   fnWe = 8'h00;
2526
        default: fnWe = 8'hFF;
2527
        endcase
2528
default: fnWe = 8'hFF;
2529
endcase
2530
/*
2531
casez(isn[`INSTRUCTION_OP])
2532
`R2:
2533
        case(isn[`INSTRUCTION_S2])
2534
        `R1:
2535
                case(isn[22:18])
2536
                `ABS,`CNTLZ,`CNTLO,`CNTPOP:
2537
                        case(isn[25:23])
2538
                        3'b000: fnWe = 8'h01;
2539
                        3'b001: fnWe = 8'h03;
2540
                        3'b010: fnWe = 8'h0F;
2541
                        3'b011: fnWe = 8'hFF;
2542
                        default:        fnWe = 8'hFF;
2543
                        endcase
2544
                default: fnWe = 8'hFF;
2545
                endcase
2546
        `SHIFT31:       fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
2547
        `SHIFT63:       fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
2548
        `SLT,`SLTU,`SLE,`SLEU,
2549
        `ADD,`SUB,
2550
        `AND,`OR,`XOR,
2551
        `NAND,`NOR,`XNOR,
2552
        `DIV,`DIVU,`DIVSU,
2553
        `MOD,`MODU,`MODSU,
2554
        `MUL,`MULU,`MULSU,
2555
        `MULH,`MULUH,`MULSUH,
2556
        `FXMUL:
2557
                case(isn[25:23])
2558
                3'b000: fnWe = 8'h01;
2559
                3'b001: fnWe = 8'h03;
2560
                3'b010: fnWe = 8'h0F;
2561
                3'b011: fnWe = 8'hFF;
2562
                default:        fnWe = 8'hFF;
2563
                endcase
2564
        default: fnWe = 8'hFF;
2565
        endcase
2566
default:        fnWe = 8'hFF;
2567
endcase
2568
*/
2569
endfunction
2570
 
2571
// Detect if a source is automatically valid
2572
function Source1Valid;
2573
input [47:0] isn;
2574
casez(isn[`INSTRUCTION_OP])
2575
`BRK:   Source1Valid = isn[16] ? isn[`INSTRUCTION_RA]==5'd0 : TRUE;
2576
`Bcc:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2577 61 robfinch
`BLcc:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2578 60 robfinch
`BBc:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2579
`BEQI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2580 61 robfinch
`BNEI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2581 60 robfinch
`CHK:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2582
`RR:    case(isn[`INSTRUCTION_S2])
2583
        `SHIFT31:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2584
        `SHIFT63:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2585
        `SHIFTR:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2586
        default:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2587
        endcase
2588
`MEMNDX:Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2589
`ADDI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2590 61 robfinch
`SEQI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2591 60 robfinch
`SLTI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2592
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2593
`SGTI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2594
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2595
`ANDI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2596
`ORI:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2597
`XORI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2598
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2599
`MULI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2600
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2601
`MULFI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2602
`DIVI:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2603
`DIVUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2604
`AMO:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2605
`LB:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2606
`LBU:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2607
`Lx:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2608
`LxU:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2609
`LWR:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2610
`LV:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2611
`LVx:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2612
`LVxU:  Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2613
`SB:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2614
`Sx:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2615
`SWC:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2616
`SV:    Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2617 61 robfinch
`PUSHC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2618 60 robfinch
`INC:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2619
`CAS:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2620
`CACHE: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2621
`JAL:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2622
`RET:   Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2623
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
2624
`BITFIELD:      case(isn[47:44])
2625
        `BFINSI:        Source1Valid = TRUE;
2626
        default:        Source1Valid = isn[`INSTRUCTION_RA]==5'd0 || isn[30]==1'b0;
2627
        endcase
2628
`IVECTOR:
2629
        Source1Valid = FALSE;
2630
default:    Source1Valid = TRUE;
2631
endcase
2632
endfunction
2633
 
2634
function Source2Valid;
2635
input [47:0] isn;
2636
casez(isn[`INSTRUCTION_OP])
2637
`BRK:   Source2Valid = TRUE;
2638
`Bcc:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2639 61 robfinch
`BLcc:  Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2640 60 robfinch
`BBc:   Source2Valid = TRUE;
2641
`BEQI:  Source2Valid = TRUE;
2642 61 robfinch
`BNEI:  Source2Valid = TRUE;
2643 60 robfinch
`CHK:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2644
`R2:    casez(isn[`INSTRUCTION_S2])
2645
                                `TLB:                           Source2Valid = TRUE;
2646
        `R1:            Source2Valid = TRUE;
2647
        `MOV:                           Source2Valid = TRUE;
2648 61 robfinch
        `SHIFT31:       Source2Valid = TRUE;
2649
        `SHIFT63:       Source2Valid = TRUE;
2650 60 robfinch
        `LVX,`SVX:      Source2Valid = FALSE;
2651
        default:        Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2652
        endcase
2653
`MEMNDX:
2654
        begin
2655
                if (!isn[31])
2656
                        case({isn[31:28],isn[22:21]})
2657
                        `LVX: Source2Valid = FALSE;
2658
                        `CACHEX,
2659
                        `LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
2660
                        `LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,`LWRX:    Source2Valid = TRUE;
2661
                        default:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2662
                        endcase
2663
                else
2664
                        case({isn[31:28],isn[17:16]})
2665
                        `SVX: Source2Valid = FALSE;
2666
                        default:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2667
                        endcase
2668
        end
2669
`ADDI:  Source2Valid = TRUE;
2670 61 robfinch
`SEQI:  Source2Valid = TRUE;
2671 60 robfinch
`SLTI:  Source2Valid = TRUE;
2672
`SLTUI: Source2Valid = TRUE;
2673
`SGTI:  Source2Valid = TRUE;
2674
`SGTUI: Source2Valid = TRUE;
2675
`ANDI:  Source2Valid = TRUE;
2676
`ORI:   Source2Valid = TRUE;
2677
`XORI:  Source2Valid = TRUE;
2678
`XNORI: Source2Valid = TRUE;
2679
`MULUI: Source2Valid = TRUE;
2680
`MULFI: Source2Valid = TRUE;
2681
`LB:    Source2Valid = TRUE;
2682
`LBU:   Source2Valid = TRUE;
2683
`Lx:    Source2Valid = TRUE;
2684
`LxU:   Source2Valid = TRUE;
2685
`LWR:   Source2Valid = TRUE;
2686
`LVx:   Source2Valid = TRUE;
2687
`LVxU:  Source2Valid = TRUE;
2688
`INC:           Source2Valid = TRUE;
2689
`SB:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2690
`Sx:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2691
`SWC:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2692 61 robfinch
`PUSHC: Source2Valid = TRUE;
2693 60 robfinch
`CAS:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2694
`JAL:   Source2Valid = TRUE;
2695
`RET:   Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2696
`IVECTOR:
2697
                    case(isn[`INSTRUCTION_S2])
2698
        `VABS:  Source2Valid = TRUE;
2699
        `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
2700
            Source2Valid = FALSE;
2701
        `VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
2702
            Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2703
        `VBITS2V:   Source2Valid = TRUE;
2704
        `V2BITS:    Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
2705
        `VSHL,`VSHR,`VASR:  Source2Valid = isn[22:21]==2'd2;
2706
        default:    Source2Valid = FALSE;
2707
        endcase
2708
`LV:        Source2Valid = TRUE;
2709
`SV:        Source2Valid = FALSE;
2710
`AMO:           Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
2711
`BITFIELD:      Source2Valid = isn[`INSTRUCTION_RB]==5'd0 || isn[31]==1'b0;
2712
default:    Source2Valid = TRUE;
2713
endcase
2714
endfunction
2715
 
2716
function Source3Valid;
2717
input [47:0] isn;
2718
case(isn[`INSTRUCTION_OP])
2719
`IVECTOR:
2720
    case(isn[`INSTRUCTION_S2])
2721
    `VEX:       Source3Valid = TRUE;
2722
    default:    Source3Valid = TRUE;
2723
    endcase
2724
`CHK:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2725
`R2:
2726
        if (isn[`INSTRUCTION_L2]==2'b01)
2727
                case(isn[47:42])
2728
    `CMOVEZ,`CMOVNZ:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2729
                default:        Source3Valid = TRUE;
2730
                endcase
2731
        else
2732
    case(isn[`INSTRUCTION_S2])
2733
    `MAJ:               Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2734
    default:    Source3Valid = TRUE;
2735
    endcase
2736
`MEMNDX:
2737
                if (!isn[31])
2738
                        case({isn[31:28],isn[22:21]})
2739
                        `CACHEX,
2740
                        `LVBX,`LVBUX,`LVCX,`LVCUX,`LVHX,`LVHUX,`LVWX,
2741
                        `LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,`LWRX:
2742
                                Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2743
            default:    Source3Valid = TRUE;
2744
                        endcase
2745
                else
2746
            case({isn[31:28],isn[17:16]})
2747
            `PUSH:      Source3Valid = TRUE;
2748
            `SBX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2749
            `SCX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2750
            `SHX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2751
            `SWX:   Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2752
            `SWCX:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2753
            `CASX:  Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
2754
            default:    Source3Valid = TRUE;
2755
            endcase
2756
`BITFIELD:      Source3Valid = isn[`INSTRUCTION_RC]==5'd0 || isn[32]==1'b0;
2757
default:    Source3Valid = TRUE;
2758
endcase
2759
endfunction
2760
 
2761
 
2762
// Used to indicate to the queue logic that the instruction needs to be
2763
// recycled to the queue VL number of times.
2764
function IsVector;
2765
input [47:0] isn;
2766
case(isn[`INSTRUCTION_OP])
2767
`MEMNDX:
2768
  case(isn[`INSTRUCTION_S2])
2769
  `LVX,`SVX:  IsVector = TRUE;
2770
  default:    IsVector = FALSE;
2771
  endcase
2772
`IVECTOR:
2773
        case(isn[`INSTRUCTION_S2])
2774
        `VMxx:
2775
                case(isn[25:23])
2776
        `VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
2777
              IsVector = FALSE;
2778
    default:    IsVector = TRUE;
2779
    endcase
2780
  `VEINS:     IsVector = FALSE;
2781
  `VEX:       IsVector = FALSE;
2782
  default:    IsVector = TRUE;
2783
  endcase
2784
`LV,`SV:    IsVector = TRUE;
2785
default:    IsVector = FALSE;
2786
endcase
2787
endfunction
2788
 
2789
function IsVeins;
2790
input [47:0] isn;
2791
case(isn[`INSTRUCTION_OP])
2792
`IVECTOR:   IsVeins = isn[`INSTRUCTION_S2]==`VEINS;
2793
default:    IsVeins = FALSE;
2794
endcase
2795
endfunction
2796
 
2797
function IsVex;
2798
input [47:0] isn;
2799
case(isn[`INSTRUCTION_OP])
2800
`IVECTOR:   IsVex = isn[`INSTRUCTION_S2]==`VEX;
2801
default:    IsVex = FALSE;
2802
endcase
2803
endfunction
2804
 
2805
function IsVCmprss;
2806
input [47:0] isn;
2807
case(isn[`INSTRUCTION_OP])
2808
`IVECTOR:   IsVCmprss = isn[`INSTRUCTION_S2]==`VCMPRSS || isn[`INSTRUCTION_S2]==`VCIDX;
2809
default:    IsVCmprss = FALSE;
2810
endcase
2811
endfunction
2812
 
2813
function IsVShifti;
2814
input [47:0] isn;
2815
case(isn[`INSTRUCTION_OP])
2816
`IVECTOR:
2817
                    case(isn[`INSTRUCTION_S2])
2818
            `VSHL,`VSHR,`VASR:
2819
                IsVShifti = {isn[25],isn[22]}==2'd2;
2820
            default:    IsVShifti = FALSE;
2821
            endcase
2822
default:    IsVShifti = FALSE;
2823
endcase
2824
endfunction
2825
 
2826
function IsVLS;
2827
input [47:0] isn;
2828
case(isn[`INSTRUCTION_OP])
2829
`MEMNDX:
2830
                if (IsLoad(isn))
2831
            case({isn[31:28],isn[22:21]})
2832
            `LVX,`LVWS:  IsVLS = TRUE;
2833
            default:    IsVLS = FALSE;
2834
            endcase
2835
    else
2836
            case({isn[31:28],isn[17:16]})
2837
            `SVX,`SVWS:  IsVLS = TRUE;
2838
            default:    IsVLS = FALSE;
2839
            endcase
2840
`LV,`SV:    IsVLS = TRUE;
2841
default:    IsVLS = FALSE;
2842
endcase
2843
endfunction
2844
 
2845
function [1:0] fnM2;
2846
input [31:0] isn;
2847
case(isn[`INSTRUCTION_OP])
2848
`RR:    fnM2 = isn[24:23];
2849
default:    fnM2 = 2'b00;
2850
endcase
2851
endfunction
2852
 
2853 61 robfinch
function IsMem;
2854 60 robfinch
input [47:0] isn;
2855
case(isn[`INSTRUCTION_OP])
2856
`MEMNDX:        IsMem = TRUE;
2857
`AMO:   IsMem = TRUE;
2858
`LB:    IsMem = TRUE;
2859
`LBU:   IsMem = TRUE;
2860
`Lx:    IsMem = TRUE;
2861
`LxU:   IsMem = TRUE;
2862
`LWR:   IsMem = TRUE;
2863
`LV,`SV:    IsMem = TRUE;
2864
`INC:           IsMem = TRUE;
2865
`SB:    IsMem = TRUE;
2866
`Sx:    IsMem = TRUE;
2867
`SWC:   IsMem = TRUE;
2868 61 robfinch
`PUSHC: IsMem = TRUE;
2869 60 robfinch
`CAS:   IsMem = TRUE;
2870
`LVx:           IsMem = TRUE;
2871
`LVxU:  IsMem = TRUE;
2872
default:    IsMem = FALSE;
2873
endcase
2874
endfunction
2875
 
2876
function IsMemNdx;
2877
input [47:0] isn;
2878
case(isn[`INSTRUCTION_OP])
2879
`MEMNDX:        IsMemNdx = TRUE;
2880
default:    IsMemNdx = FALSE;
2881
endcase
2882
endfunction
2883
 
2884
function IsLoad;
2885
input [47:0] isn;
2886
case(isn[`INSTRUCTION_OP])
2887
`MEMNDX:        IsLoad = !isn[31];
2888
`LB:    IsLoad = TRUE;
2889
`LBU:   IsLoad = TRUE;
2890
`Lx:    IsLoad = TRUE;
2891
`LxU:   IsLoad = TRUE;
2892
`LWR:   IsLoad = TRUE;
2893
`LV:    IsLoad = TRUE;
2894
`LVx:   IsLoad = TRUE;
2895
`LVxU:  IsLoad = TRUE;
2896
default:    IsLoad = FALSE;
2897
endcase
2898
endfunction
2899
 
2900
function IsInc;
2901
input [47:0] isn;
2902
case(isn[`INSTRUCTION_OP])
2903
`MEMNDX:
2904
        if (isn[`INSTRUCTION_L2]==2'b00)
2905
                case({isn[31:28],isn[17:16]})
2906
    `INC:   IsInc = TRUE;
2907
    default:    IsInc = FALSE;
2908
    endcase
2909
        else
2910
                IsInc = FALSE;
2911
`INC:    IsInc = TRUE;
2912
default:    IsInc = FALSE;
2913
endcase
2914
endfunction
2915
 
2916
function IsSWC;
2917
input [47:0] isn;
2918
case(isn[`INSTRUCTION_OP])
2919
`MEMNDX:
2920
        if (isn[`INSTRUCTION_L2]==2'b00)
2921
                case({isn[31:28],isn[17:16]})
2922
    `SWCX:   IsSWC = TRUE;
2923
    default:    IsSWC = FALSE;
2924
    endcase
2925
        else
2926
                IsSWC = FALSE;
2927
`SWC:    IsSWC = TRUE;
2928
default:    IsSWC = FALSE;
2929
endcase
2930
endfunction
2931
 
2932
// Aquire / release bits are only available on indexed SWC / LWR
2933
function IsSWCX;
2934
input [47:0] isn;
2935
case(isn[`INSTRUCTION_OP])
2936
`MEMNDX:
2937
        if (isn[`INSTRUCTION_L2]==2'b00)
2938
                case({isn[31:28],isn[17:16]})
2939
    `SWCX:   IsSWCX = TRUE;
2940
    default:    IsSWCX = FALSE;
2941
    endcase
2942
        else
2943
                IsSWCX = FALSE;
2944
default:    IsSWCX = FALSE;
2945
endcase
2946
endfunction
2947
 
2948
function IsLWR;
2949
input [47:0] isn;
2950
case(isn[`INSTRUCTION_OP])
2951
`MEMNDX:
2952
        if (isn[`INSTRUCTION_L2]==2'b00)
2953
            case({isn[31:28],isn[22:21]})
2954
            `LWRX:   IsLWR = TRUE;
2955
            default:    IsLWR = FALSE;
2956
            endcase
2957
        else
2958
                IsLWR = FALSE;
2959
`LWR:    IsLWR = TRUE;
2960
default:    IsLWR = FALSE;
2961
endcase
2962
endfunction
2963
 
2964
function IsLWRX;
2965
input [47:0] isn;
2966
case(isn[`INSTRUCTION_OP])
2967
`MEMNDX:
2968
        if (isn[`INSTRUCTION_L2]==2'b00)
2969
            case({isn[31:28],isn[22:21]})
2970
            `LWRX:   IsLWRX = TRUE;
2971
            default:    IsLWRX = FALSE;
2972
            endcase
2973
        else
2974
                IsLWRX = FALSE;
2975
default:    IsLWRX = FALSE;
2976
endcase
2977
endfunction
2978
 
2979
function IsCAS;
2980
input [47:0] isn;
2981
case(isn[`INSTRUCTION_OP])
2982
`MEMNDX:
2983
        if (isn[`INSTRUCTION_L2]==2'b00)
2984
                case({isn[31:28],isn[17:16]})
2985
    `CASX:   IsCAS = TRUE;
2986
    default:    IsCAS = FALSE;
2987
    endcase
2988
        else
2989
                IsCAS = FALSE;
2990
`CAS:       IsCAS = TRUE;
2991
default:    IsCAS = FALSE;
2992
endcase
2993
endfunction
2994
 
2995
function IsAMO;
2996
input [47:0] isn;
2997
case(isn[`INSTRUCTION_OP])
2998
`AMO:       IsAMO = TRUE;
2999
default:    IsAMO = FALSE;
3000
endcase
3001
endfunction
3002
 
3003
// Really IsPredictableBranch
3004
// Does not include BccR's
3005
function IsBranch;
3006
input [47:0] isn;
3007
casez(isn[`INSTRUCTION_OP])
3008
`Bcc:   IsBranch = TRUE;
3009 61 robfinch
`BLcc:  IsBranch = TRUE;
3010 60 robfinch
`BBc:   IsBranch = TRUE;
3011
`BEQI:  IsBranch = TRUE;
3012 61 robfinch
`BNEI:  IsBranch = TRUE;
3013 60 robfinch
`CHK:   IsBranch = TRUE;
3014
default:    IsBranch = FALSE;
3015
endcase
3016
endfunction
3017
 
3018
function IsWait;
3019
input [47:0] isn;
3020
IsWait = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`WAIT;
3021
endfunction
3022
 
3023
function IsCall;
3024
input [47:0] isn;
3025
IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
3026
endfunction
3027
 
3028
function IsJmp;
3029
input [47:0] isn;
3030
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
3031
endfunction
3032
 
3033
function IsFlowCtrl;
3034
input [47:0] isn;
3035
casez(isn[`INSTRUCTION_OP])
3036
`BRK:    IsFlowCtrl = TRUE;
3037
`R2:    case(isn[`INSTRUCTION_S2])
3038
        `RTI:   IsFlowCtrl = TRUE;
3039
        default:    IsFlowCtrl = FALSE;
3040
        endcase
3041
`Bcc:   IsFlowCtrl = TRUE;
3042 61 robfinch
`BLcc:  IsFlowCtrl = TRUE;
3043 60 robfinch
`BBc:           IsFlowCtrl = TRUE;
3044
`BEQI:  IsFlowCtrl = TRUE;
3045 61 robfinch
`BNEI:  IsFlowCtrl = TRUE;
3046 60 robfinch
`CHK:   IsFlowCtrl = TRUE;
3047
`JAL:   IsFlowCtrl = TRUE;
3048
`JMP:           IsFlowCtrl = TRUE;
3049
`CALL:  IsFlowCtrl = TRUE;
3050
`RET:   IsFlowCtrl = TRUE;
3051
default:    IsFlowCtrl = FALSE;
3052
endcase
3053
endfunction
3054
 
3055
function IsCache;
3056
input [47:0] isn;
3057
case(isn[`INSTRUCTION_OP])
3058
`MEMNDX:
3059
        if (isn[`INSTRUCTION_L2]==2'b00)
3060
            case({isn[31:28],isn[22:21]})
3061
            `CACHEX:    IsCache = TRUE;
3062
            default:    IsCache = FALSE;
3063
            endcase
3064
        else
3065
                IsCache = FALSE;
3066
`CACHE: IsCache = TRUE;
3067
default: IsCache = FALSE;
3068
endcase
3069
endfunction
3070
 
3071
function [4:0] CacheCmd;
3072
input [47:0] isn;
3073
case(isn[`INSTRUCTION_OP])
3074
`MEMNDX:
3075
        if (isn[`INSTRUCTION_L2]==2'b00)
3076
            case({isn[31:28],isn[22:21]})
3077
            `CACHEX:    CacheCmd = isn[17:13];
3078
            default:    CacheCmd = 5'd0;
3079
            endcase
3080
        else
3081
                CacheCmd = 5'd0;
3082 66 robfinch
`CACHE: CacheCmd = isn[17:13];
3083 60 robfinch
default: CacheCmd = 5'd0;
3084
endcase
3085
endfunction
3086
 
3087
function IsMemsb;
3088
input [47:0] isn;
3089
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
3090
endfunction
3091
 
3092
function IsSEI;
3093
input [47:0] isn;
3094
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
3095
endfunction
3096
 
3097
function IsLV;
3098
input [47:0] isn;
3099
case(isn[`INSTRUCTION_OP])
3100
`MEMNDX:
3101
        if (isn[`INSTRUCTION_L2]==2'b00)
3102
            case({isn[31:28],isn[22:21]})
3103
            `LVX:   IsLV = TRUE;
3104
            default:    IsLV = FALSE;
3105
            endcase
3106
        else
3107
                IsLV = FALSE;
3108
`LV:        IsLV = TRUE;
3109
default:    IsLV = FALSE;
3110
endcase
3111
endfunction
3112
 
3113 61 robfinch
function IsRet;
3114
input [47:0] isn;
3115
IsRet = isn[`INSTRUCTION_OP]==`RET;
3116
endfunction
3117
 
3118 60 robfinch
function IsRFW;
3119
input [47:0] isn;
3120
input [5:0] vqei;
3121
input [5:0] vli;
3122
input thrd;
3123
if (fnRt(isn,vqei,vli,thrd)==12'd0)
3124
    IsRFW = FALSE;
3125
else
3126
casez(isn[`INSTRUCTION_OP])
3127
`IVECTOR:   IsRFW = TRUE;
3128
`FVECTOR:   IsRFW = TRUE;
3129
`R2:
3130
        if (isn[`INSTRUCTION_L2]==2'b00)
3131
            casez(isn[`INSTRUCTION_S2])
3132
            `TLB:               IsRFW = TRUE;
3133
            `R1:
3134
                case(isn[22:18])
3135
                `MEMDB,`MEMSB,`SYNC,`SETWB,5'h14,5'h15: IsRFW = FALSE;
3136
                default:        IsRFW = TRUE;
3137
                endcase
3138
            `ADD:   IsRFW = TRUE;
3139
            `SUB:   IsRFW = TRUE;
3140 61 robfinch
            `SEQ:   IsRFW = TRUE;
3141 60 robfinch
            `SLT:   IsRFW = TRUE;
3142
            `SLTU:  IsRFW = TRUE;
3143
            `SLE:   IsRFW = TRUE;
3144
        `SLEU:  IsRFW = TRUE;
3145
            `AND:   IsRFW = TRUE;
3146
            `OR:    IsRFW = TRUE;
3147
            `XOR:   IsRFW = TRUE;
3148
            `NAND:      IsRFW = TRUE;
3149
            `NOR:               IsRFW = TRUE;
3150
            `XNOR:      IsRFW = TRUE;
3151
            `MULU:  IsRFW = TRUE;
3152
            `MULSU: IsRFW = TRUE;
3153
            `MUL:   IsRFW = TRUE;
3154
            `MULUH:  IsRFW = TRUE;
3155
            `MULSUH: IsRFW = TRUE;
3156
            `MULH:   IsRFW = TRUE;
3157
            `MULF:      IsRFW = TRUE;
3158
            `FXMUL:     IsRFW = TRUE;
3159
            `DIVU:  IsRFW = TRUE;
3160
            `DIVSU: IsRFW = TRUE;
3161
            `DIV:IsRFW = TRUE;
3162
            `MODU:  IsRFW = TRUE;
3163
            `MODSU: IsRFW = TRUE;
3164
            `MOD:IsRFW = TRUE;
3165
            `MOV:       IsRFW = TRUE;
3166
            `VMOV:      IsRFW = TRUE;
3167
            `SHIFTR,`SHIFT31,`SHIFT63:
3168
                        IsRFW = TRUE;
3169
            `MIN,`MAX:    IsRFW = TRUE;
3170
            `SEI:       IsRFW = TRUE;
3171
            default:    IsRFW = FALSE;
3172
            endcase
3173
        else if (isn[`INSTRUCTION_L2]==2'b01)
3174
                case(isn[47:42])
3175
                `CMOVEZ:        IsRFW = TRUE;
3176
                `CMOVNZ:        IsRFW = TRUE;
3177
                default:        IsRFW = FALSE;
3178
                endcase
3179
        else if (isn[7]==1'b1)
3180
        // The following instructions might come from a compressed version.
3181
            casez(isn[`INSTRUCTION_S2])
3182
            `ADD:   IsRFW = TRUE;
3183
            `SUB:   IsRFW = TRUE;
3184
            `AND:   IsRFW = TRUE;
3185
            `OR:    IsRFW = TRUE;
3186
            `XOR:   IsRFW = TRUE;
3187
            `MOV:       IsRFW = TRUE;
3188
            `SHIFTR,`SHIFT31,`SHIFT63:
3189
                        IsRFW = TRUE;
3190
            default:    IsRFW = FALSE;
3191
            endcase
3192
        else
3193
                IsRFW = FALSE;
3194
`MEMNDX:
3195
        if (isn[`INSTRUCTION_L2]==2'b10) begin
3196
                if (!isn[31])
3197
                        IsRFW = TRUE;
3198
                else
3199
                        case({isn[31:28],isn[17:16]})
3200
                        `PUSH:  IsRFW = TRUE;
3201
            `CASX:  IsRFW = TRUE;
3202
            default:    IsRFW = FALSE;
3203
            endcase
3204
        end
3205
        else if (isn[`INSTRUCTION_L2]==2'b00) begin
3206
                if (!isn[31])
3207
            case({isn[31:28],isn[22:21]})
3208
            `LBX:   IsRFW = TRUE;
3209
            `LBUX:  IsRFW = TRUE;
3210
            `LCX:   IsRFW = TRUE;
3211
            `LCUX:  IsRFW = TRUE;
3212
            `LHX:   IsRFW = TRUE;
3213
            `LHUX:  IsRFW = TRUE;
3214
            `LWX:   IsRFW = TRUE;
3215
            `LVBX:  IsRFW = TRUE;
3216
            `LVBUX: IsRFW = TRUE;
3217
            `LVCX:  IsRFW = TRUE;
3218
            `LVCUX: IsRFW = TRUE;
3219
            `LVHX:  IsRFW = TRUE;
3220
            `LVHUX: IsRFW = TRUE;
3221
            `LVWX:  IsRFW = TRUE;
3222
            `LWRX:  IsRFW = TRUE;
3223
            `LVX:   IsRFW = TRUE;
3224
            default:    IsRFW = FALSE;
3225
            endcase
3226
    else
3227
                        case({isn[31:28],isn[17:16]})
3228
                        `PUSH:  IsRFW = TRUE;
3229
            `CASX:  IsRFW = TRUE;
3230
            default:    IsRFW = FALSE;
3231
            endcase
3232
        end
3233
        else
3234
                IsRFW = FALSE;
3235
`BBc:   IsRFW = FALSE;
3236
`BITFIELD:  IsRFW = TRUE;
3237
`ADDI:      IsRFW = TRUE;
3238 61 robfinch
`SEQI:      IsRFW = TRUE;
3239 60 robfinch
`SLTI:      IsRFW = TRUE;
3240
`SLTUI:     IsRFW = TRUE;
3241
`SGTI:      IsRFW = TRUE;
3242
`SGTUI:     IsRFW = TRUE;
3243
`ANDI:      IsRFW = TRUE;
3244
`ORI:       IsRFW = TRUE;
3245
`XORI:      IsRFW = TRUE;
3246
`XNORI:                 IsRFW = TRUE;
3247
`MULUI:     IsRFW = TRUE;
3248
`MULI:      IsRFW = TRUE;
3249
`MULFI:                 IsRFW = TRUE;
3250
`DIVUI:     IsRFW = TRUE;
3251
`DIVI:      IsRFW = TRUE;
3252
`MODI:      IsRFW = TRUE;
3253
`JAL:       IsRFW = TRUE;
3254
`CALL:      IsRFW = TRUE;
3255
`RET:       IsRFW = TRUE;
3256
`LB:        IsRFW = TRUE;
3257
`LBU:       IsRFW = TRUE;
3258
`Lx:        IsRFW = TRUE;
3259
`LxU:       IsRFW = TRUE;
3260
`LWR:       IsRFW = TRUE;
3261
`LV:        IsRFW = TRUE;
3262
`LVx:                           IsRFW = TRUE;
3263
`LVxU:                  IsRFW = TRUE;
3264 61 robfinch
`PUSHC:                 IsRFW = TRUE;
3265 60 robfinch
`CAS:       IsRFW = TRUE;
3266
`AMO:                           IsRFW = TRUE;
3267
`CSRRW:                 IsRFW = TRUE;
3268
`AUIPC:                 IsRFW = TRUE;
3269
`LUI:                           IsRFW = TRUE;
3270
default:    IsRFW = FALSE;
3271
endcase
3272
endfunction
3273
 
3274
function IsShifti;
3275
input [47:0] isn;
3276
case(isn[`INSTRUCTION_OP])
3277
`R2:
3278
        if (isn[`INSTRUCTION_L2]==2'b00)
3279
            case(isn[`INSTRUCTION_S2])
3280
            `SHIFT31,`SHIFT63:
3281
                IsShifti = TRUE;
3282
            default: IsShifti = FALSE;
3283
            endcase
3284
    else
3285
        IsShifti = FALSE;
3286
default: IsShifti = FALSE;
3287
endcase
3288
endfunction
3289
 
3290
function IsShift;
3291
input [47:0] isn;
3292
case(isn[`INSTRUCTION_OP])
3293
`R2:
3294
        if (isn[`INSTRUCTION_L2]==2'b00)
3295
    case(isn[31:26])
3296
    `SHIFTR: IsShift = TRUE;
3297
    `SHIFT31: IsShift = TRUE;
3298
    `SHIFT63: IsShift = TRUE;
3299
    default: IsShift = FALSE;
3300
    endcase
3301
  else
3302
        IsShift = FALSE;
3303
default: IsShift = FALSE;
3304
endcase
3305
endfunction
3306
 
3307
function IsShift48;
3308
input [47:0] isn;
3309
case(isn[`INSTRUCTION_OP])
3310
`R2:
3311
        if (isn[`INSTRUCTION_L2]==2'b01)
3312
    case(isn[47:42])
3313
    `SHIFTR: IsShift48 = TRUE;
3314
    default: IsShift48 = FALSE;
3315
    endcase
3316
  else
3317
        IsShift48 = FALSE;
3318
default: IsShift48 = FALSE;
3319
endcase
3320
endfunction
3321
 
3322
function IsRtop;
3323
input [47:0] isn;
3324
case(isn[`INSTRUCTION_OP])
3325
`R2:
3326
        if (isn[`INSTRUCTION_L2]==2'b01)
3327
            case(isn[47:42])
3328
            `RTOP: IsRtop = TRUE;
3329
            default: IsRtop = FALSE;
3330
            endcase
3331
    else
3332
        IsRtop = FALSE;
3333
default: IsRtop = FALSE;
3334
endcase
3335
endfunction
3336
 
3337
function IsMul;
3338
input [47:0] isn;
3339
case(isn[`INSTRUCTION_OP])
3340
`R2:
3341
        if (isn[`INSTRUCTION_L2]==2'b00)
3342
    case(isn[`INSTRUCTION_S2])
3343
    `MULU,`MULSU,`MUL: IsMul = TRUE;
3344
    `MULUH,`MULSUH,`MULH: IsMul = TRUE;
3345
    default:    IsMul = FALSE;
3346
    endcase
3347
        else
3348
                IsMul = FALSE;
3349
`MULUI,`MULI:  IsMul = TRUE;
3350
default:    IsMul = FALSE;
3351
endcase
3352
endfunction
3353
 
3354
function IsDivmod;
3355
input [47:0] isn;
3356
case(isn[`INSTRUCTION_OP])
3357
`R2:
3358
        if (isn[`INSTRUCTION_L2]==2'b00)
3359
    case(isn[`INSTRUCTION_S2])
3360
    `DIVU,`DIVSU,`DIV: IsDivmod = TRUE;
3361
    `MODU,`MODSU,`MOD: IsDivmod = TRUE;
3362
    default: IsDivmod = FALSE;
3363
    endcase
3364
        else
3365
                IsDivmod = FALSE;
3366
`DIVUI,`DIVI,`MODI:  IsDivmod = TRUE;
3367
default:    IsDivmod = FALSE;
3368
endcase
3369
endfunction
3370
 
3371
function [7:0] fnSelect;
3372
input [47:0] ins;
3373
input [`ABITS] adr;
3374
begin
3375
        case(ins[`INSTRUCTION_OP])
3376
        `MEMNDX:
3377
                if (ins[`INSTRUCTION_L2]==2'b10) begin
3378
                        if (ins[31]) begin
3379
                                case({ins[31:28],ins[17:16]})
3380
                                `PUSH:  fnSelect = 8'hFF;
3381
                                default: fnSelect = 8'h00;
3382
                                endcase
3383
                        end
3384
                        else
3385
                                fnSelect = 8'h00;
3386
                end
3387
                else if (ins[`INSTRUCTION_L2]==2'b00) begin
3388
                        if (!ins[31])
3389
                                case({ins[31:28],ins[22:21]})
3390
                                `LBX,`LBUX,`LVBX,`LVBUX:
3391
                                   case(adr[2:0])
3392
                                   3'd0:    fnSelect = 8'h01;
3393
                                   3'd1:    fnSelect = 8'h02;
3394
                                   3'd2:    fnSelect = 8'h04;
3395
                                   3'd3:    fnSelect = 8'h08;
3396
                                   3'd4:    fnSelect = 8'h10;
3397
                                   3'd5:    fnSelect = 8'h20;
3398
                                   3'd6:    fnSelect = 8'h40;
3399
                                   3'd7:    fnSelect = 8'h80;
3400
                                   endcase
3401
                                `LCX,`LCUX,`LVCX,`LVCUX:
3402
                                    case(adr[2:1])
3403
                                    2'd0:   fnSelect = 8'h03;
3404
                                    2'd1:   fnSelect = 8'h0C;
3405
                                    2'd2:   fnSelect = 8'h30;
3406
                                    2'd3:   fnSelect = 8'hC0;
3407
                                    endcase
3408
                                `LHX,`LHUX,`LVHX,`LVHUX:
3409
                                   case(adr[2])
3410
                                   1'b0:    fnSelect = 8'h0F;
3411
                                   1'b1:    fnSelect = 8'hF0;
3412
                                   endcase
3413
                                `INC,`LVWX,
3414
                                `LWX,`LWRX,`LVX:
3415
                                   fnSelect = 8'hFF;
3416
                                default:fnSelect = 8'hFF;
3417
                endcase
3418
            else
3419
                                case({ins[31:28],ins[17:16]})
3420
               `SBX:
3421
                   case(adr[2:0])
3422
                   3'd0:    fnSelect = 8'h01;
3423
                   3'd1:    fnSelect = 8'h02;
3424
                   3'd2:    fnSelect = 8'h04;
3425
                   3'd3:    fnSelect = 8'h08;
3426
                   3'd4:    fnSelect = 8'h10;
3427
                   3'd5:    fnSelect = 8'h20;
3428
                   3'd6:    fnSelect = 8'h40;
3429
                   3'd7:    fnSelect = 8'h80;
3430
                   endcase
3431
                `SCX:
3432
                    case(adr[2:1])
3433
                    2'd0:   fnSelect = 8'h03;
3434
                    2'd1:   fnSelect = 8'h0C;
3435
                    2'd2:   fnSelect = 8'h30;
3436
                    2'd3:   fnSelect = 8'hC0;
3437
                    endcase
3438
                `SHX:
3439
                   case(adr[2])
3440
                   1'b0:    fnSelect = 8'h0F;
3441
                   1'b1:    fnSelect = 8'hF0;
3442
                   endcase
3443
               `INC,
3444
               `SWX,`SWCX,`SVX,`CASX,`PUSH:
3445
                   fnSelect = 8'hFF;
3446
               default: fnSelect = 8'h00;
3447
                   endcase
3448
                 end
3449
           else
3450
                fnSelect = 8'h00;
3451
  `LB,`LBU,`SB:
3452
                case(adr[2:0])
3453
                3'd0:   fnSelect = 8'h01;
3454
                3'd1:   fnSelect = 8'h02;
3455
                3'd2:   fnSelect = 8'h04;
3456
                3'd3:   fnSelect = 8'h08;
3457
                3'd4:   fnSelect = 8'h10;
3458
                3'd5:   fnSelect = 8'h20;
3459
                3'd6:   fnSelect = 8'h40;
3460
                3'd7:   fnSelect = 8'h80;
3461
                endcase
3462
  `Lx,`LxU,`LVx,`LVxU:
3463
        casez(ins[20:18])
3464
        3'b100: fnSelect = 8'hFF;
3465
        3'b?10: fnSelect = adr[2] ? 8'hF0 : 8'h0F;
3466
        3'b??1:
3467
      case(adr[2:1])
3468
      2'd0:   fnSelect = 8'h03;
3469
      2'd1:   fnSelect = 8'h0C;
3470
      2'd2:   fnSelect = 8'h30;
3471
      2'd3:   fnSelect = 8'hC0;
3472
      endcase
3473
    default: fnSelect = 8'h00;
3474
    endcase
3475
  `Sx:
3476
        casez(ins[15:13])
3477
        3'b100: fnSelect = 8'hFF;
3478
        3'b?10: fnSelect = adr[2] ? 8'hF0 : 8'h0F;
3479
        3'b??1:
3480
      case(adr[2:1])
3481
      2'd0:   fnSelect = 8'h03;
3482
      2'd1:   fnSelect = 8'h0C;
3483
      2'd2:   fnSelect = 8'h30;
3484
      2'd3:   fnSelect = 8'hC0;
3485
      endcase
3486
    default: fnSelect = 8'h00;
3487
    endcase
3488 61 robfinch
  `PUSHC,
3489 60 robfinch
        `INC,
3490
        `LWR,`SWC,`CAS:   fnSelect = 8'hFF;
3491
        `LV,`SV:   fnSelect = 8'hFF;
3492
        `AMO:
3493
                case(ins[23:21])
3494
                3'd0:   fnSelect = {8'h01 << adr[2:0]};
3495
                3'd1:   fnSelect = {8'h03 << {adr[2:1],1'b0}};
3496
                3'd2:   fnSelect = {8'h0F << {adr[2],2'b00}};
3497
                3'd3:   fnSelect = 8'hFF;
3498
                default:        fnSelect = 8'hFF;
3499
                endcase
3500
        default:        fnSelect = 8'h00;
3501
        endcase
3502
end
3503
endfunction
3504
/*
3505
function [63:0] fnDatc;
3506
input [47:0] ins;
3507
input [63:0] dat;
3508
case(ins[`INSTRUCTION_OP])
3509
`R2:
3510
        if (isn[`INSTRUCTION_L2]==2'b01)
3511
                case(ins[47:42])
3512
                `FINDB:         fnDatc = dat[7:0];
3513
                `FINDC:         fnDatc = dat[15:0];
3514
                `FINDH:         fnDatc = dat[31:0];
3515
                `FINDW:         fnDatc = dat[63:0];
3516
                default:        fnDatc = dat[63:0];
3517
                endcase
3518
        else
3519
                fnDatc = dat[63:0];
3520
default:        fnDatc = dat[63:0];
3521
endcase
3522
endfunction
3523
*/
3524
/*
3525
function [63:0] fnMemInc;
3526
input [47:0] ins;
3527
case(ins[`INSTRUCTION_OP])
3528
`R2:
3529
        if (isn[`INSTRUCTION_L2]==2'b01)
3530
                case(ins[47:42])
3531
                `FINDB:         fnMemInc = 32'd1;
3532
                `FINDC:         fnMemInc = 32'd2;
3533
                `FINDH:         fnMemInc = 32'd4;
3534
                `FINDW:         fnMemInc = 32'd8;
3535
                default:        fnMemInc = 32'd8;
3536
                endcase
3537
        else
3538
                fnMemInc = 32'd8;
3539
default:        fnMemInc = 32'd8;
3540
endcase
3541
endfunction
3542
*/
3543
function [63:0] fnDatiAlign;
3544
input [47:0] ins;
3545
input [`ABITS] adr;
3546
input [63:0] dat;
3547
case(ins[`INSTRUCTION_OP])
3548
`MEMNDX:
3549
        if (ins[`INSTRUCTION_L2]==2'b00)
3550
            case({ins[31:28],ins[22:21]})
3551
            `LBX,`LVBX:
3552
                case(adr[2:0])
3553
                3'd0:   fnDatiAlign = {{56{dat[7]}},dat[7:0]};
3554
                3'd1:   fnDatiAlign = {{56{dat[15]}},dat[15:8]};
3555
                3'd2:   fnDatiAlign = {{56{dat[23]}},dat[23:16]};
3556
                3'd3:   fnDatiAlign = {{56{dat[31]}},dat[31:24]};
3557
                3'd4:   fnDatiAlign = {{56{dat[39]}},dat[39:32]};
3558
                3'd5:   fnDatiAlign = {{56{dat[47]}},dat[47:40]};
3559
                3'd6:   fnDatiAlign = {{56{dat[55]}},dat[55:48]};
3560
                3'd7:   fnDatiAlign = {{56{dat[63]}},dat[63:56]};
3561
                endcase
3562
            `LBUX,`LVBUX:
3563
                case(adr[2:0])
3564
                3'd0:   fnDatiAlign = {{56{1'b0}},dat[7:0]};
3565
                3'd1:   fnDatiAlign = {{56{1'b0}},dat[15:8]};
3566
                3'd2:   fnDatiAlign = {{56{1'b0}},dat[23:16]};
3567
                3'd3:   fnDatiAlign = {{56{1'b0}},dat[31:24]};
3568
                3'd4:   fnDatiAlign = {{56{1'b0}},dat[39:32]};
3569
                3'd5:   fnDatiAlign = {{56{1'b0}},dat[47:40]};
3570
                3'd6:   fnDatiAlign = {{56{1'b0}},dat[55:48]};
3571
                3'd7:   fnDatiAlign = {{56{2'b0}},dat[63:56]};
3572
                endcase
3573
            `LCX,`LVCX:
3574
                case(adr[2:1])
3575
                2'd0:   fnDatiAlign = {{48{dat[15]}},dat[15:0]};
3576
                2'd1:   fnDatiAlign = {{48{dat[31]}},dat[31:16]};
3577
                2'd2:   fnDatiAlign = {{48{dat[47]}},dat[47:32]};
3578
                2'd3:   fnDatiAlign = {{48{dat[63]}},dat[63:48]};
3579
                endcase
3580
            `LCUX,`LVCUX:
3581
                case(adr[2:1])
3582
                2'd0:   fnDatiAlign = {{48{1'b0}},dat[15:0]};
3583
                2'd1:   fnDatiAlign = {{48{1'b0}},dat[31:16]};
3584
                2'd2:   fnDatiAlign = {{48{1'b0}},dat[47:32]};
3585
                2'd3:   fnDatiAlign = {{48{1'b0}},dat[63:48]};
3586
                endcase
3587
            `LHX,`LVHX:
3588
                case(adr[2])
3589
                1'b0:   fnDatiAlign = {{32{dat[31]}},dat[31:0]};
3590
                1'b1:   fnDatiAlign = {{32{dat[63]}},dat[63:32]};
3591
                endcase
3592
            `LHUX,`LVHUX:
3593
                case(adr[2])
3594
                1'b0:   fnDatiAlign = {{32{1'b0}},dat[31:0]};
3595
                1'b1:   fnDatiAlign = {{32{1'b0}},dat[63:32]};
3596
                endcase
3597
            `LWX,`LWRX,`LVX,`CAS,`LVWX:  fnDatiAlign = dat;
3598
            default:    fnDatiAlign = dat;
3599
            endcase
3600
        else
3601
                fnDatiAlign = dat;
3602
`LB:
3603
  case(adr[2:0])
3604
  3'd0:   fnDatiAlign = {{56{dat[7]}},dat[7:0]};
3605
  3'd1:   fnDatiAlign = {{56{dat[15]}},dat[15:8]};
3606
  3'd2:   fnDatiAlign = {{56{dat[23]}},dat[23:16]};
3607
  3'd3:   fnDatiAlign = {{56{dat[31]}},dat[31:24]};
3608
  3'd4:   fnDatiAlign = {{56{dat[39]}},dat[39:32]};
3609
  3'd5:   fnDatiAlign = {{56{dat[47]}},dat[47:40]};
3610
  3'd6:   fnDatiAlign = {{56{dat[55]}},dat[55:48]};
3611
  3'd7:   fnDatiAlign = {{56{dat[63]}},dat[63:56]};
3612
  endcase
3613
`LBU:
3614
  case(adr[2:0])
3615
  3'd0:   fnDatiAlign = {{56{1'b0}},dat[7:0]};
3616
  3'd1:   fnDatiAlign = {{56{1'b0}},dat[15:8]};
3617
  3'd2:   fnDatiAlign = {{56{1'b0}},dat[23:16]};
3618
  3'd3:   fnDatiAlign = {{56{1'b0}},dat[31:24]};
3619
  3'd4:   fnDatiAlign = {{56{1'b0}},dat[39:32]};
3620
  3'd5:   fnDatiAlign = {{56{1'b0}},dat[47:40]};
3621
  3'd6:   fnDatiAlign = {{56{1'b0}},dat[55:48]};
3622
  3'd7:   fnDatiAlign = {{56{2'b0}},dat[63:56]};
3623
  endcase
3624
`Lx,`LVx:
3625
        casez(ins[20:18])
3626
        3'b100: fnDatiAlign = dat;
3627
        3'b?10:
3628
          case(adr[2])
3629
          1'b0:   fnDatiAlign = {{32{dat[31]}},dat[31:0]};
3630
          1'b1:   fnDatiAlign = {{32{dat[63]}},dat[63:32]};
3631
          endcase
3632
        3'b??1:
3633
          case(adr[2:1])
3634
          2'd0:   fnDatiAlign = {{48{dat[15]}},dat[15:0]};
3635
          2'd1:   fnDatiAlign = {{48{dat[31]}},dat[31:16]};
3636
          2'd2:   fnDatiAlign = {{48{dat[47]}},dat[47:32]};
3637
          2'd3:   fnDatiAlign = {{48{dat[63]}},dat[63:48]};
3638
          endcase
3639
        default:        fnDatiAlign = dat;
3640
        endcase
3641
`LxU,`LVxU:
3642
        casez(ins[20:18])
3643
        3'b100: fnDatiAlign = dat;
3644
        3'b?10:
3645
          case(adr[2])
3646
          1'b0:   fnDatiAlign = {{32{1'b0}},dat[31:0]};
3647
          1'b1:   fnDatiAlign = {{32{1'b0}},dat[63:32]};
3648
          endcase
3649
        3'b??1:
3650
          case(adr[2:1])
3651
          2'd0:   fnDatiAlign = {{48{1'b0}},dat[15:0]};
3652
          2'd1:   fnDatiAlign = {{48{1'b0}},dat[31:16]};
3653
          2'd2:   fnDatiAlign = {{48{1'b0}},dat[47:32]};
3654
          2'd3:   fnDatiAlign = {{48{1'b0}},dat[63:48]};
3655
          endcase
3656
        default:        fnDatiAlign = dat;
3657
        endcase
3658
`LWR,`LV,`CAS,`AMO:   fnDatiAlign = dat;
3659
default:    fnDatiAlign = dat;
3660
endcase
3661
endfunction
3662
 
3663
function [63:0] fnDato;
3664
input [47:0] isn;
3665
input [63:0] dat;
3666
case(isn[`INSTRUCTION_OP])
3667
`MEMNDX:
3668
        if (isn[`INSTRUCTION_L2]==2'b00)
3669
                case({isn[31:28],isn[17:16]})
3670
                `SBX:   fnDato = {8{dat[7:0]}};
3671
                `SCX:   fnDato = {4{dat[15:0]}};
3672
                `SHX:   fnDato = {2{dat[31:0]}};
3673
                default:    fnDato = dat;
3674
                endcase
3675
        else
3676
                fnDato = dat;
3677
`SB:   fnDato = {8{dat[7:0]}};
3678
`Sx:
3679
        casez(isn[15:13])
3680
        3'b100: fnDato = dat;
3681
        3'b?10: fnDato = {2{dat[31:0]}};
3682
        3'b??1: fnDato = {4{dat[15:0]}};
3683
        default:        fnDato = dat;
3684
        endcase
3685
`AMO:
3686
        case(isn[23:21])
3687
        3'd0:   fnDato = {8{dat[7:0]}};
3688
        3'd1:   fnDato = {4{dat[15:0]}};
3689
        3'd2:   fnDato = {2{dat[31:0]}};
3690
        3'd3:   fnDato = dat;
3691
        default:        fnDato = dat;
3692
        endcase
3693
default:    fnDato = dat;
3694
endcase
3695
endfunction
3696
 
3697
function IsTLB;
3698
input [47:0] isn;
3699
case(isn[`INSTRUCTION_OP])
3700
`R2:
3701
  case(isn[`INSTRUCTION_S2])
3702
  `TLB:   IsTLB = TRUE;
3703
  default:    IsTLB = FALSE;
3704
  endcase
3705
default:    IsTLB = FALSE;
3706
endcase
3707
endfunction
3708
 
3709
// Indicate if the ALU instruction is valid immediately (single cycle operation)
3710
function IsSingleCycle;
3711
input [47:0] isn;
3712
IsSingleCycle = !(IsMul(isn)|IsDivmod(isn)|IsTLB(isn)|IsShift48(isn));
3713
endfunction
3714
 
3715
 
3716
generate begin : gDecocderInst
3717
for (g = 0; g < QENTRIES; g = g + 1) begin
3718
`ifdef SUPPORT_SMT
3719
decoder8 iq0(.num({iqentry_tgt[g][8:7],iqentry_tgt[g][5:0]}), .out(iq_out[g]));
3720
`else
3721
decoder7 iq0(.num({iqentry_tgt[g][7],iqentry_tgt[g][5:0]}), .out(iq_out[g]));
3722
`endif
3723
end
3724
end
3725
endgenerate
3726
 
3727
initial begin: Init
3728
        //
3729
        //
3730
        // set up panic messages
3731
        message[ `PANIC_NONE ]                  = "NONE            ";
3732
        message[ `PANIC_FETCHBUFBEQ ]           = "FETCHBUFBEQ     ";
3733
        message[ `PANIC_INVALIDISLOT ]          = "INVALIDISLOT    ";
3734
        message[ `PANIC_IDENTICALDRAMS ]        = "IDENTICALDRAMS  ";
3735
        message[ `PANIC_OVERRUN ]               = "OVERRUN         ";
3736
        message[ `PANIC_HALTINSTRUCTION ]       = "HALTINSTRUCTION ";
3737
        message[ `PANIC_INVALIDMEMOP ]          = "INVALIDMEMOP    ";
3738
        message[ `PANIC_INVALIDFBSTATE ]        = "INVALIDFBSTATE  ";
3739
        message[ `PANIC_INVALIDIQSTATE ]        = "INVALIDIQSTATE  ";
3740
        message[ `PANIC_BRANCHBACK ]            = "BRANCHBACK      ";
3741
        message[ `PANIC_MEMORYRACE ]            = "MEMORYRACE      ";
3742
        message[ `PANIC_ALU0ONLY ] = "ALU0 Only       ";
3743
 
3744
        for (n = 0; n < 64; n = n + 1)
3745
                codebuf[n] <= 48'h0;
3746
 
3747
end
3748
 
3749
// ---------------------------------------------------------------------------
3750
// FETCH
3751
// ---------------------------------------------------------------------------
3752
//
3753 61 robfinch
assign fetchbuf0_mem = IsMem(fetchbuf0_instr) & ~IsRet(fetchbuf0_instr);// & IsLoad(fetchbuf0_instr);
3754 60 robfinch
assign fetchbuf0_rfw   = IsRFW(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd);
3755
 
3756
generate begin: gFetchbufDec
3757
if (`WAYS > 1) begin
3758 61 robfinch
assign fetchbuf1_mem = IsMem(fetchbuf1_instr) & ~IsRet(fetchbuf1_instr);// & IsLoad(fetchbuf1_instr);
3759 60 robfinch
assign fetchbuf1_rfw   = IsRFW(fetchbuf1_instr,vqe1,vl,fetchbuf1_thrd);
3760
end
3761
if (`WAYS > 2) begin
3762 61 robfinch
assign fetchbuf2_mem = IsMem(fetchbuf2_instr) & ~IsRet(fetchbuf2_instr);// & IsLoad(fetchbuf2_instr);
3763 60 robfinch
assign fetchbuf2_rfw   = IsRFW(fetchbuf2_instr,vqe2,vl,fetchbuf2_thrd);
3764
end
3765
end
3766
endgenerate
3767
 
3768
generate begin : gFetchbufInst
3769
if (`WAYS > 2) begin : gb1
3770
FT64_fetchbuf_x3 #(AMSB,RSTPC) ufb1
3771
(
3772
  .rst(rst),
3773
  .clk4x(clk4x),
3774
  .clk(clk),
3775
  .fcu_clk(fcu_clk),
3776
  .cs_i(vadr[31:16]==16'hFFFF),
3777
  .cyc_i(cyc),
3778
  .stb_i(stb_o),
3779
  .ack_o(dc_ack),
3780
  .we_i(we),
3781
  .adr_i(vadr[15:0]),
3782
  .dat_i(dat_o[47:0]),
3783
  .cmpgrp(cr0[10:8]),
3784
  .freezePC(freezePC),
3785
  .regLR(regLR),
3786
  .thread_en(thread_en),
3787
  .insn0(insn0),
3788
  .insn1(insn1),
3789
  .insn1(insn2),
3790
  .phit(phit),
3791
  .threadx(threadx),
3792
  .branchmiss(branchmiss),
3793
  .misspc(misspc),
3794
  .branchmiss_thrd(branchmiss_thrd),
3795
  .predict_takenA(predict_takenA),
3796
  .predict_takenB(predict_takenB),
3797
  .predict_takenC(predict_takenC),
3798
  .predict_takenD(predict_takenD),
3799
  .predict_takenE(predict_takenE),
3800
  .predict_takenF(predict_takenF),
3801
  .predict_taken0(predict_taken0),
3802
  .predict_taken1(predict_taken1),
3803
  .predict_taken2(predict_taken2),
3804
  .queued1(queued1),
3805
  .queued2(queued2),
3806
  .queued2(queued3),
3807
  .queuedNop(queuedNop),
3808
  .pc0(pc0a),
3809
  .pc1(pc1a),
3810
  .fetchbuf(fetchbuf),
3811
  .fetchbufA_v(fetchbufA_v),
3812
  .fetchbufB_v(fetchbufB_v),
3813
  .fetchbufC_v(fetchbufC_v),
3814
  .fetchbufD_v(fetchbufD_v),
3815
  .fetchbufD_v(fetchbufE_v),
3816
  .fetchbufD_v(fetchbufF_v),
3817
  .fetchbufA_pc(fetchbufA_pc),
3818
  .fetchbufB_pc(fetchbufB_pc),
3819
  .fetchbufC_pc(fetchbufC_pc),
3820
  .fetchbufD_pc(fetchbufD_pc),
3821
  .fetchbufD_pc(fetchbufE_pc),
3822
  .fetchbufD_pc(fetchbufF_pc),
3823
  .fetchbufA_instr(fetchbufA_instr),
3824
  .fetchbufB_instr(fetchbufB_instr),
3825
  .fetchbufC_instr(fetchbufC_instr),
3826
  .fetchbufD_instr(fetchbufD_instr),
3827
  .fetchbufE_instr(fetchbufE_instr),
3828
  .fetchbufF_instr(fetchbufF_instr),
3829
  .fetchbuf0_instr(fetchbuf0_instr),
3830
  .fetchbuf1_instr(fetchbuf1_instr),
3831
  .fetchbuf0_thrd(fetchbuf0_thrd),
3832
  .fetchbuf1_thrd(fetchbuf1_thrd),
3833
  .fetchbuf2_thrd(fetchbuf2_thrd),
3834
  .fetchbuf0_pc(fetchbuf0_pc),
3835
  .fetchbuf1_pc(fetchbuf1_pc),
3836
  .fetchbuf2_pc(fetchbuf2_pc),
3837
  .fetchbuf0_v(fetchbuf0_v),
3838
  .fetchbuf1_v(fetchbuf1_v),
3839
  .fetchbuf2_v(fetchbuf2_v),
3840
  .fetchbuf0_insln(fetchbuf0_insln),
3841
  .fetchbuf1_insln(fetchbuf1_insln),
3842
  .fetchbuf2_insln(fetchbuf2_insln),
3843 61 robfinch
  .codebuf0(codebuf[insn0[13:8]]),
3844
  .codebuf1(codebuf[insn1[13:8]]),
3845
  .codebuf2(codebuf[insn2[13:8]]),
3846 60 robfinch
  .btgtA(btgtA),
3847
  .btgtB(btgtB),
3848
  .btgtC(btgtC),
3849
  .btgtD(btgtD),
3850
  .btgtE(btgtE),
3851
  .btgtF(btgtF),
3852
  .nop_fetchbuf(nop_fetchbuf),
3853
  .take_branch0(take_branch0),
3854
  .take_branch1(take_branch1),
3855
  .take_branch2(take_branch2),
3856
  .stompedRets(stompedOnRets),
3857
  .pred_on(pred_on),
3858
  .panic(fb_panic)
3859
);
3860
end
3861
else if (`WAYS > 1) begin : gb1
3862
FT64_fetchbuf #(AMSB,RSTPC) ufb1
3863
(
3864
  .rst(rst),
3865
  .clk4x(clk4x),
3866
  .clk(clk),
3867
  .fcu_clk(fcu_clk),
3868
  .cs_i(vadr[31:16]==16'hFFFF),
3869
  .cyc_i(cyc),
3870
  .stb_i(stb_o),
3871
  .ack_o(dc_ack),
3872
  .we_i(we),
3873
  .adr_i(vadr[15:0]),
3874
  .dat_i(dat_o[47:0]),
3875
  .cmpgrp(cr0[10:8]),
3876
  .freezePC(freezePC),
3877
  .regLR(regLR),
3878
  .thread_en(thread_en),
3879
  .insn0(insn0),
3880
  .insn1(insn1),
3881
  .phit(phit),
3882
  .threadx(threadx),
3883
  .branchmiss(branchmiss),
3884
  .misspc(misspc),
3885
  .branchmiss_thrd(branchmiss_thrd),
3886
  .predict_takenA(predict_takenA),
3887
  .predict_takenB(predict_takenB),
3888
  .predict_takenC(predict_takenC),
3889
  .predict_takenD(predict_takenD),
3890
  .predict_taken0(predict_taken0),
3891
  .predict_taken1(predict_taken1),
3892
  .queued1(queued1),
3893
  .queued2(queued2),
3894
  .queuedNop(queuedNop),
3895
  .pc0(pc0a),
3896
  .pc1(pc1a),
3897
  .fetchbuf(fetchbuf),
3898
  .fetchbufA_v(fetchbufA_v),
3899
  .fetchbufB_v(fetchbufB_v),
3900
  .fetchbufC_v(fetchbufC_v),
3901
  .fetchbufD_v(fetchbufD_v),
3902
  .fetchbufA_pc(fetchbufA_pc),
3903
  .fetchbufB_pc(fetchbufB_pc),
3904
  .fetchbufC_pc(fetchbufC_pc),
3905
  .fetchbufD_pc(fetchbufD_pc),
3906
  .fetchbufA_instr(fetchbufA_instr),
3907
  .fetchbufB_instr(fetchbufB_instr),
3908
  .fetchbufC_instr(fetchbufC_instr),
3909
  .fetchbufD_instr(fetchbufD_instr),
3910
  .fetchbuf0_instr(fetchbuf0_instr),
3911
  .fetchbuf1_instr(fetchbuf1_instr),
3912
  .fetchbuf0_thrd(fetchbuf0_thrd),
3913
  .fetchbuf1_thrd(fetchbuf1_thrd),
3914
  .fetchbuf0_pc(fetchbuf0_pc),
3915
  .fetchbuf1_pc(fetchbuf1_pc),
3916
  .fetchbuf0_v(fetchbuf0_v),
3917
  .fetchbuf1_v(fetchbuf1_v),
3918
  .fetchbuf0_insln(fetchbuf0_insln),
3919
  .fetchbuf1_insln(fetchbuf1_insln),
3920 61 robfinch
  .codebuf0(codebuf[insn0[13:8]]),
3921
  .codebuf1(codebuf[insn1[13:8]]),
3922 60 robfinch
  .btgtA(btgtA),
3923
  .btgtB(btgtB),
3924
  .btgtC(btgtC),
3925
  .btgtD(btgtD),
3926
  .nop_fetchbuf(nop_fetchbuf),
3927
  .take_branch0(take_branch0),
3928
  .take_branch1(take_branch1),
3929
  .stompedRets(stompedOnRets),
3930
  .pred_on(pred_on),
3931
  .panic(fb_panic)
3932
);
3933
end
3934
else begin : gb1
3935
FT64_fetchbuf_x1 #(AMSB,RSTPC) ufb1
3936
(
3937
  .rst(rst),
3938
  .clk4x(clk4x),
3939
  .clk(clk),
3940
  .fcu_clk(fcu_clk),
3941
  .cs_i(vadr[31:16]==16'hFFFF),
3942
  .cyc_i(cyc),
3943
  .stb_i(stb_o),
3944
  .ack_o(dc_ack),
3945
  .we_i(we),
3946
  .adr_i(vadr[15:0]),
3947
  .dat_i(dat_o[47:0]),
3948
  .cmpgrp(cr0[10:8]),
3949
  .freezePC(freezePC),
3950
  .regLR(regLR),
3951
  .thread_en(thread_en),
3952
  .insn0(insn0),
3953
  .phit(phit),
3954
  .threadx(threadx),
3955
  .branchmiss(branchmiss),
3956
  .misspc(misspc),
3957
  .branchmiss_thrd(branchmiss_thrd),
3958
  .predict_takenA(predict_takenA),
3959
  .predict_takenB(predict_takenB),
3960
  .predict_taken0(predict_taken0),
3961
  .queued1(queued1),
3962
  .queuedNop(queuedNop),
3963
  .pc0(pc0a),
3964
  .fetchbuf(fetchbuf),
3965
  .fetchbufA_v(fetchbufA_v),
3966
  .fetchbufB_v(fetchbufB_v),
3967
  .fetchbufA_pc(fetchbufA_pc),
3968
  .fetchbufB_pc(fetchbufB_pc),
3969
  .fetchbufA_instr(fetchbufA_instr),
3970
  .fetchbufB_instr(fetchbufB_instr),
3971
  .fetchbuf0_instr(fetchbuf0_instr),
3972
  .fetchbuf0_thrd(fetchbuf0_thrd),
3973
  .fetchbuf0_pc(fetchbuf0_pc),
3974
  .fetchbuf0_v(fetchbuf0_v),
3975
  .fetchbuf0_insln(fetchbuf0_insln),
3976
  .fetchbuf0_pbyte(fetchbuf0_pbyte),
3977 61 robfinch
  .codebuf0(codebuf[insn0[13:8]]),
3978 60 robfinch
  .btgtA(btgtA),
3979
  .btgtB(btgtB),
3980
  .nop_fetchbuf(nop_fetchbuf),
3981
  .take_branch0(take_branch0),
3982
  .stompedRets(stompedOnRets),
3983
  .pred_on(pred_on),
3984
  .panic(fb_panic)
3985
);
3986
assign fetchbuf1_v = `INV;
3987
end
3988
end
3989
endgenerate
3990
 
3991 61 robfinch
// Stores might exception so we don't want the heads to advance if a subsequent
3992
// instruction is store even though there's no target register.
3993 60 robfinch
wire cmt_head1 = (!iqentry_rfw[heads[1]] && !iqentry_oddball[heads[1]] && ~|iqentry_exc[heads[1]]);
3994
wire cmt_head2 = (!iqentry_rfw[heads[2]] && !iqentry_oddball[heads[2]] && ~|iqentry_exc[heads[2]]);
3995
 
3996
// Determine the head increment amount, this must match code later on.
3997
reg [2:0] hi_amt;
3998
always @*
3999
begin
4000
        hi_amt <= 4'd0;
4001
  casez ({ iqentry_v[heads[0]],
4002
                iqentry_state[heads[0]]==IQS_CMT,
4003
                iqentry_v[heads[1]],
4004
                iqentry_state[heads[1]]==IQS_CMT,
4005
                iqentry_v[heads[2]],
4006
                iqentry_state[heads[2]]==IQS_CMT})
4007
 
4008
        // retire 3
4009
        6'b0?_0?_0?:
4010
                if (heads[0] != tail0 && heads[1] != tail0 && heads[2] != tail0)
4011
                        hi_amt <= 3'd3;
4012
                else if (heads[0] != tail0 && heads[1] != tail0)
4013
                        hi_amt <= 3'd2;
4014
                else if (heads[0] != tail0)
4015
                        hi_amt <= 3'd1;
4016
        6'b0?_0?_10:
4017
                if (heads[0] != tail0 && heads[1] != tail0)
4018
                        hi_amt <= 3'd2;
4019
                else if (heads[0] != tail0)
4020
                        hi_amt <= 3'd1;
4021
                else
4022
                        hi_amt <= 3'd0;
4023
        6'b0?_0?_11:
4024
                if (`NUM_CMT > 2 || cmt_head2)
4025
                        hi_amt <= 3'd3;
4026
                else
4027
                        hi_amt <= 3'd2;
4028
 
4029
        // retire 1 (wait for regfile for heads[1])
4030
        6'b0?_10_??:
4031
                hi_amt <= 3'd1;
4032
 
4033
        // retire 2
4034
        6'b0?_11_0?,
4035
        6'b0?_11_10:
4036
    if (`NUM_CMT > 1 || cmt_head1)
4037
                        hi_amt <= 3'd2;
4038
    else
4039
                        hi_amt <= 3'd1;
4040
  6'b0?_11_11:
4041
    if (`NUM_CMT > 2 || (`NUM_CMT > 1 && cmt_head2))
4042
                        hi_amt <= 3'd3;
4043
        else if (`NUM_CMT > 1 || cmt_head1)
4044
                        hi_amt <= 3'd2;
4045
        else
4046
                        hi_amt <= 3'd1;
4047
  6'b10_??_??:  ;
4048
  6'b11_0?_0?:
4049
        if (heads[1] != tail0 && heads[2] != tail0)
4050
                        hi_amt <= 3'd3;
4051
        else if (heads[1] != tail0)
4052
                        hi_amt <= 3'd2;
4053
        else
4054
                        hi_amt <= 3'd1;
4055
  6'b11_0?_10:
4056
        if (heads[1] != tail0)
4057
                        hi_amt <= 3'd2;
4058
        else
4059
                        hi_amt <= 3'd1;
4060
  6'b11_0?_11:
4061
        if (heads[1] != tail0) begin
4062
                if (`NUM_CMT > 2 || cmt_head2)
4063
                                hi_amt <= 3'd3;
4064
                else
4065
                                hi_amt <= 3'd2;
4066
        end
4067
        else
4068
                        hi_amt <= 3'd1;
4069
  6'b11_10_??:
4070
                        hi_amt <= 3'd1;
4071
  6'b11_11_0?:
4072
        if (`NUM_CMT > 1 && heads[2] != tail0)
4073
                        hi_amt <= 3'd3;
4074
        else if (cmt_head1 && heads[2] != tail0)
4075
                        hi_amt <= 3'd3;
4076
                else if (`NUM_CMT > 1 || cmt_head1)
4077
                        hi_amt <= 3'd2;
4078
        else
4079
                        hi_amt <= 3'd1;
4080
  6'b11_11_10:
4081
                if (`NUM_CMT > 1 || cmt_head1)
4082
                        hi_amt <= 3'd2;
4083
        else
4084
                        hi_amt <= 3'd1;
4085
        6'b11_11_11:
4086
                if (`NUM_CMT > 2 || (`NUM_CMT > 1 && cmt_head2))
4087
                        hi_amt <= 3'd3;
4088
                else if (`NUM_CMT > 1 || cmt_head1)
4089
                        hi_amt <= 3'd2;
4090
                else
4091
                        hi_amt <= 3'd1;
4092
        default:
4093
                begin
4094
                        hi_amt <= 3'd0;
4095
                        $display("hi_amt: Uncoded case %h",{ iqentry_v[heads[0]],
4096
                                iqentry_state[heads[0]],
4097
                                iqentry_v[heads[1]],
4098
                                iqentry_state[heads[1]],
4099
                                iqentry_v[heads[2]],
4100
                                iqentry_state[heads[2]]});
4101
                end
4102
  endcase
4103
end
4104
 
4105
// Amount subtracted from sequence numbers
4106
reg [`SNBITS] tosub;
4107
always @*
4108
case(hi_amt)
4109
3'd3: tosub <= (iqentry_v[heads[2]] ? iqentry_sn[heads[2]]
4110
                                                         : iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
4111
                                                         : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
4112
                                                         : 4'b0);
4113
3'd2: tosub <= (iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
4114
                                                         : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
4115
                                                         : 4'b0);
4116
3'd1: tosub <= (iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
4117
                                                         : 4'b0);
4118
default:        tosub <= 4'd0;
4119
endcase
4120
 
4121
//initial begin: stop_at
4122
//#1000000; panic <= `PANIC_OVERRUN;
4123
//end
4124
 
4125
//
4126
// BRANCH-MISS LOGIC: livetarget
4127
//
4128
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
4129
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
4130
// 
4131
 
4132
always @*
4133
for (j = 1; j < PREGS; j = j + 1) begin
4134
        livetarget[j] = 1'b0;
4135
        for (n = 0; n < QENTRIES; n = n + 1)
4136
                livetarget[j] = livetarget[j] | iqentry_livetarget[n][j];
4137
end
4138
 
4139
always @*
4140
        for (n = 0; n < QENTRIES; n = n + 1)
4141
                iqentry_livetarget[n] = {PREGS {iqentry_v[n]}} & {PREGS {~iqentry_stomp[n] && iqentry_thrd[n]==branchmiss_thrd}} & iq_out[n];
4142
 
4143
//
4144
// BRANCH-MISS LOGIC: latestID
4145
//
4146
// latestID is the instruction queue ID of the newest instruction (latest) that targets
4147
// a particular register.  looks a lot like scheduling logic, but in reverse.
4148
// 
4149
always @*
4150
        for (n = 0; n < QENTRIES; n = n + 1) begin
4151
                iqentry_cumulative[n] = 1'b0;
4152
                for (j = n; j < n + QENTRIES; j = j + 1) begin
4153
                        if (missid==(j % QENTRIES))
4154
                                for (k = n; k <= j; k = k + 1)
4155
                                        iqentry_cumulative[n] = iqentry_cumulative[n] | iqentry_livetarget[k % QENTRIES];
4156
                end
4157
        end
4158
 
4159
always @*
4160
        for (n = 0; n < QENTRIES; n = n + 1)
4161
    iqentry_latestID[n] = (missid == n || ((iqentry_livetarget[n] & iqentry_cumulative[(n+1)%QENTRIES]) == {PREGS{1'b0}}))
4162
                                    ? iqentry_livetarget[n]
4163
                                    : {PREGS{1'b0}};
4164
 
4165
always @*
4166
        for (n = 0; n < QENTRIES; n = n + 1)
4167
          iqentry_source[n] = | iqentry_latestID[n];
4168
 
4169
reg vqueued2;
4170
assign Ra0 = fnRa(fetchbuf0_instr,vqe0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
4171
assign Rb0 = fnRb(fetchbuf0_instr,1'b0,vqe0,rfoa0[5:0],rfoa1[5:0],fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
4172
assign Rc0 = fnRc(fetchbuf0_instr,vqe0,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
4173
assign Rt0 = fnRt(fetchbuf0_instr,vqet0,vl,fetchbuf0_thrd) | {fetchbuf0_thrd,7'b0};
4174
assign Ra1 = fnRa(fetchbuf1_instr,vqueued2 ? vqe0 + 1 : vqe1,vl,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
4175
assign Rb1 = fnRb(fetchbuf1_instr,1'b1,vqueued2 ? vqe0 + 1 : vqe1,rfoa0[5:0],rfoa1[5:0],fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
4176
assign Rc1 = fnRc(fetchbuf1_instr,vqueued2 ? vqe0 + 1 : vqe1,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
4177
assign Rt1 = fnRt(fetchbuf1_instr,vqueued2 ? vqet0 + 1 : vqet1,vl,fetchbuf1_thrd) | {fetchbuf1_thrd,7'b0};
4178
 
4179
//
4180
// additional logic for ISSUE
4181
//
4182
// for the moment, we look at ALU-input buffers to allow back-to-back issue of 
4183
// dependent instructions ... we do not, however, look ahead for DRAM requests 
4184
// that will become valid in the next cycle.  instead, these have to propagate
4185
// their results into the IQ entry directly, at which point it becomes issue-able
4186
//
4187
 
4188
// note that, for all intents & purposes, iqentry_done == iqentry_agen ... no need to duplicate
4189
 
4190
wire [QENTRIES-1:0] args_valid;
4191
wire [QENTRIES-1:0] could_issue;
4192
wire [QENTRIES-1:0] could_issueid;
4193
 
4194
// Note that bypassing is provided only from the first fpu.
4195
generate begin : issue_logic
4196
for (g = 0; g < QENTRIES; g = g + 1)
4197
begin
4198
assign args_valid[g] =
4199
                  (iqentry_a1_v[g]
4200
`ifdef FU_BYPASS
4201
        || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready && (~alu0_mem | alu0_push))
4202
        || ((iqentry_a1_s[g] == alu1_sourceid && alu1_dataready && (~alu1_mem | alu1_push)) && (`NUM_ALU > 1))
4203
        || ((iqentry_a1_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
4204
`endif
4205
        )
4206
    && (iqentry_a2_v[g] || iqentry_mem[g]       // a2 does not need to be valid immediately for a mem op (agen), it is checked by iqentry_memready logic
4207
`ifdef FU_BYPASS
4208
        || (iqentry_a2_s[g] == alu0_sourceid && alu0_dataready && (~alu0_mem | alu0_push))
4209
        || ((iqentry_a2_s[g] == alu1_sourceid && alu1_dataready && (~alu1_mem | alu1_push)) && (`NUM_ALU > 1))
4210
        || ((iqentry_a2_s[g] == fpu1_sourceid && fpu1_dataready) && (`NUM_FPU > 0))
4211
`endif
4212
        )
4213
    && (iqentry_a3_v[g]
4214
        || (iqentry_mem[g] & ~iqentry_agen[g] & ~iqentry_memndx[g])    // a3 needs to be valid for indexed instruction
4215
//        || (iqentry_mem[g] & ~iqentry_agen[g])
4216
`ifdef FU_BYPASS
4217
        || (iqentry_a3_s[g] == alu0_sourceid && alu0_dataready && (~alu0_mem | alu0_push))
4218
        || ((iqentry_a3_s[g] == alu1_sourceid && alu1_dataready && (~alu1_mem | alu1_push)) && (`NUM_ALU > 1))
4219
`endif
4220
        )
4221
    ;
4222
 
4223
assign could_issue[g] = iqentry_v[g] && iqentry_state[g]==IQS_QUEUED
4224
                                                                                                && args_valid[g]
4225
                                                                                                && iqentry_iv[g];
4226
                        //&& (iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
4227
 
4228
assign could_issueid[g] = (iqentry_v[g])// || (g==tail0 && canq1))// || (g==tail1 && canq2))
4229
                                                                                                                && !iqentry_iv[g];
4230
//                && (iqentry_a1_v[g] 
4231
//        || (iqentry_a1_s[g] == alu0_sourceid && alu0_dataready)
4232
//        || (iqentry_a1_s[g] == alu1_sourceid && alu1_dataready));
4233
 
4234
end
4235
end
4236
endgenerate
4237
 
4238
// The (old) simulator didn't handle the asynchronous race loop properly in the 
4239
// original code. It would issue two instructions to the same islot. So the
4240
// issue logic has been re-written to eliminate the asynchronous loop.
4241
// Can't issue to the ALU if it's busy doing a long running operation like a 
4242
// divide.
4243
// ToDo: fix the memory synchronization, see fp_issue below
4244
`ifndef INLINE_DECODE
4245
always @*
4246
begin
4247
        iqentry_id1issue = {QENTRIES{1'b0}};
4248
        if (id1_available) begin
4249
                for (n = 0; n < QENTRIES; n = n + 1)
4250
                        if (could_issueid[heads[n]] && iqentry_id1issue=={QENTRIES{1'b0}})
4251
                          iqentry_id1issue[heads[n]] = `TRUE;
4252
        end
4253
end
4254
generate begin : gIDUIssue
4255
        if (`NUM_IDU > 1) begin
4256
                always @*
4257
                begin
4258
                        iqentry_id2issue = {QENTRIES{1'b0}};
4259
                        if (id2_available) begin
4260
                                for (n = 0; n < QENTRIES; n = n + 1)
4261
                                        if (could_issueid[heads[n]] && !iqentry_id1issue[heads[n]] && iqentry_id2issue=={QENTRIES{1'b0}})
4262
                                          iqentry_id2issue[heads[n]] = `TRUE;
4263
                        end
4264
                end
4265
        end
4266
        if (`NUM_IDU > 2) begin
4267
                always @*
4268
                begin
4269
                        iqentry_id3issue = {QENTRIES{1'b0}};
4270
                        if (id3_available) begin
4271
                                for (n = 0; n < QENTRIES; n = n + 1)
4272
                                        if (could_issueid[heads[n]]
4273
                                        && !iqentry_id1issue[heads[n]]
4274
                                        && !iqentry_id2issue[heads[n]]
4275
                                        && iqentry_id3issue=={QENTRIES{1'b0}})
4276
                                          iqentry_id3issue[heads[n]] = `TRUE;
4277
                        end
4278
                end
4279
        end
4280
end
4281
endgenerate
4282
`endif  // not INLINE_DECODE
4283
 
4284
// Detect if there are any valid queue entries prior to the given queue entry.
4285
reg [QENTRIES-1:0] prior_valid;
4286
//generate begin : gPriorValid
4287
always @*
4288
for (j = 0; j < QENTRIES; j = j + 1)
4289
begin
4290
        prior_valid[heads[j]] = 1'b0;
4291
        if (j > 0)
4292
                for (n = j-1; n >= 0; n = n - 1)
4293
                        prior_valid[heads[j]] = prior_valid[heads[j]]|iqentry_v[heads[n]];
4294
end
4295
//end
4296
//endgenerate
4297
 
4298
// Detect if there are any valid sync instructions prior to the given queue 
4299
// entry.
4300
reg [QENTRIES-1:0] prior_sync;
4301
//generate begin : gPriorSync
4302
always @*
4303
for (j = 0; j < QENTRIES; j = j + 1)
4304
begin
4305
        prior_sync[heads[j]] = 1'b0;
4306
        if (j > 0)
4307
                for (n = j-1; n >= 0; n = n - 1)
4308
                        prior_sync[heads[j]] = prior_sync[heads[j]]|(iqentry_v[heads[n]] & iqentry_sync[heads[n]]);
4309
end
4310
//end
4311
//endgenerate
4312
 
4313
// Detect if there are any valid fsync instructions prior to the given queue 
4314
// entry.
4315
reg [QENTRIES-1:0] prior_fsync;
4316
//generate begin : gPriorFsync
4317
always @*
4318
for (j = 0; j < QENTRIES; j = j + 1)
4319
begin
4320
        prior_fsync[heads[j]] = 1'b0;
4321
        if (j > 0)
4322
                for (n = j-1; n >= 0; n = n - 1)
4323
                        prior_fsync[heads[j]] = prior_fsync[heads[j]]|(iqentry_v[heads[n]] & iqentry_fsync[heads[n]]);
4324
end
4325
//end
4326
//endgenerate
4327
 
4328
// Start search for instructions to process at head of queue (oldest instruction).
4329
always @*
4330
begin
4331
        iqentry_alu0_issue = {QENTRIES{1'b0}};
4332
        iqentry_alu1_issue = {QENTRIES{1'b0}};
4333
 
4334
        if (alu0_available & alu0_idle) begin
4335
                for (n = 0; n < QENTRIES; n = n + 1) begin
4336
                        if (could_issue[heads[n]] && iqentry_alu[heads[n]]
4337
                        && iqentry_alu0_issue == {QENTRIES{1'b0}}
4338
                        // If there are no valid queue entries prior it doesn't matter if there is
4339
                        // a sync.
4340
                        && (!prior_sync[heads[n]] || !prior_valid[heads[n]])
4341
                        )
4342
                          iqentry_alu0_issue[heads[n]] = `TRUE;
4343
                end
4344
        end
4345
 
4346
        if (alu1_available && alu1_idle && `NUM_ALU > 1) begin
4347
//              if ((could_issue & ~iqentry_alu0_issue & ~iqentry_alu0) != {QENTRIES{1'b0}}) begin
4348
                        for (n = 0; n < QENTRIES; n = n + 1) begin
4349
                                if (could_issue[heads[n]] && iqentry_alu[heads[n]]
4350
                                        && !iqentry_alu0[heads[n]]      // alu0 only
4351
                                        && !iqentry_alu0_issue[heads[n]]
4352
                                        && iqentry_alu1_issue == {QENTRIES{1'b0}}
4353
                                        && (!prior_sync[heads[n]] || !prior_valid[heads[n]])
4354
                                )
4355
                                  iqentry_alu1_issue[heads[n]] = `TRUE;
4356
                        end
4357
//              end
4358
        end
4359
end
4360
 
4361
 
4362
// Start search for instructions to process at head of queue (oldest instruction).
4363
always @*
4364
begin
4365
        iqentry_fpu1_issue = {QENTRIES{1'b0}};
4366
        iqentry_fpu2_issue = {QENTRIES{1'b0}};
4367
 
4368
        if (fpu1_available && fpu1_idle && `NUM_FPU > 0) begin
4369
                for (n = 0; n < QENTRIES; n = n + 1) begin
4370
                        if (could_issue[heads[n]] && iqentry_fpu[heads[n]]
4371
                        && iqentry_fpu1_issue == {QENTRIES{1'b0}}
4372
                        // If there are no valid queue entries prior it doesn't matter if there is
4373
                        // a sync.
4374
                        && (!(prior_sync[heads[n]]|prior_fsync[heads[n]]) || !prior_valid[heads[n]])
4375
                        )
4376
                          iqentry_fpu1_issue[heads[n]] = `TRUE;
4377
                end
4378
        end
4379
 
4380
        if (fpu2_available && fpu2_idle && `NUM_FPU > 1) begin
4381
                for (n = 0; n < QENTRIES; n = n + 1) begin
4382
                        if (could_issue[heads[n]] && iqentry_fpu[heads[n]]
4383
                        && !iqentry_fpu1_issue[heads[n]]
4384
                        && iqentry_fpu2_issue == {QENTRIES{1'b0}}
4385
                        && (!(prior_sync[heads[n]]|prior_fsync[heads[n]]) || !prior_valid[heads[n]])
4386
                        )
4387
                          iqentry_fpu2_issue[heads[n]] = `TRUE;
4388
                end
4389
        end
4390
end
4391
 
4392
reg [QENTRIES-1:0] nextqd;
4393
// Next queue id
4394
 
4395
/*
4396
reg [`QBITS] nids [0:QENTRIES-1];
4397
always @*
4398
for (n = 0; n < QENTRIES; n = n + 1)
4399
begin
4400
        nids[n] = n[`QBITS];
4401
        for (j = n; j != (n+1) % QENTRIES; j = (j - 1) % QENTRIES)
4402
                if (iqentry_thrd[(j+1)%QENTRIES]==iqentry_thrd[n])
4403
                        nids[n] = (j + 1) % QENTRIES;
4404
        // Add one more compare and set
4405
end
4406
*/
4407
 
4408
reg [`QBITS] nids [0:QENTRIES-1];
4409
always @*
4410
for (j = 0; j < QENTRIES; j = j + 1) begin
4411
        // We can't both start and stop at j
4412
        for (n = j; n != (j+1)%QENTRIES; n = (n + (QENTRIES-1)) % QENTRIES)
4413
                if (iqentry_thrd[n]==iqentry_thrd[j])
4414
                        nids[j] = n;
4415
        // Do the last one
4416
        if (iqentry_thrd[(j+1)%QENTRIES]==iqentry_thrd[j])
4417
                nids[j] = (j+1)%QENTRIES;
4418
end
4419
/*
4420
assign nids[0] = nid0;
4421
assign nids[1] = nid1;
4422
assign nids[2] = nid2;
4423
assign nids[3] = nid3;
4424
assign nids[4] = nid4;
4425
assign nids[5] = nid5;
4426
assign nids[6] = nid6;
4427
assign nids[7] = nid7;
4428
assign nids[8] = nid8;
4429
assign nids[9] = nid9;
4430
*/
4431
// Search the queue for the next entry on the same thread.
4432
reg [`QBITS] nid;
4433
always @*
4434
begin
4435
        nid = fcu_id;
4436
        for (n = QENTRIES-1; n > 0; n = n - 1)
4437
                if (iqentry_thrd[(fcu_id + n) % QENTRIES]==fcu_thrd)
4438
                        nid = (fcu_id + n) % QENTRIES;
4439
end
4440
/*
4441
always @*
4442
if (iqentry_thrd[idp1(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4443
        nid = idp1(fcu_id);
4444
else if (iqentry_thrd[idp2(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4445
        nid = idp2(fcu_id);
4446
else if (iqentry_thrd[idp3(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4447
        nid = idp3(fcu_id);
4448
else if (iqentry_thrd[idp4(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4449
        nid = idp4(fcu_id);
4450
else if (iqentry_thrd[idp5(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4451
        nid = idp5(fcu_id);
4452
else if (iqentry_thrd[idp6(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4453
        nid = idp6(fcu_id);
4454
else if (iqentry_thrd[idp7(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4455
        nid = idp7(fcu_id);
4456
else if (iqentry_thrd[idp8(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4457
        nid = idp8(fcu_id);
4458
else if (iqentry_thrd[idp9(fcu_id)]==iqentry_thrd[fcu_id[`QBITS]])
4459
        nid = idp9(fcu_id);
4460
else
4461
        nid = fcu_id;
4462
*/
4463
always @*
4464
for (n = 0; n < QENTRIES; n = n + 1)
4465
        nextqd[n] <= iqentry_sn[nids[n]] > iqentry_sn[n] || iqentry_v[n];
4466
 
4467
//assign nextqd = 8'hFF;
4468
 
4469
// Don't issue to the fcu until the following instruction is enqueued.
4470
// However, if the queue is full then issue anyway. A branch miss will likely occur.
4471
// Start search for instructions at head of queue (oldest instruction).
4472
always @*
4473
begin
4474
        iqentry_fcu_issue = {QENTRIES{1'b0}};
4475
 
4476
        if (fcu_done & ~branchmiss) begin
4477
                for (n = 0; n < QENTRIES; n = n + 1) begin
4478
                        if (could_issue[heads[n]] && iqentry_fc[heads[n]] && (nextqd[heads[n]] || iqentry_br[heads[n]])
4479
                        && iqentry_fcu_issue == {QENTRIES{1'b0}}
4480
                        && (!prior_sync[heads[n]] || !prior_valid[heads[n]])
4481
                        )
4482
                          iqentry_fcu_issue[heads[n]] = `TRUE;
4483
                end
4484
        end
4485
end
4486
 
4487
 
4488
// Test if a given address is in the write buffer. This is done only for the
4489
// first two queue slots to save logic on comparators.
4490
reg inwb0;
4491
always @*
4492
begin
4493
        inwb0 = FALSE;
4494
`ifdef HAS_WB
4495
        for (n = 0; n < `WB_DEPTH; n = n + 1)
4496
                if (iqentry_ma[heads[0]][AMSB:3]==wb_addr[n][AMSB:3] && wb_v[n])
4497
                        inwb0 = TRUE;
4498
`endif
4499
end
4500
 
4501
reg inwb1;
4502
always @*
4503
begin
4504
        inwb1 = FALSE;
4505
`ifdef HAS_WB
4506
        for (n = 0; n < `WB_DEPTH; n = n + 1)
4507
                if (iqentry_ma[heads[1]][AMSB:3]==wb_addr[n][AMSB:3] && wb_v[n])
4508
                        inwb1 = TRUE;
4509
`endif
4510
end
4511
 
4512
always @*
4513
begin
4514
        for (n = 0; n < QENTRIES; n = n + 1) begin
4515 61 robfinch
                iqentry_v[n] = iqentry_state[n] != IQS_INVALID;
4516
                iqentry_done[n] = iqentry_state[n]==IQS_DONE || iqentry_state[n]==IQS_CMT;
4517
                iqentry_out[n] = iqentry_state[n]==IQS_OUT;
4518
                iqentry_agen[n] = iqentry_state[n]==IQS_AGEN;
4519 60 robfinch
        end
4520
end
4521
 
4522
//
4523
// determine if the instructions ready to issue can, in fact, issue.
4524
// "ready" means that the instruction has valid operands but has not gone yet
4525
reg [1:0] issue_count, missue_count;
4526
generate begin : gMemIssue
4527
always @*
4528
begin
4529
        issue_count = 0;
4530
         memissue[ heads[0] ] =  iqentry_memready[ heads[0] ] && !(iqentry_load[heads[0]] && inwb0);               // first in line ... go as soon as ready
4531
         if (memissue[heads[0]])
4532
                issue_count = issue_count + 1;
4533
 
4534
         memissue[ heads[1] ] = ~iqentry_stomp[heads[1]] && iqentry_memready[ heads[1] ]                // addr and data are valid
4535
                                        && issue_count < `NUM_MEM
4536
                                        // ... and no preceding instruction is ready to go
4537
                                        //&& ~iqentry_memready[heads[0]]
4538
                                        // ... and there is no address-overlap with any preceding instruction
4539
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
4540
                                                || ((iqentry_ma[heads[1]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4541
                                        // ... if a release, any prior memory ops must be done before this one
4542
                                        && (iqentry_rl[heads[1]] ? iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]] : 1'b1)
4543
                                        // ... if a preivous op has the aquire bit set
4544
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4545
                                        // ... and there's nothing in the write buffer during a load
4546
                                        && !(iqentry_load[heads[1]] && (inwb1 || iqentry_store[heads[0]]))
4547
                                        // ... and, if it is a store, there is no chance of it being undone
4548
                                        && ((iqentry_load[heads[1]] && sple) ||
4549
                                           !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]]));
4550
         if (memissue[heads[1]])
4551
                issue_count = issue_count + 1;
4552
 
4553
         memissue[ heads[2] ] = ~iqentry_stomp[heads[2]] && iqentry_memready[ heads[2] ]                // addr and data are valid
4554
                                        // ... and no preceding instruction is ready to go
4555
                                        && issue_count < `NUM_MEM
4556
                                        //&& ~iqentry_memready[heads[0]]
4557
                                        //&& ~iqentry_memready[heads[1]] 
4558
                                        // ... and there is no address-overlap with any preceding instruction
4559
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]])  || iqentry_done[heads[0]]
4560
                                                || ((iqentry_ma[heads[2]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4561
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]])  || iqentry_done[heads[1]]
4562
                                                || ((iqentry_ma[heads[2]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
4563
                                        // ... if a release, any prior memory ops must be done before this one
4564
                                        && (iqentry_rl[heads[2]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4565
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4566
                                                                                         : 1'b1)
4567
                                        // ... if a preivous op has the aquire bit set
4568
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4569
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4570
                                        // ... and there's nothing in the write buffer during a load
4571
                                        && !(iqentry_load[heads[2]] && (wb_v!=1'b0
4572
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]]))
4573
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4574
            && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4575
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4576
                                        // ... and, if it is a SW, there is no chance of it being undone
4577
                                        && ((iqentry_load[heads[2]] && sple) ||
4578
                                              !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4579
                                           && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]]));
4580
         if (memissue[heads[2]])
4581
                issue_count = issue_count + 1;
4582
 
4583
         memissue[ heads[3] ] = ~iqentry_stomp[heads[3]] && iqentry_memready[ heads[3] ]                // addr and data are valid
4584
                                        // ... and no preceding instruction is ready to go
4585
                                        && issue_count < `NUM_MEM
4586
                                        //&& ~iqentry_memready[heads[0]]
4587
                                        //&& ~iqentry_memready[heads[1]] 
4588
                                        //&& ~iqentry_memready[heads[2]] 
4589
                                        // ... and there is no address-overlap with any preceding instruction
4590
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]])  || iqentry_done[heads[0]]
4591
                                                || ((iqentry_ma[heads[3]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4592
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]])  || iqentry_done[heads[1]]
4593
                                                || ((iqentry_ma[heads[3]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
4594
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]])  || iqentry_done[heads[2]]
4595
                                                || ((iqentry_ma[heads[3]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
4596
                                        // ... if a release, any prior memory ops must be done before this one
4597
                                        && (iqentry_rl[heads[3]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4598
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4599
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
4600
                                                                                         : 1'b1)
4601
                                        // ... if a preivous op has the aquire bit set
4602
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4603
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4604
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
4605
                                        // ... and there's nothing in the write buffer during a load
4606
                                        && !(iqentry_load[heads[3]] && (wb_v!=1'b0
4607
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]]))
4608
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4609
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4610
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
4611
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4612
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4613
                                )
4614
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4615
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
4616
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4617
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4618
                                )
4619
                    // ... and, if it is a SW, there is no chance of it being undone
4620
                                        && ((iqentry_load[heads[3]] && sple) ||
4621
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4622
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
4623
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]]));
4624
         if (memissue[heads[3]])
4625
                issue_count = issue_count + 1;
4626
 
4627
        if (QENTRIES > 4) begin
4628
         memissue[ heads[4] ] = ~iqentry_stomp[heads[4]] && iqentry_memready[ heads[4] ]                // addr and data are valid
4629
                                        // ... and no preceding instruction is ready to go
4630
                                        && issue_count < `NUM_MEM
4631
                                        //&& ~iqentry_memready[heads[0]]
4632
                                        //&& ~iqentry_memready[heads[1]] 
4633
                                        //&& ~iqentry_memready[heads[2]] 
4634
                                        //&& ~iqentry_memready[heads[3]] 
4635
                                        // ... and there is no address-overlap with any preceding instruction
4636
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]])  || iqentry_done[heads[0]]
4637
                                                || ((iqentry_ma[heads[4]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4638
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]])  || iqentry_done[heads[1]]
4639
                                                || ((iqentry_ma[heads[4]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
4640
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]])  || iqentry_done[heads[2]]
4641
                                                || ((iqentry_ma[heads[4]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
4642
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]])  || iqentry_done[heads[3]]
4643
                                                || ((iqentry_ma[heads[4]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3] || iqentry_out[heads[3]] || iqentry_done[heads[3]])))
4644
                                        // ... if a release, any prior memory ops must be done before this one
4645
                                        && (iqentry_rl[heads[4]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4646
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4647
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
4648
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
4649
                                                                                         : 1'b1)
4650
                                        // ... if a preivous op has the aquire bit set
4651
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4652
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4653
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
4654
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
4655
                                        // ... and there's nothing in the write buffer during a load
4656
                                        && !(iqentry_load[heads[4]] && (wb_v!=1'b0
4657
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]))
4658
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4659
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4660
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
4661
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4662
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4663
                                )
4664
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
4665
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4666
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4667
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4668
                                )
4669
                                && (!(iqentry_v[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4670
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
4671
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4672
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4673
                                )
4674
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
4675
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4676
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4677
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4678
                                )
4679
                                        // ... and, if it is a SW, there is no chance of it being undone
4680
                                        && ((iqentry_load[heads[4]] && sple) ||
4681
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4682
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
4683
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
4684
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]]));
4685
         if (memissue[heads[4]])
4686
                issue_count = issue_count + 1;
4687
        end
4688
 
4689
        if (QENTRIES > 5) begin
4690
         memissue[ heads[5] ] = ~iqentry_stomp[heads[5]] && iqentry_memready[ heads[5] ]                // addr and data are valid
4691
                                        // ... and no preceding instruction is ready to go
4692
                                        && issue_count < `NUM_MEM
4693
                                        //&& ~iqentry_memready[heads[0]]
4694
                                        //&& ~iqentry_memready[heads[1]] 
4695
                                        //&& ~iqentry_memready[heads[2]] 
4696
                                        //&& ~iqentry_memready[heads[3]] 
4697
                                        //&& ~iqentry_memready[heads[4]] 
4698
                                        // ... and there is no address-overlap with any preceding instruction
4699
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
4700
                                                || ((iqentry_ma[heads[5]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4701
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]]) || iqentry_done[heads[1]]
4702
                                                || ((iqentry_ma[heads[5]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
4703
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]]) || iqentry_done[heads[2]]
4704
                                                || ((iqentry_ma[heads[5]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
4705
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]]) || iqentry_done[heads[3]]
4706
                                                || ((iqentry_ma[heads[5]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3] || iqentry_out[heads[3]] || iqentry_done[heads[3]])))
4707
                                        && (!iqentry_mem[heads[4]] || (iqentry_agen[heads[4]] & iqentry_out[heads[4]]) || iqentry_done[heads[4]]
4708
                                                || ((iqentry_ma[heads[5]][AMSB:3] != iqentry_ma[heads[4]][AMSB:3] || iqentry_out[heads[4]] || iqentry_done[heads[4]])))
4709
                                        // ... if a release, any prior memory ops must be done before this one
4710
                                        && (iqentry_rl[heads[5]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4711
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4712
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
4713
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
4714
                                                                                 && (iqentry_done[heads[4]] || !iqentry_v[heads[4]] || !iqentry_mem[heads[4]])
4715
                                                                                         : 1'b1)
4716
                                        // ... if a preivous op has the aquire bit set
4717
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4718
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4719
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
4720
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
4721
                                        && !(iqentry_aq[heads[4]] && iqentry_v[heads[4]])
4722
                                        // ... and there's nothing in the write buffer during a load
4723
                                        && !(iqentry_load[heads[5]] && (wb_v!=1'b0
4724
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]
4725
                                                || iqentry_store[heads[4]]))
4726
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4727
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4728
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
4729
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4730
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4731
                                )
4732
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
4733
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4734
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4735
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4736
                                )
4737
                    && (!(iqentry_iv[heads[4]] && iqentry_memsb[heads[4]]) ||
4738
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4739
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4740
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4741
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4742
                                )
4743
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4744
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
4745
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4746
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4747
                                )
4748
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
4749
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4750
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4751
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4752
                                )
4753
                    && (!(iqentry_iv[heads[4]] && iqentry_memdb[heads[4]]) ||
4754
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4755
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4756
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4757
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4758
                                )
4759
                                        // ... and, if it is a SW, there is no chance of it being undone
4760
                                        && ((iqentry_load[heads[5]] && sple) ||
4761
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4762
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
4763
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
4764
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]])
4765
                       && !(iqentry_fc[heads[4]]||iqentry_canex[heads[4]]));
4766
         if (memissue[heads[5]])
4767
                issue_count = issue_count + 1;
4768
        end
4769
 
4770
`ifdef FULL_ISSUE_LOGIC
4771
if (QENTRIES > 6) begin
4772
 memissue[ heads[6] ] = ~iqentry_stomp[heads[6]] && iqentry_memready[ heads[6] ]                // addr and data are valid
4773
                                        // ... and no preceding instruction is ready to go
4774
                                        && issue_count < `NUM_MEM
4775
                                        //&& ~iqentry_memready[heads[0]]
4776
                                        //&& ~iqentry_memready[heads[1]] 
4777
                                        //&& ~iqentry_memready[heads[2]] 
4778
                                        //&& ~iqentry_memready[heads[3]] 
4779
                                        //&& ~iqentry_memready[heads[4]] 
4780
                                        //&& ~iqentry_memready[heads[5]] 
4781
                                        // ... and there is no address-overlap with any preceding instruction
4782
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
4783
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3])))
4784
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]]) || iqentry_done[heads[1]]
4785
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3])))
4786
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]]) || iqentry_done[heads[2]]
4787
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3])))
4788
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]]) || iqentry_done[heads[3]]
4789
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3])))
4790
                                        && (!iqentry_mem[heads[4]] || (iqentry_agen[heads[4]] & iqentry_out[heads[4]]) || iqentry_done[heads[4]]
4791
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[4]][AMSB:3])))
4792
                                        && (!iqentry_mem[heads[5]] || (iqentry_agen[heads[5]] & iqentry_out[heads[5]]) || iqentry_done[heads[5]]
4793
                                                || ((iqentry_ma[heads[6]][AMSB:3] != iqentry_ma[heads[5]][AMSB:3])))
4794
                                        && (iqentry_rl[heads[6]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4795
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4796
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
4797
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
4798
                                                                                 && (iqentry_done[heads[4]] || !iqentry_v[heads[4]] || !iqentry_mem[heads[4]])
4799
                                                                                 && (iqentry_done[heads[5]] || !iqentry_v[heads[5]] || !iqentry_mem[heads[5]])
4800
                                                                                         : 1'b1)
4801
                                        // ... if a preivous op has the aquire bit set
4802
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4803
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4804
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
4805
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
4806
                                        && !(iqentry_aq[heads[4]] && iqentry_v[heads[4]])
4807
                                        && !(iqentry_aq[heads[5]] && iqentry_v[heads[5]])
4808
                                        // ... and there's nothing in the write buffer during a load
4809
                                        && !(iqentry_load[heads[6]] && (wb_v!=1'b0
4810
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]
4811
                                                || iqentry_store[heads[4]] || iqentry_store[heads[5]]))
4812
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4813
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4814
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
4815
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4816
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4817
                                )
4818
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
4819
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4820
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4821
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4822
                                )
4823
                    && (!(iqentry_iv[heads[4]] && iqentry_memsb[heads[4]]) ||
4824
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4825
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4826
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4827
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4828
                                )
4829
                    && (!(iqentry_iv[heads[5]] && iqentry_memsb[heads[5]]) ||
4830
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4831
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4832
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4833
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4834
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
4835
                                )
4836
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4837
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
4838
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4839
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4840
                                )
4841
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
4842
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4843
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4844
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4845
                                )
4846
                    && (!(iqentry_iv[heads[4]] && iqentry_memdb[heads[4]]) ||
4847
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4848
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4849
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4850
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4851
                                )
4852
                    && (!(iqentry_iv[heads[5]] && iqentry_memdb[heads[5]]) ||
4853
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4854
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4855
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4856
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4857
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
4858
                                )
4859
                                        // ... and, if it is a SW, there is no chance of it being undone
4860
                                        && ((iqentry_load[heads[6]] && sple) ||
4861
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4862
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
4863
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
4864
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]])
4865
                       && !(iqentry_fc[heads[4]]||iqentry_canex[heads[4]])
4866
                       && !(iqentry_fc[heads[5]]||iqentry_canex[heads[5]]));
4867
         if (memissue[heads[6]])
4868
                issue_count = issue_count + 1;
4869
        end
4870
 
4871
        if (QENTRIES > 7) begin
4872
        memissue[ heads[7] ] =  ~iqentry_stomp[heads[7]] && iqentry_memready[ heads[7] ]                // addr and data are valid
4873
                                        // ... and no preceding instruction is ready to go
4874
                                        && issue_count < `NUM_MEM
4875
                                        //&& ~iqentry_memready[heads[0]]
4876
                                        //&& ~iqentry_memready[heads[1]] 
4877
                                        //&& ~iqentry_memready[heads[2]] 
4878
                                        //&& ~iqentry_memready[heads[3]] 
4879
                                        //&& ~iqentry_memready[heads[4]] 
4880
                                        //&& ~iqentry_memready[heads[5]] 
4881
                                        //&& ~iqentry_memready[heads[6]] 
4882
                                        // ... and there is no address-overlap with any preceding instruction
4883
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
4884
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
4885
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]]) || iqentry_done[heads[1]]
4886
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
4887
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]]) || iqentry_done[heads[2]]
4888
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
4889
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]]) || iqentry_done[heads[3]]
4890
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3] || iqentry_out[heads[3]] || iqentry_done[heads[3]])))
4891
                                        && (!iqentry_mem[heads[4]] || (iqentry_agen[heads[4]] & iqentry_out[heads[4]]) || iqentry_done[heads[4]]
4892
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[4]][AMSB:3] || iqentry_out[heads[4]] || iqentry_done[heads[4]])))
4893
                                        && (!iqentry_mem[heads[5]] || (iqentry_agen[heads[5]] & iqentry_out[heads[5]]) || iqentry_done[heads[5]]
4894
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[5]][AMSB:3] || iqentry_out[heads[5]] || iqentry_done[heads[5]])))
4895
                                        && (!iqentry_mem[heads[6]] || (iqentry_agen[heads[6]] & iqentry_out[heads[6]]) || iqentry_done[heads[6]]
4896
                                                || ((iqentry_ma[heads[7]][AMSB:3] != iqentry_ma[heads[6]][AMSB:3] || iqentry_out[heads[6]] || iqentry_done[heads[6]])))
4897
                                        && (iqentry_rl[heads[7]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
4898
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
4899
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
4900
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
4901
                                                                                 && (iqentry_done[heads[4]] || !iqentry_v[heads[4]] || !iqentry_mem[heads[4]])
4902
                                                                                 && (iqentry_done[heads[5]] || !iqentry_v[heads[5]] || !iqentry_mem[heads[5]])
4903
                                                                                 && (iqentry_done[heads[6]] || !iqentry_v[heads[6]] || !iqentry_mem[heads[6]])
4904
                                                                                         : 1'b1)
4905
                                        // ... if a preivous op has the aquire bit set
4906
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
4907
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
4908
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
4909
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
4910
                                        && !(iqentry_aq[heads[4]] && iqentry_v[heads[4]])
4911
                                        && !(iqentry_aq[heads[5]] && iqentry_v[heads[5]])
4912
                                        && !(iqentry_aq[heads[6]] && iqentry_v[heads[6]])
4913
                                        // ... and there's nothing in the write buffer during a load
4914
                                        && !(iqentry_load[heads[7]] && (wb_v!=1'b0
4915
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]
4916
                                                || iqentry_store[heads[4]] || iqentry_store[heads[5]] || iqentry_store[heads[6]]))
4917
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
4918
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4919
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
4920
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4921
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4922
                                )
4923
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
4924
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4925
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4926
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4927
                                )
4928
                    && (!(iqentry_iv[heads[4]] && iqentry_memsb[heads[4]]) ||
4929
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4930
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4931
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4932
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4933
                                )
4934
                    && (!(iqentry_iv[heads[5]] && iqentry_memsb[heads[5]]) ||
4935
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4936
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4937
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4938
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4939
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
4940
                                )
4941
                    && (!(iqentry_iv[heads[6]] && iqentry_memsb[heads[6]]) ||
4942
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4943
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4944
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4945
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4946
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
4947
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
4948
                                )
4949
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
4950
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
4951
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4952
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
4953
                                )
4954
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
4955
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4956
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4957
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
4958
                                )
4959
                    && (!(iqentry_iv[heads[4]] && iqentry_memdb[heads[4]]) ||
4960
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4961
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4962
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4963
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
4964
                                )
4965
                    && (!(iqentry_iv[heads[5]] && iqentry_memdb[heads[5]]) ||
4966
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4967
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4968
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4969
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4970
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
4971
                                )
4972
                    && (!(iqentry_iv[heads[6]] && iqentry_memdb[heads[6]]) ||
4973
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
4974
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
4975
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
4976
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
4977
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
4978
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
4979
                                )
4980
                                        // ... and, if it is a SW, there is no chance of it being undone
4981
                                        && ((iqentry_load[heads[7]] && sple) ||
4982
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
4983
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
4984
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
4985
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]])
4986
                       && !(iqentry_fc[heads[4]]||iqentry_canex[heads[4]])
4987
                       && !(iqentry_fc[heads[5]]||iqentry_canex[heads[5]])
4988
                       && !(iqentry_fc[heads[6]]||iqentry_canex[heads[6]]));
4989
         if (memissue[heads[7]])
4990
                issue_count = issue_count + 1;
4991
        end
4992
 
4993
        if (QENTRIES > 8) begin
4994
        memissue[ heads[8] ] =  ~iqentry_stomp[heads[8]] && iqentry_memready[ heads[8] ]                // addr and data are valid
4995
                                        // ... and no preceding instruction is ready to go
4996
                                        && issue_count < `NUM_MEM
4997
                                        //&& ~iqentry_memready[heads[0]]
4998
                                        //&& ~iqentry_memready[heads[1]] 
4999
                                        //&& ~iqentry_memready[heads[2]] 
5000
                                        //&& ~iqentry_memready[heads[3]] 
5001
                                        //&& ~iqentry_memready[heads[4]] 
5002
                                        //&& ~iqentry_memready[heads[5]] 
5003
                                        //&& ~iqentry_memready[heads[6]] 
5004
                                        // ... and there is no address-overlap with any preceding instruction
5005
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
5006
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
5007
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]]) || iqentry_done[heads[1]]
5008
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
5009
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]]) || iqentry_done[heads[2]]
5010
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
5011
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]]) || iqentry_done[heads[3]]
5012
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3] || iqentry_out[heads[3]] || iqentry_done[heads[3]])))
5013
                                        && (!iqentry_mem[heads[4]] || (iqentry_agen[heads[4]] & iqentry_out[heads[4]]) || iqentry_done[heads[4]]
5014
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[4]][AMSB:3] || iqentry_out[heads[4]] || iqentry_done[heads[4]])))
5015
                                        && (!iqentry_mem[heads[5]] || (iqentry_agen[heads[5]] & iqentry_out[heads[5]]) || iqentry_done[heads[5]]
5016
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[5]][AMSB:3] || iqentry_out[heads[5]] || iqentry_done[heads[5]])))
5017
                                        && (!iqentry_mem[heads[6]] || (iqentry_agen[heads[6]] & iqentry_out[heads[6]]) || iqentry_done[heads[6]]
5018
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[6]][AMSB:3] || iqentry_out[heads[6]] || iqentry_done[heads[6]])))
5019
                                        && (!iqentry_mem[heads[7]] || (iqentry_agen[heads[7]] & iqentry_out[heads[7]]) || iqentry_done[heads[7]]
5020
                                                || ((iqentry_ma[heads[8]][AMSB:3] != iqentry_ma[heads[7]][AMSB:3] || iqentry_out[heads[7]] || iqentry_done[heads[7]])))
5021
                                        && (iqentry_rl[heads[8]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
5022
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
5023
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
5024
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
5025
                                                                                 && (iqentry_done[heads[4]] || !iqentry_v[heads[4]] || !iqentry_mem[heads[4]])
5026
                                                                                 && (iqentry_done[heads[5]] || !iqentry_v[heads[5]] || !iqentry_mem[heads[5]])
5027
                                                                                 && (iqentry_done[heads[6]] || !iqentry_v[heads[6]] || !iqentry_mem[heads[6]])
5028
                                                                                 && (iqentry_done[heads[7]] || !iqentry_v[heads[7]] || !iqentry_mem[heads[7]])
5029
                                                                                         : 1'b1)
5030
                                        // ... if a preivous op has the aquire bit set
5031
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
5032
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
5033
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
5034
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
5035
                                        && !(iqentry_aq[heads[4]] && iqentry_v[heads[4]])
5036
                                        && !(iqentry_aq[heads[5]] && iqentry_v[heads[5]])
5037
                                        && !(iqentry_aq[heads[6]] && iqentry_v[heads[6]])
5038
                                        && !(iqentry_aq[heads[7]] && iqentry_v[heads[7]])
5039
                                        // ... and there's nothing in the write buffer during a load
5040
                                        && !(iqentry_load[heads[8]] && (wb_v!=1'b0
5041
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]
5042
                                                || iqentry_store[heads[4]] || iqentry_store[heads[5]] || iqentry_store[heads[6]] || iqentry_store[heads[7]]))
5043
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
5044
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
5045
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
5046
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5047
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
5048
                                )
5049
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
5050
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5051
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5052
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
5053
                                )
5054
                    && (!(iqentry_iv[heads[4]] && iqentry_memsb[heads[4]]) ||
5055
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5056
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5057
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5058
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
5059
                                )
5060
                    && (!(iqentry_iv[heads[5]] && iqentry_memsb[heads[5]]) ||
5061
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5062
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5063
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5064
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5065
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
5066
                                )
5067
                    && (!(iqentry_iv[heads[6]] && iqentry_memsb[heads[6]]) ||
5068
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5069
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5070
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5071
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5072
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5073
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
5074
                                )
5075
                    && (!(iqentry_iv[heads[7]] && iqentry_memsb[heads[7]]) ||
5076
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5077
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5078
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5079
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5080
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5081
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5082
                                &&   (iqentry_done[heads[6]] || !iqentry_v[heads[6]])
5083
                                )
5084
                                )
5085
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
5086
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
5087
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5088
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
5089
                                )
5090
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
5091
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5092
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5093
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
5094
                                )
5095
                    && (!(iqentry_iv[heads[4]] && iqentry_memdb[heads[4]]) ||
5096
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5097
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5098
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5099
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
5100
                                )
5101
                    && (!(iqentry_iv[heads[5]] && iqentry_memdb[heads[5]]) ||
5102
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5103
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5104
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5105
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5106
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
5107
                                )
5108
                    && (!(iqentry_iv[heads[6]] && iqentry_memdb[heads[6]]) ||
5109
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5110
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5111
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5112
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5113
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5114
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
5115
                                )
5116
                    && (!(iqentry_iv[heads[7]] && iqentry_memdb[heads[7]]) ||
5117
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5118
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5119
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5120
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5121
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5122
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5123
                                && (!iqentry_mem[heads[6]] || iqentry_done[heads[6]] || !iqentry_v[heads[6]])
5124
                                )
5125
                                )
5126
                                        // ... and, if it is a SW, there is no chance of it being undone
5127
                                        && ((iqentry_load[heads[8]] && sple) ||
5128
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
5129
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
5130
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
5131
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]])
5132
                       && !(iqentry_fc[heads[4]]||iqentry_canex[heads[4]])
5133
                       && !(iqentry_fc[heads[5]]||iqentry_canex[heads[5]])
5134
                       && !(iqentry_fc[heads[6]]||iqentry_canex[heads[6]])
5135
                       && !(iqentry_fc[heads[7]]||iqentry_canex[heads[7]])
5136
                       );
5137
         if (memissue[heads[8]])
5138
                issue_count = issue_count + 1;
5139
        end
5140
 
5141
        if (QENTRIES > 9) begin
5142
        memissue[ heads[9] ] =  ~iqentry_stomp[heads[9]] && iqentry_memready[ heads[9] ]                // addr and data are valid
5143
                                        // ... and no preceding instruction is ready to go
5144
                                        && issue_count < `NUM_MEM
5145
                                        //&& ~iqentry_memready[heads[0]]
5146
                                        //&& ~iqentry_memready[heads[1]] 
5147
                                        //&& ~iqentry_memready[heads[2]] 
5148
                                        //&& ~iqentry_memready[heads[3]] 
5149
                                        //&& ~iqentry_memready[heads[4]] 
5150
                                        //&& ~iqentry_memready[heads[5]] 
5151
                                        //&& ~iqentry_memready[heads[6]] 
5152
                                        // ... and there is no address-overlap with any preceding instruction
5153
                                        && (!iqentry_mem[heads[0]] || (iqentry_agen[heads[0]] & iqentry_out[heads[0]]) || iqentry_done[heads[0]]
5154
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[0]][AMSB:3] || iqentry_out[heads[0]] || iqentry_done[heads[0]])))
5155
                                        && (!iqentry_mem[heads[1]] || (iqentry_agen[heads[1]] & iqentry_out[heads[1]]) || iqentry_done[heads[1]]
5156
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[1]][AMSB:3] || iqentry_out[heads[1]] || iqentry_done[heads[1]])))
5157
                                        && (!iqentry_mem[heads[2]] || (iqentry_agen[heads[2]] & iqentry_out[heads[2]]) || iqentry_done[heads[2]]
5158
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[2]][AMSB:3] || iqentry_out[heads[2]] || iqentry_done[heads[2]])))
5159
                                        && (!iqentry_mem[heads[3]] || (iqentry_agen[heads[3]] & iqentry_out[heads[3]]) || iqentry_done[heads[3]]
5160
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[3]][AMSB:3] || iqentry_out[heads[3]] || iqentry_done[heads[3]])))
5161
                                        && (!iqentry_mem[heads[4]] || (iqentry_agen[heads[4]] & iqentry_out[heads[4]]) || iqentry_done[heads[4]]
5162
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[4]][AMSB:3] || iqentry_out[heads[4]] || iqentry_done[heads[4]])))
5163
                                        && (!iqentry_mem[heads[5]] || (iqentry_agen[heads[5]] & iqentry_out[heads[5]]) || iqentry_done[heads[5]]
5164
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[5]][AMSB:3] || iqentry_out[heads[5]] || iqentry_done[heads[5]])))
5165
                                        && (!iqentry_mem[heads[6]] || (iqentry_agen[heads[6]] & iqentry_out[heads[6]]) || iqentry_done[heads[6]]
5166
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[6]][AMSB:3] || iqentry_out[heads[6]] || iqentry_done[heads[6]])))
5167
                                        && (!iqentry_mem[heads[7]] || (iqentry_agen[heads[7]] & iqentry_out[heads[7]]) || iqentry_done[heads[7]]
5168
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[7]][AMSB:3] || iqentry_out[heads[7]] || iqentry_done[heads[7]])))
5169
                                        && (!iqentry_mem[heads[8]] || (iqentry_agen[heads[8]] & iqentry_out[heads[8]]) || iqentry_done[heads[8]]
5170
                                                || ((iqentry_ma[heads[9]][AMSB:3] != iqentry_ma[heads[8]][AMSB:3] || iqentry_out[heads[8]] || iqentry_done[heads[8]])))
5171
                                        && (iqentry_rl[heads[9]] ? (iqentry_done[heads[0]] || !iqentry_v[heads[0]] || !iqentry_mem[heads[0]])
5172
                                                                                 && (iqentry_done[heads[1]] || !iqentry_v[heads[1]] || !iqentry_mem[heads[1]])
5173
                                                                                 && (iqentry_done[heads[2]] || !iqentry_v[heads[2]] || !iqentry_mem[heads[2]])
5174
                                                                                 && (iqentry_done[heads[3]] || !iqentry_v[heads[3]] || !iqentry_mem[heads[3]])
5175
                                                                                 && (iqentry_done[heads[4]] || !iqentry_v[heads[4]] || !iqentry_mem[heads[4]])
5176
                                                                                 && (iqentry_done[heads[5]] || !iqentry_v[heads[5]] || !iqentry_mem[heads[5]])
5177
                                                                                 && (iqentry_done[heads[6]] || !iqentry_v[heads[6]] || !iqentry_mem[heads[6]])
5178
                                                                                 && (iqentry_done[heads[7]] || !iqentry_v[heads[7]] || !iqentry_mem[heads[7]])
5179
                                                                                 && (iqentry_done[heads[8]] || !iqentry_v[heads[8]] || !iqentry_mem[heads[8]])
5180
                                                                                         : 1'b1)
5181
                                        // ... if a preivous op has the aquire bit set
5182
                                        && !(iqentry_aq[heads[0]] && iqentry_v[heads[0]])
5183
                                        && !(iqentry_aq[heads[1]] && iqentry_v[heads[1]])
5184
                                        && !(iqentry_aq[heads[2]] && iqentry_v[heads[2]])
5185
                                        && !(iqentry_aq[heads[3]] && iqentry_v[heads[3]])
5186
                                        && !(iqentry_aq[heads[4]] && iqentry_v[heads[4]])
5187
                                        && !(iqentry_aq[heads[5]] && iqentry_v[heads[5]])
5188
                                        && !(iqentry_aq[heads[6]] && iqentry_v[heads[6]])
5189
                                        && !(iqentry_aq[heads[7]] && iqentry_v[heads[7]])
5190
                                        && !(iqentry_aq[heads[8]] && iqentry_v[heads[8]])
5191
                                        // ... and there's nothing in the write buffer during a load
5192
                                        && !(iqentry_load[heads[9]] && (wb_v!=1'b0
5193
                                                || iqentry_store[heads[0]] || iqentry_store[heads[1]] || iqentry_store[heads[2]] || iqentry_store[heads[3]]
5194
                                                || iqentry_store[heads[4]] || iqentry_store[heads[5]] || iqentry_store[heads[6]] || iqentry_store[heads[7]]
5195
                                                || iqentry_store[heads[8]]))
5196
                                        // ... and there isn't a barrier, or everything before the barrier is done or invalid
5197
                    && (!(iqentry_iv[heads[1]] && iqentry_memsb[heads[1]]) || (iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
5198
                    && (!(iqentry_iv[heads[2]] && iqentry_memsb[heads[2]]) ||
5199
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5200
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
5201
                                )
5202
                    && (!(iqentry_iv[heads[3]] && iqentry_memsb[heads[3]]) ||
5203
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5204
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5205
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
5206
                                )
5207
                    && (!(iqentry_iv[heads[4]] && iqentry_memsb[heads[4]]) ||
5208
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5209
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5210
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5211
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
5212
                                )
5213
                    && (!(iqentry_iv[heads[5]] && iqentry_memsb[heads[5]]) ||
5214
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5215
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5216
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5217
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5218
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
5219
                                )
5220
                    && (!(iqentry_iv[heads[6]] && iqentry_memsb[heads[6]]) ||
5221
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5222
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5223
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5224
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5225
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5226
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
5227
                                )
5228
                    && (!(iqentry_iv[heads[7]] && iqentry_memsb[heads[7]]) ||
5229
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5230
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5231
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5232
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5233
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5234
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5235
                                &&   (iqentry_done[heads[6]] || !iqentry_v[heads[6]]))
5236
                                )
5237
                    && (!(iqentry_iv[heads[8]] && iqentry_memsb[heads[8]]) ||
5238
                                        ((iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5239
                                &&   (iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5240
                                &&   (iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5241
                                &&   (iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5242
                                &&   (iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5243
                                &&   (iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5244
                                &&   (iqentry_done[heads[6]] || !iqentry_v[heads[6]])
5245
                                &&   (iqentry_done[heads[7]] || !iqentry_v[heads[7]])
5246
                                )
5247
                                )
5248
                                && (!(iqentry_iv[heads[1]] && iqentry_memdb[heads[1]]) || (!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]]))
5249
                    && (!(iqentry_iv[heads[2]] && iqentry_memdb[heads[2]]) ||
5250
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5251
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]]))
5252
                                )
5253
                    && (!(iqentry_iv[heads[3]] && iqentry_memdb[heads[3]]) ||
5254
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5255
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5256
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]]))
5257
                                )
5258
                    && (!(iqentry_iv[heads[4]] && iqentry_memdb[heads[4]]) ||
5259
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5260
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5261
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5262
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]]))
5263
                                )
5264
                    && (!(iqentry_iv[heads[5]] && iqentry_memdb[heads[5]]) ||
5265
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5266
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5267
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5268
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5269
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]]))
5270
                                )
5271
                    && (!(iqentry_iv[heads[6]] && iqentry_memdb[heads[6]]) ||
5272
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5273
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5274
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5275
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5276
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5277
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]]))
5278
                                )
5279
                    && (!(iqentry_iv[heads[7]] && iqentry_memdb[heads[7]]) ||
5280
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5281
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5282
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5283
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5284
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5285
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5286
                                && (!iqentry_mem[heads[6]] || iqentry_done[heads[6]] || !iqentry_v[heads[6]]))
5287
                                )
5288
                    && (!(iqentry_iv[heads[8]] && iqentry_memdb[heads[8]]) ||
5289
                                  ((!iqentry_mem[heads[0]] || iqentry_done[heads[0]] || !iqentry_v[heads[0]])
5290
                                && (!iqentry_mem[heads[1]] || iqentry_done[heads[1]] || !iqentry_v[heads[1]])
5291
                                && (!iqentry_mem[heads[2]] || iqentry_done[heads[2]] || !iqentry_v[heads[2]])
5292
                                && (!iqentry_mem[heads[3]] || iqentry_done[heads[3]] || !iqentry_v[heads[3]])
5293
                                && (!iqentry_mem[heads[4]] || iqentry_done[heads[4]] || !iqentry_v[heads[4]])
5294
                                && (!iqentry_mem[heads[5]] || iqentry_done[heads[5]] || !iqentry_v[heads[5]])
5295
                                && (!iqentry_mem[heads[6]] || iqentry_done[heads[6]] || !iqentry_v[heads[6]])
5296
                                && (!iqentry_mem[heads[7]] || iqentry_done[heads[7]] || !iqentry_v[heads[7]])
5297
                                )
5298
                                )
5299
                                        // ... and, if it is a store, there is no chance of it being undone
5300
                                        && ((iqentry_load[heads[9]] && sple) ||
5301
                                      !(iqentry_fc[heads[0]]||iqentry_canex[heads[0]])
5302
                       && !(iqentry_fc[heads[1]]||iqentry_canex[heads[1]])
5303
                       && !(iqentry_fc[heads[2]]||iqentry_canex[heads[2]])
5304
                       && !(iqentry_fc[heads[3]]||iqentry_canex[heads[3]])
5305
                       && !(iqentry_fc[heads[4]]||iqentry_canex[heads[4]])
5306
                       && !(iqentry_fc[heads[5]]||iqentry_canex[heads[5]])
5307
                       && !(iqentry_fc[heads[6]]||iqentry_canex[heads[6]])
5308
                       && !(iqentry_fc[heads[7]]||iqentry_canex[heads[7]])
5309
                       && !(iqentry_fc[heads[8]]||iqentry_canex[heads[8]])
5310
                       );
5311
         if (memissue[heads[9]])
5312
                issue_count = issue_count + 1;
5313
        end
5314
end
5315
end
5316
endgenerate
5317
`endif
5318
 
5319
// Starts search for instructions to issue at the head of the queue and 
5320
// progresses from there. This ensures that the oldest instructions are
5321
// selected first for processing.
5322
always @*
5323
begin
5324
        last_issue0 = QENTRIES;
5325
        last_issue1 = QENTRIES;
5326
        last_issue2 = QENTRIES;
5327
        for (n = 0; n < QENTRIES; n = n + 1)
5328 61 robfinch
    if (~iqentry_stomp[heads[n]] && iqentry_memissue[heads[n]] && !iqentry_done[heads[n]] && iqentry_v[heads[n]]) begin
5329 60 robfinch
      if (mem1_available && dram0 == `DRAMSLOT_AVAIL) begin
5330
       last_issue0 = heads[n];
5331
      end
5332
    end
5333
        for (n = 0; n < QENTRIES; n = n + 1)
5334
    if (~iqentry_stomp[heads[n]] && iqentry_memissue[heads[n]]) begin
5335
        if (mem2_available && heads[n] != last_issue0 && `NUM_MEM > 1) begin
5336
        if (dram1 == `DRAMSLOT_AVAIL) begin
5337
                                        last_issue1 = heads[n];
5338
        end
5339
        end
5340
    end
5341
        for (n = 0; n < QENTRIES; n = n + 1)
5342
    if (~iqentry_stomp[heads[n]] && iqentry_memissue[heads[n]]) begin
5343
        if (mem3_available && heads[n] != last_issue0 && heads[n] != last_issue1 && `NUM_MEM > 2) begin
5344
        if (dram2 == `DRAMSLOT_AVAIL) begin
5345
                last_issue2 = heads[n];
5346
        end
5347
        end
5348
    end
5349
end
5350
 
5351 66 robfinch
reg [2:0] wbptr = 2'd0;
5352 60 robfinch
// Stomp logic for branch miss.
5353
/*
5354
FT64_stomp #(QENTRIES) ustmp1
5355
(
5356
        .branchmiss(branchmiss),
5357
        .branchmiss_thrd(branchmiss_thrd),
5358
        .missid(missid),
5359
        .head0(heads[0]),
5360
        .thrd(iqentry_thrd),
5361
        .iqentry_v(iqentry_v),
5362
        .stomp(iqentry_stomp)
5363
);
5364
*/
5365
always @*
5366
begin
5367
        iqentry_stomp <= 1'b0;
5368
        if (branchmiss) begin
5369
                for (n = 0; n < QENTRIES; n = n + 1) begin
5370
                        if (iqentry_v[n] && iqentry_thrd[n]==branchmiss_thrd) begin
5371
                                if (iqentry_sn[n] > iqentry_sn[missid[`QBITS]])
5372
                                        iqentry_stomp[n] <= `TRUE;
5373
                        end
5374
                end
5375
        end
5376
        /*
5377
        if (fcu_branchmiss) begin
5378
                for (n = 0; n < QENTRIES; n = n + 1) begin
5379
                        if (iqentry_v[n] && iqentry_thrd[n]==fcu_thrd) begin
5380
                                if (iqentry_sn[n] > iqentry_sn[fcu_id[`QBITS]])
5381
                                        iqentry_stomp[n] <= `TRUE;
5382
                        end
5383
                end
5384
        end
5385
        */
5386
end
5387
 
5388
always @*
5389
begin
5390
        stompedOnRets = 1'b0;
5391
        for (n = 0; n < QENTRIES; n = n + 1)
5392
                if (iqentry_stomp[n] && iqentry_ret[n])
5393
                        stompedOnRets = stompedOnRets + 4'd1;
5394
end
5395
 
5396
reg id1_vi, id2_vi, id3_vi;
5397
wire [4:0] id1_ido, id2_ido, id3_ido;
5398
wire id1_vo, id2_vo, id3_vo;
5399
wire id1_clk, id2_clk, id3_clk;
5400
 
5401
// Always at least one decoder
5402 66 robfinch
BUFH uidclk (.I(clk_i), .O(id1_clk));
5403
//assign id1_clk = clk_i;
5404 60 robfinch
//BUFGCE uclkb2
5405
//(
5406
//      .I(clk_i),
5407
//      .CE(id1_available),
5408
//      .O(id1_clk)
5409
//);
5410
 
5411
FT64_idecoder uid1
5412
(
5413
        .clk(id1_clk),
5414
        .idv_i(id1_vi),
5415
        .id_i(id1_id),
5416
`ifdef INLINE_DECODE
5417
        .instr(fetchbuf0_instr),
5418
        .Rt(Rt0[4:0]),
5419
        .predict_taken(predict_taken0),
5420
        .thrd(fetchbuf0_thrd),
5421
        .vl(vl),
5422
`else
5423
        .instr(id1_instr),
5424
        .Rt(id1_Rt),
5425
        .predict_taken(id1_pt),
5426
        .thrd(id1_thrd),
5427
        .vl(id1_vl),
5428
`endif
5429
//ToDo: fix for vectors length and element number
5430
        .ven(id1_ven),
5431
        .bus(id1_bus),
5432
        .id_o(id1_ido),
5433
        .idv_o(id1_vo),
5434
        .debug_on(debug_on),
5435
        .pred_on(pred_on)
5436
);
5437
/*
5438
`ifdef INLINE_DECODE
5439
        id1_Rt <= Rt0[4:0];
5440
        id1_vl <= vl;
5441
        id1_ven <= venno;
5442
        id1_id <= tail;
5443
        id1_pt <= predict_taken0;
5444
        id1_thrd <= fetchbuf0_thrd;
5445
        setinsn1(tail,id1_bus);
5446
`endif
5447
*/
5448
generate begin : gIDUInst
5449
if (`NUM_IDU > 1) begin
5450
//BUFGCE uclkb3
5451
//(
5452
//      .I(clk_i),
5453
//      .CE(id2_available),
5454
//      .O(id2_clk)
5455
//);
5456
assign id2_clk = clk_i;
5457
 
5458
FT64_idecoder uid2
5459
(
5460
        .clk(id2_clk),
5461
        .idv_i(id2_vi),
5462
        .id_i(id2_id),
5463
`ifdef INLINE_DECODE
5464
        .instr(fetchbuf1_instr),
5465
        .Rt(Rt1[4:0]),
5466
        .predict_taken(predict_taken1),
5467
        .thrd(fetchbuf1_thrd),
5468
        .vl(vl),
5469
`else
5470
        .instr(id2_instr),
5471
        .Rt(id2_Rt),
5472
        .predict_taken(id2_pt),
5473
        .thrd(id2_thrd),
5474
        .vl(id2_vl),
5475
`endif
5476
        .ven(id2_ven),
5477
        .bus(id2_bus),
5478
        .id_o(id2_ido),
5479
        .idv_o(id2_vo),
5480
        .debug_on(debug_on),
5481
        .pred_on(pred_on)
5482
);
5483
end
5484
if (`NUM_IDU > 2) begin
5485
//BUFGCE uclkb4
5486
//(
5487
//      .I(clk_i),
5488
//      .CE(id3_available),
5489
//      .O(id3_clk)
5490
//);
5491
assign id3_clk = clk_i;
5492
 
5493
FT64_idecoder uid2
5494
(
5495
        .clk(id3_clk),
5496
        .idv_i(id3_vi),
5497
        .id_i(id3_id),
5498
`ifdef INLINE_DECODE
5499
        .instr(fetchbuf2_instr),
5500
        .Rt(Rt2[4:0]),
5501
        .predict_taken(predict_taken2),
5502
        .thrd(fetchbuf2_thrd),
5503
        .vl(vl),
5504
`else
5505
        .instr(id3_instr),
5506
        .Rt(id3_Rt),
5507
        .predict_taken(id3_pt),
5508
        .thrd(id3_thrd),
5509
        .vl(id3_vl),
5510
`endif
5511
        .ven(id3_ven),
5512
        .bus(id3_bus),
5513
        .id_o(id3_ido),
5514
        .idv_o(id3_vo),
5515
        .debug_on(debug_on),
5516
        .pred_on(pred_on)
5517
);
5518
end
5519
end
5520
endgenerate
5521
 
5522
//
5523
// EXECUTE
5524
//
5525
wire [15:0] lfsro;
5526
lfsr #(16,16'hACE4) u1 (rst, clk, 1'b1, 1'b0, lfsro);
5527
 
5528
reg [63:0] csr_r;
5529
wire [11:0] csrno = alu0_instr[29:18];
5530
always @*
5531
begin
5532
`ifdef SUPPORT_SMT
5533
    if (csrno[11:10] >= ol[alu0_thrd])
5534
`else
5535
    if (csrno[11:10] >= ol)
5536
`endif
5537
    casez(csrno[9:0])
5538
    `CSR_CR0:       csr_r <= cr0;
5539
    `CSR_HARTID:    csr_r <= hartid;
5540
    `CSR_TICK:      csr_r <= tick;
5541
    `CSR_PCR:       csr_r <= pcr;
5542
    `CSR_PCR2:      csr_r <= pcr2;
5543
    `CSR_PMR:                           csr_r <= pmr;
5544
    `CSR_WBRCD:         csr_r <= wbrcd;
5545
    `CSR_SEMA:      csr_r <= sema;
5546
    `CSR_KEYS:                  csr_r <= keys;
5547
    `CSR_TCB:           csr_r <= tcb;
5548
    `CSR_FSTAT:     csr_r <= {fp_rgs,fp_status};
5549
`ifdef SUPPORT_DBG
5550
    `CSR_DBAD0:     csr_r <= dbg_adr0;
5551
    `CSR_DBAD1:     csr_r <= dbg_adr1;
5552
    `CSR_DBAD2:     csr_r <= dbg_adr2;
5553
    `CSR_DBAD3:     csr_r <= dbg_adr3;
5554
    `CSR_DBCTRL:    csr_r <= dbg_ctrl;
5555
    `CSR_DBSTAT:    csr_r <= dbg_stat;
5556
`endif
5557
    `CSR_CAS:       csr_r <= cas;
5558
    `CSR_TVEC:      csr_r <= tvec[csrno[2:0]];
5559
    `CSR_BADADR:    csr_r <= badaddr[{alu0_thrd,csrno[11:10]}];
5560
    `CSR_BADINSTR:      csr_r <= bad_instr[{alu0_thrd,csrno[11:10]}];
5561
    `CSR_CAUSE:     csr_r <= {48'd0,cause[{alu0_thrd,csrno[11:10]}]};
5562
`ifdef SUPPORT_SMT
5563 66 robfinch
    `CSR_ODL_STACK:     csr_r <= {16'h0,dl_stack[alu0_thrd],16'h0,ol_stack[alu0_thrd]};
5564 60 robfinch
    `CSR_IM_STACK:      csr_r <= im_stack[alu0_thrd];
5565
    `CSR_PL_STACK:      csr_r <= pl_stack[alu0_thrd];
5566
    `CSR_RS_STACK:      csr_r <= rs_stack[alu0_thrd];
5567
    `CSR_STATUS:    csr_r <= mstatus[alu0_thrd][63:0];
5568
    `CSR_BRS_STACK:     csr_r <= brs_stack[alu0_thrd];
5569
    `CSR_EPC0:      csr_r <= epc0[alu0_thrd];
5570
    `CSR_EPC1:      csr_r <= epc1[alu0_thrd];
5571
    `CSR_EPC2:      csr_r <= epc2[alu0_thrd];
5572
    `CSR_EPC3:      csr_r <= epc3[alu0_thrd];
5573
    `CSR_EPC4:      csr_r <= epc4[alu0_thrd];
5574
    `CSR_EPC5:      csr_r <= epc5[alu0_thrd];
5575
    `CSR_EPC6:      csr_r <= epc6[alu0_thrd];
5576
    `CSR_EPC7:      csr_r <= epc7[alu0_thrd];
5577
`else
5578 66 robfinch
    `CSR_ODL_STACK:     csr_r <= {16'h0,dl_stack,16'h0,ol_stack};
5579 60 robfinch
    `CSR_IM_STACK:      csr_r <= im_stack;
5580
    `CSR_PL_STACK:      csr_r <= pl_stack;
5581
    `CSR_RS_STACK:      csr_r <= rs_stack;
5582
    `CSR_STATUS:    csr_r <= mstatus[63:0];
5583
    `CSR_BRS_STACK:     csr_r <= brs_stack;
5584
    `CSR_EPC0:      csr_r <= epc0;
5585
    `CSR_EPC1:      csr_r <= epc1;
5586
    `CSR_EPC2:      csr_r <= epc2;
5587
    `CSR_EPC3:      csr_r <= epc3;
5588
    `CSR_EPC4:      csr_r <= epc4;
5589
    `CSR_EPC5:      csr_r <= epc5;
5590
    `CSR_EPC6:      csr_r <= epc6;
5591
    `CSR_EPC7:      csr_r <= epc7;
5592
`endif
5593
    `CSR_CODEBUF:   csr_r <= codebuf[csrno[5:0]];
5594
`ifdef SUPPORT_BBMS
5595
                `CSR_TB:                        csr_r <= tb;
5596
                `CSR_CBL:                       csr_r <= cbl;
5597
                `CSR_CBU:                       csr_r <= cbu;
5598
                `CSR_RO:                        csr_r <= ro;
5599
                `CSR_DBL:                       csr_r <= dbl;
5600
                `CSR_DBU:                       csr_r <= dbu;
5601
                `CSR_SBL:                       csr_r <= sbl;
5602
                `CSR_SBU:                       csr_r <= sbu;
5603
                `CSR_ENU:                       csr_r <= en;
5604
`endif
5605
    `CSR_Q_CTR:         csr_r <= iq_ctr;
5606
    `CSR_BM_CTR:        csr_r <= bm_ctr;
5607
    `CSR_ICL_CTR:       csr_r <= icl_ctr;
5608
    `CSR_IRQ_CTR:       csr_r <= irq_ctr;
5609
    `CSR_TIME:          csr_r <= wc_times;
5610
    `CSR_INFO:
5611
                    case(csrno[3:0])
5612
                    4'd0:   csr_r <= "Finitron";  // manufacturer
5613
                    4'd1:   csr_r <= "        ";
5614
                    4'd2:   csr_r <= "64 bit  ";  // CPU class
5615
                    4'd3:   csr_r <= "        ";
5616
                    4'd4:   csr_r <= "FT64    ";  // Name
5617
                    4'd5:   csr_r <= "        ";
5618
                    4'd6:   csr_r <= 64'd1;       // model #
5619
                    4'd7:   csr_r <= 64'd1;       // serial number
5620
                    4'd8:   csr_r <= {32'd16384,32'd16384};   // cache sizes instruction,csr_ra
5621
                    4'd9:   csr_r <= 64'd0;
5622
                    default:    csr_r <= 64'd0;
5623
                    endcase
5624
    default:    begin
5625
                        $display("Unsupported CSR:%h",csrno[10:0]);
5626
                        csr_r <= 64'hEEEEEEEEEEEEEEEE;
5627
                        end
5628
    endcase
5629
    else
5630
        csr_r <= 64'h0;
5631
end
5632
 
5633
reg [63:0] alu0_xu = 1'd0, alu1_xu = 1'd0;
5634
 
5635
`ifdef SUPPORT_BBMS
5636
 
5637
`else
5638
// This always block didn't work, it left the signals as X's.
5639
// So they are set to zero where the reg declaration is.
5640
// I'm guessing the @* says there's no variables on the right
5641
// hand side, so I'm not going to evaluate it.
5642
always @*
5643
        alu0_xs <= 64'd0;
5644
always @*
5645
        alu1_xs <= 64'd0;
5646
`endif
5647
 
5648 66 robfinch
wire alu_clk = clk;
5649
//BUFH uclka (.I(clk), .O(alu_clk));
5650
 
5651 60 robfinch
//always @*
5652
//    read_csr(alu0_instr[29:18],csr_r,alu0_thrd);
5653
FT64_alu #(.BIG(1'b1),.SUP_VECTOR(SUP_VECTOR)) ualu0 (
5654
  .rst(rst),
5655 66 robfinch
  .clk(alu_clk),
5656 60 robfinch
  .ld(alu0_ld),
5657
  .abort(alu0_abort),
5658
  .instr(alu0_instr),
5659
  .sz(alu0_sz),
5660
  .store(alu0_store),
5661
  .a(alu0_argA),
5662
  .b(alu0_argB),
5663
  .c(alu0_argC),
5664
  .pc(alu0_pc),
5665
//    .imm(alu0_argI),
5666
  .tgt(alu0_tgt),
5667
  .ven(alu0_ven),
5668
  .vm(vm[alu0_instr[25:23]]),
5669
  .csr(csr_r),
5670
  .o(alu0_out),
5671
  .ob(alu0b_bus),
5672
  .done(alu0_done),
5673
  .idle(alu0_idle),
5674
  .excen(aec[4:0]),
5675
  .exc(alu0_exc),
5676
  .thrd(alu0_thrd),
5677
  .mem(alu0_mem),
5678
  .shift(alu0_shft),    // 48 bit shift inst.
5679 66 robfinch
  .ol(ol)
5680 60 robfinch
`ifdef SUPPORT_BBMS
5681 66 robfinch
  , .pb(dl==2'b00 ? 64'd0 : pb),
5682 60 robfinch
  .cbl(cbl),
5683
  .cbu(cbu),
5684
  .ro(ro),
5685
  .dbl(dbl),
5686
  .dbu(dbu),
5687
  .sbl(sbl),
5688
  .sbu(sbu),
5689
  .en(en)
5690
`endif
5691
);
5692
generate begin : gAluInst
5693
if (`NUM_ALU > 1) begin
5694
FT64_alu #(.BIG(1'b0),.SUP_VECTOR(SUP_VECTOR)) ualu1 (
5695
  .rst(rst),
5696
  .clk(clk),
5697
  .ld(alu1_ld),
5698
  .abort(alu1_abort),
5699
  .instr(alu1_instr),
5700
  .sz(alu1_sz),
5701
  .store(alu1_store),
5702
  .a(alu1_argA),
5703
  .b(alu1_argB),
5704
  .c(alu1_argC),
5705
  .pc(alu1_pc),
5706
  //.imm(alu1_argI),
5707
  .tgt(alu1_tgt),
5708
  .ven(alu1_ven),
5709
  .vm(vm[alu1_instr[25:23]]),
5710
  .csr(64'd0),
5711
  .o(alu1_out),
5712
  .ob(alu1b_bus),
5713
  .done(alu1_done),
5714
  .idle(alu1_idle),
5715
  .excen(aec[4:0]),
5716
  .exc(alu1_exc),
5717
  .thrd(1'b0),
5718
  .mem(alu1_mem),
5719
  .shift(alu1_shft),
5720 66 robfinch
  .ol(2'b0)
5721 60 robfinch
`ifdef SUPPORT_BBMS
5722 66 robfinch
  , .pb(dl==2'b00 ? 64'd0 : pb),
5723 60 robfinch
  .cbl(cbl),
5724
  .cbu(cbu),
5725
  .ro(ro),
5726
  .dbl(dbl),
5727
  .dbu(dbu),
5728
  .sbl(sbl),
5729
  .sbu(sbu),
5730
  .en(en)
5731
`endif
5732
);
5733
end
5734
end
5735
endgenerate
5736
 
5737 66 robfinch
wire tlb_done;
5738
wire tlb_idle;
5739
wire [63:0] tlbo;
5740
wire uncached;
5741
`ifdef SUPPORT_TLB
5742
FT64_TLB utlb1 (
5743
        .clk(clk),
5744
        .ld(alu0_ld & alu0_tlb),
5745
        .done(tlb_done),
5746
        .idle(tlb_idle),
5747
        .ol(ol),
5748
        .ASID(ASID),
5749
        .op(alu0_instr[25:22]),
5750
        .regno(alu0_instr[21:18]),
5751
        .dati(alu0_argA),
5752
        .dato(tlbo),
5753
        .uncached(uncached),
5754
        .icl_i(icl_o),
5755
        .cyc_i(cyc),
5756
        .we_i(we),
5757
        .vadr_i(vadr),
5758
        .cyc_o(cyc_o),
5759
        .we_o(we_o),
5760
        .padr_o(adr_o),
5761
        .TLBMiss(tlb_miss),
5762
        .wrv_o(wrv_o),
5763
        .rdv_o(rdv_o),
5764
        .exv_o(exv_o),
5765
        .HTLBVirtPageo()
5766
);
5767
`else
5768
assign tlb_done = 1'b1;
5769
assign tlb_idle = 1'b1;
5770
assign tlbo = 64'hDEADDEADDEADDEAD;
5771
assign uncached = 1'b0;
5772
assign adr_o = vadr;
5773
assign cyc_o = cyc;
5774
assign we_o = we;
5775
assign tlb_miss = 1'b0;
5776
assign wrv_o = 1'b0;
5777
assign rdv_o = 1'b0;
5778
assign exv_o = 1'b0;
5779
assign exv_i = 1'b0;    // for now
5780
`endif
5781
 
5782 60 robfinch
always @*
5783
begin
5784
    alu0_cmt <= 1'b1;
5785
    alu1_cmt <= 1'b1;
5786
    fpu1_cmt <= 1'b1;
5787
    fpu2_cmt <= 1'b1;
5788
    fcu_cmt <= 1'b1;
5789
 
5790
    alu0_bus <= alu0_out;
5791
    alu1_bus <= alu1_out;
5792
    fpu1_bus <= fpu1_out;
5793
    fpu2_bus <= fpu2_out;
5794
    fcu_bus <= fcu_out;
5795
end
5796
 
5797
assign alu0_abort = 1'b0;
5798
assign alu1_abort = 1'b0;
5799
 
5800
generate begin : gFPUInst
5801
if (`NUM_FPU > 0) begin
5802
wire fpu1_clk;
5803
//BUFGCE ufpc1
5804
//(
5805
//      .I(clk_i),
5806
//      .CE(fpu1_available),
5807
//      .O(fpu1_clk)
5808
//);
5809
assign fpu1_clk = clk_i;
5810
 
5811
fpUnit ufp1
5812
(
5813
  .rst(rst),
5814
  .clk(fpu1_clk),
5815
  .clk4x(clk4x),
5816
  .ce(1'b1),
5817
  .ir(fpu1_instr),
5818
  .ld(fpu1_ld),
5819
  .a(fpu1_argA),
5820
  .b(fpu1_argB),
5821
  .imm(fpu1_argI),
5822
  .o(fpu1_out),
5823
  .csr_i(),
5824
  .status(fpu1_status),
5825
  .exception(),
5826
  .done(fpu1_done)
5827
);
5828
end
5829
if (`NUM_FPU > 1) begin
5830
wire fpu2_clk;
5831
//BUFGCE ufpc2
5832
//(
5833
//      .I(clk_i),
5834
//      .CE(fpu2_available),
5835
//      .O(fpu2_clk)
5836
//);
5837
assign fpu2_clk = clk_i;
5838
fpUnit ufp1
5839
(
5840
  .rst(rst),
5841
  .clk(fpu2_clk),
5842
  .clk4x(clk4x),
5843
  .ce(1'b1),
5844
  .ir(fpu2_instr),
5845
  .ld(fpu2_ld),
5846
  .a(fpu2_argA),
5847
  .b(fpu2_argB),
5848
  .imm(fpu2_argI),
5849
  .o(fpu2_out),
5850
  .csr_i(),
5851
  .status(fpu2_status),
5852
  .exception(),
5853
  .done(fpu2_done)
5854
);
5855
end
5856
end
5857
endgenerate
5858
 
5859
assign fpu1_exc = (fpu1_available) ?
5860
                                                                        ((|fpu1_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
5861
assign fpu2_exc = (fpu2_available) ?
5862
                                                                        ((|fpu2_status[15:0]) ? `FLT_FLT : `FLT_NONE) : `FLT_UNIMP;
5863
 
5864
assign  alu0_v = alu0_dataready,
5865
        alu1_v = alu1_dataready;
5866
assign  alu0_id = alu0_sourceid,
5867
            alu1_id = alu1_sourceid;
5868
assign  fpu1_v = fpu1_dataready;
5869
assign  fpu1_id = fpu1_sourceid;
5870
assign  fpu2_v = fpu2_dataready;
5871
assign  fpu2_id = fpu2_sourceid;
5872
 
5873
`ifdef SUPPORT_SMT
5874
wire [1:0] olm = ol[fcu_thrd];
5875
`else
5876
wire [1:0] olm = ol;
5877
`endif
5878
 
5879
reg [`SNBITS] maxsn [0:`WAYS-1];
5880
always @*
5881
begin
5882
        for (j = 0; j < `WAYS; j = j + 1) begin
5883
                maxsn[j] = 8'd0;
5884
                for (n = 0; n < QENTRIES; n = n + 1)
5885
                        if (iqentry_sn[n] > maxsn[j] && iqentry_thrd[n]==j && iqentry_v[n])
5886
                                maxsn[j] = iqentry_sn[n];
5887
                maxsn[j] = maxsn[j] - tosub;
5888
        end
5889
end
5890
 
5891
assign  fcu_v = fcu_dataready;
5892
assign  fcu_id = fcu_sourceid;
5893
 
5894
wire [4:0] fcmpo;
5895
wire fnanx;
5896
fp_cmp_unit #(64) ufcmp1 (fcu_argA, fcu_argB, fcmpo, fnanx);
5897
 
5898
wire fcu_takb;
5899
 
5900
always @*
5901
begin
5902
    fcu_exc <= `FLT_NONE;
5903
    casez(fcu_instr[`INSTRUCTION_OP])
5904
`ifdef SUPPORT_BBMS
5905
    `LFCS:      fcu_exc <= currentCSSelector != fcu_instr[31:8] ? `FLT_CS : `FLT_NONE;
5906
    `RET:               fcu_exc <= fcu_argB[63:40] != currentCSSelector ? `FLT_RET : `FLT_NONE;
5907
`endif
5908
    `CHK:   begin
5909
                if (fcu_instr[21])
5910
                    fcu_exc <= fcu_argA >= fcu_argB && fcu_argA < fcu_argC ? `FLT_NONE : `FLT_CHK;
5911
            end
5912
    `REX:
5913
        case(olm)
5914
        `OL_USER:   fcu_exc <= `FLT_PRIV;
5915
        default:    ;
5916
        endcase
5917 61 robfinch
// Could have long branches exceptioning and unimplmented in the fetch stage.
5918
//   `BBc:      fcu_exc <= fcu_instr[6] ? `FLT_BRN : `FLT_NONE;
5919 60 robfinch
   default: fcu_exc <= `FLT_NONE;
5920
        endcase
5921
end
5922
 
5923
FT64_EvalBranch ube1
5924
(
5925
        .instr(fcu_instr),
5926
        .a(fcu_argA),
5927
        .b(fcu_argB),
5928
        .c(fcu_argC),
5929
        .takb(fcu_takb)
5930
);
5931
 
5932
FT64_FCU_Calc #(.AMSB(AMSB)) ufcuc1
5933
(
5934
        .ol(olm),
5935
        .instr(fcu_instr),
5936
        .tvec(tvec[fcu_instr[14:13]]),
5937
        .a(fcu_argA),
5938
        .pc(fcu_pc),
5939
        .nextpc(fcu_nextpc),
5940
        .im(im),
5941
        .waitctr(waitctr),
5942
        .bus(fcu_out)
5943
);
5944
 
5945
wire will_clear_branchmiss = branchmiss && ((fetchbuf0_v && fetchbuf0_pc==misspc) || (fetchbuf1_v && fetchbuf1_pc==misspc));
5946
 
5947
always @*
5948
begin
5949
case(fcu_instr[`INSTRUCTION_OP])
5950 61 robfinch
`R2:    fcu_misspc = fcu_epc;           // RTI (we don't bother fully decoding this as it's the only R2)
5951 60 robfinch
`RET:   fcu_misspc = fcu_argB;
5952
`REX:   fcu_misspc = fcu_bus;
5953
`BRK:   fcu_misspc = {tvec[0][AMSB:8], 1'b0, olm, 5'h0};
5954
`JAL:   fcu_misspc = fcu_argA + fcu_argI;
5955
//`CHK: fcu_misspc = fcu_nextpc + fcu_argI;     // Handled as an instruction exception
5956
// Default: branch
5957 61 robfinch
default:        fcu_misspc = fcu_pt ? fcu_nextpc : {fcu_pc[AMSB:32],fcu_pc[31:0] + fcu_brdisp[31:0]};
5958 60 robfinch
endcase
5959
fcu_misspc[0] = 1'b0;
5960
end
5961
 
5962
// To avoid false branch mispredicts the branch isn't evaluated until the
5963
// following instruction queues. The address of the next instruction is
5964
// looked at to see if the BTB predicted correctly.
5965
 
5966
wire fcu_brk_miss = fcu_brk || fcu_rti;
5967
`ifdef FCU_ENH
5968
wire fcu_ret_miss = fcu_ret && (fcu_argB != iqentry_pc[nid]);
5969
wire fcu_jal_miss = fcu_jal && (fcu_argA + fcu_argI != iqentry_pc[nid]);
5970
wire fcu_followed = iqentry_sn[nid] > iqentry_sn[fcu_id[`QBITS]];
5971
`else
5972
wire fcu_ret_miss = fcu_ret;
5973
wire fcu_jal_miss = fcu_jal;
5974
wire fcu_followed = `TRUE;
5975
`endif
5976
always @*
5977
if (fcu_v) begin
5978
        // Break and RTI switch register sets, and so are always treated as a branch miss in order to
5979
        // flush the pipeline. Hardware interrupts also stream break instructions so they need to 
5980
        // flushed from the queue so the interrupt is recognized only once.
5981
        // BRK and RTI are handled as excmiss types which are processed during the commit stage.
5982
        if (fcu_brk_miss)
5983
                fcu_branchmiss = TRUE;
5984
        else if (fcu_branch && (fcu_takb ^ fcu_pt))
5985
    fcu_branchmiss = TRUE;
5986
        else
5987
`ifdef SUPPORT_SMT
5988
                if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol[fcu_thrd]))
5989
`else
5990
                if (fcu_instr[`INSTRUCTION_OP] == `REX && (im < ~ol))
5991
`endif
5992
                fcu_branchmiss = TRUE;
5993
        else if (fcu_ret_miss)
5994
                fcu_branchmiss = TRUE;
5995
        else if (fcu_jal_miss)
5996
    fcu_branchmiss = TRUE;
5997
        else if (fcu_instr[`INSTRUCTION_OP] == `CHK && ~fcu_takb)
5998
    fcu_branchmiss = TRUE;
5999
        else
6000
    fcu_branchmiss = FALSE;
6001
end
6002
else
6003
        fcu_branchmiss = FALSE;
6004
 
6005
FT64_RMW_alu urmwalu0 (rmw_instr, rmw_argA, rmw_argB, rmw_argC, rmw_res);
6006
 
6007
 
6008
//
6009
// additional DRAM-enqueue logic
6010
 
6011
assign dram_avail = (dram0 == `DRAMSLOT_AVAIL || dram1 == `DRAMSLOT_AVAIL || dram2 == `DRAMSLOT_AVAIL);
6012
 
6013
always @*
6014
for (n = 0; n < QENTRIES; n = n + 1)
6015
        iqentry_memopsvalid[n] <= (iqentry_mem[n] && (iqentry_store[n] ? iqentry_a2_v[n] : 1'b1) && iqentry_state[n]==IQS_AGEN);
6016
 
6017
always @*
6018
for (n = 0; n < QENTRIES; n = n + 1)
6019
        iqentry_memready[n] <= (iqentry_v[n] & iqentry_iv[n] & iqentry_memopsvalid[n] & ~iqentry_memissue[n] & ~iqentry_stomp[n]);
6020
 
6021
assign outstanding_stores = (dram0 && dram0_store) ||
6022
                            (dram1 && dram1_store) ||
6023
                            (dram2 && dram2_store);
6024
 
6025
//
6026
// additional COMMIT logic
6027
//
6028
always @*
6029
begin
6030
    commit0_v <= (iqentry_state[heads[0]] == IQS_CMT && ~|panic);
6031
    commit0_id <= {iqentry_mem[heads[0]], heads[0]};      // if a memory op, it has a DRAM-bus id
6032
    commit0_tgt <= iqentry_tgt[heads[0]];
6033
    commit0_we  <= iqentry_we[heads[0]];
6034
    commit0_bus <= iqentry_res[heads[0]];
6035
    if (`NUM_CMT > 1) begin
6036
            commit1_v <= ({iqentry_v[heads[0]],  iqentry_state[heads[0]] == IQS_CMT} != 2'b10
6037
                       && iqentry_state[heads[1]] == IQS_CMT
6038
                       && ~|panic);
6039
            commit1_id <= {iqentry_mem[heads[1]], heads[1]};
6040
            commit1_tgt <= iqentry_tgt[heads[1]];
6041
            commit1_we  <= iqentry_we[heads[1]];
6042
            commit1_bus <= iqentry_res[heads[1]];
6043
            // Need to set commit1, and commit2 valid bits for the branch predictor.
6044
            if (`NUM_CMT > 2) begin
6045
                end
6046
                else begin
6047
                        commit2_v <= ({iqentry_v[heads[0]], iqentry_state[heads[0]] == IQS_CMT} != 2'b10
6048
                                                                 && {iqentry_v[heads[1]], iqentry_state[heads[1]] == IQS_CMT} != 2'b10
6049
                                                                 && {iqentry_v[heads[2]], iqentry_br[heads[2]], iqentry_state[heads[2]] == IQS_CMT}==3'b111
6050
                               && iqentry_tgt[heads[2]][4:0]==5'd0 && ~|panic);  // watch out for dbnz and ibne
6051
                        commit2_tgt <= 12'h000;
6052
                        commit2_we <= 8'h00;
6053
                end
6054
        end
6055
        else begin
6056
                commit1_v <= ({iqentry_v[heads[0]], iqentry_state[heads[0]] == IQS_CMT} != 2'b10
6057
                                                         && {iqentry_v[heads[1]], iqentry_state[heads[1]] == IQS_CMT} == 2'b11
6058
                       && !iqentry_rfw[heads[1]] && ~|panic);   // watch out for dbnz and ibne
6059
        commit1_id <= {iqentry_mem[heads[1]], heads[1]};        // if a memory op, it has a DRAM-bus id
6060
                commit1_tgt <= 12'h000;
6061
                commit1_we <= 8'h00;
6062
                // We don't really need the bus value since nothing is being written.
6063
            commit1_bus <= iqentry_res[heads[1]];
6064
                commit2_v <= ({iqentry_v[heads[0]], iqentry_state[heads[0]] == IQS_CMT} != 2'b10
6065
                                                         && {iqentry_v[heads[1]], iqentry_state[heads[1]] == IQS_CMT} != 2'b10
6066
                                                         && {iqentry_v[heads[2]], iqentry_br[heads[2]], iqentry_state[heads[2]] == IQS_CMT}==3'b111
6067
                       && !iqentry_rfw[heads[2]] && ~|panic);   // watch out for dbnz and ibne
6068
        commit2_id <= {iqentry_mem[heads[2]], heads[2]};        // if a memory op, it has a DRAM-bus id
6069
                commit2_tgt <= 12'h000;
6070
                commit2_we <= 8'h00;
6071
            commit2_bus <= iqentry_res[heads[2]];
6072
        end
6073
end
6074
 
6075
assign int_commit = (commit0_v && iqentry_irq[heads[0]])
6076
                                                                         || (commit0_v && commit1_v && iqentry_irq[heads[1]] && `NUM_CMT > 1)
6077
                                                                         || (commit0_v && commit1_v && commit2_v && iqentry_irq[heads[2]] && `NUM_CMT > 2);
6078
 
6079
// Detect if a given register will become valid during the current cycle.
6080
// We want a signal that is active during the current clock cycle for the read
6081
// through register file, which trims a cycle off register access for every
6082
// instruction. But two different kinds of assignment statements can't be
6083
// placed under the same always block, it's a bad practice and may not work.
6084
// So a signal is created here with it's own always block.
6085
reg [AREGS-1:0] regIsValid;
6086
always @*
6087
begin
6088
        for (n = 1; n < AREGS; n = n + 1)
6089
        begin
6090
                regIsValid[n] = rf_v[n];
6091
                if (branchmiss)
6092
               if (~livetarget[n]) begin
6093
                        if (branchmiss_thrd) begin
6094
                                if (n >= 128)
6095
                                        regIsValid[n] = `VAL;
6096
                        end
6097
                        else begin
6098
                                if (n < 128)
6099
                                        regIsValid[n] = `VAL;
6100
                        end
6101
               end
6102
                if (commit0_v && n=={commit0_tgt[7:0]})
6103
                        regIsValid[n] = regIsValid[n] | ((rf_source[ {commit0_tgt[7:0]} ] == commit0_id)
6104
                        || (branchmiss && branchmiss_thrd == iqentry_thrd[commit0_id[`QBITS]] && iqentry_source[ commit0_id[`QBITS] ]));
6105
                if (commit1_v && n=={commit1_tgt[7:0]} && `NUM_CMT > 1)
6106
                        regIsValid[n] = regIsValid[n] | ((rf_source[ {commit1_tgt[7:0]} ] == commit1_id)
6107
                        || (branchmiss && branchmiss_thrd == iqentry_thrd[commit1_id[`QBITS]] && iqentry_source[ commit1_id[`QBITS] ]));
6108
                if (commit2_v && n=={commit2_tgt[7:0]} && `NUM_CMT > 2)
6109
                        regIsValid[n] = regIsValid[n] | ((rf_source[ {commit2_tgt[7:0]} ] == commit2_id)
6110
                        || (branchmiss && branchmiss_thrd == iqentry_thrd[commit2_id[`QBITS]] && iqentry_source[ commit2_id[`QBITS] ]));
6111
        end
6112
        regIsValid[0] = `VAL;
6113
        regIsValid[32] = `VAL;
6114
        regIsValid[64] = `VAL;
6115
        regIsValid[96] = `VAL;
6116
`ifdef SMT
6117
        regIsValid[128] = `VAL;
6118
        regIsValid[160] = `VAL;
6119
        regIsValid[192] = `VAL;
6120
        regIsValid[224] = `VAL;
6121
`endif
6122
end
6123
 
6124
// Wait until the cycle after Ra becomes valid to give time to read
6125
// the vector element from the register file.
6126
reg rf_vra0, rf_vra1;
6127
/*always @(posedge clk)
6128
    rf_vra0 <= regIsValid[Ra0s];
6129
always @(posedge clk)
6130
    rf_vra1 <= regIsValid[Ra1s];
6131
*/
6132
// Check how many instructions can be queued. This might be fewer than the
6133
// number ready to queue from the fetch stage if queue slots aren't
6134
// available or if there are no more physical registers left for remapping.
6135
// The fetch stage needs to know how many instructions will queue so this
6136
// logic is placed here.
6137
// NOPs are filtered out and do not enter the instruction queue. The core
6138
// will stream NOPs on a cache miss and they would mess up the queue order
6139
// if there are immediate prefixes in the queue.
6140
// For the VEX instruction, the instruction can't queue until register Ra
6141
// is valid, because register Ra is used to specify the vector element to
6142
// read.
6143
wire q2open = iqentry_v[tail0]==`INV && iqentry_v[tail1]==`INV;
6144
wire q3open = iqentry_v[tail0]==`INV && iqentry_v[tail1]==`INV && iqentry_v[(tail1 + 2'd1) % QENTRIES]==`INV;
6145
always @*
6146
begin
6147
        canq1 <= FALSE;
6148
        canq2 <= FALSE;
6149
        queued1 <= FALSE;
6150
        queued2 <= FALSE;
6151
        queuedNop <= FALSE;
6152
        vqueued2 <= FALSE;
6153
        if (!branchmiss) begin
6154
      // Two available
6155
      if (fetchbuf1_v & fetchbuf0_v) begin
6156
          // Is there a pair of NOPs ? (cache miss)
6157
          if ((fetchbuf0_instr[`INSTRUCTION_OP]==`NOP) && (fetchbuf1_instr[`INSTRUCTION_OP]==`NOP))
6158
              queuedNop <= TRUE;
6159
          else begin
6160
              // If it's a predicted branch queue only the first instruction, the second
6161
              // instruction will be stomped on.
6162
              if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
6163
                  if (iqentry_v[tail0]==`INV) begin
6164
                      canq1 <= TRUE;
6165
                      queued1 <= TRUE;
6166
                  end
6167
              end
6168
              // This is where a single NOP is allowed through to simplify the code. A
6169
              // single NOP can't be a cache miss. Otherwise it would be necessary to queue
6170
              // fetchbuf1 on tail0 it would add a nightmare to the enqueue code.
6171
              // Not a branch and there are two instructions fetched, see whether or not
6172
              // both instructions can be queued.
6173
              else begin
6174
                  if (iqentry_v[tail0]==`INV) begin
6175
                      canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
6176
                      queued1 <= (
6177
                        ((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
6178
                      if (iqentry_v[tail1]==`INV) begin
6179
                          canq2 <= ((!IsVex(fetchbuf1_instr) || rf_vra1)) || !SUP_VECTOR;
6180
                          queued2 <= (
6181
                                (!IsVector(fetchbuf1_instr) && (!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
6182
                          vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
6183
                      end
6184
                  end
6185
                  // If an irq is active during a vector instruction fetch, claim the vector instruction
6186
                  // is finished queueing even though it may not be. It'll pick up where it left off after
6187
                  // the exception is processed.
6188
                  if (freezePC) begin
6189
                        if (IsVector(fetchbuf0_instr) && IsVector(fetchbuf1_instr) && vechain) begin
6190
                                queued1 <= TRUE;
6191
                                queued2 <= TRUE;
6192
                        end
6193
                        else if (IsVector(fetchbuf0_instr)) begin
6194
                                queued1 <= TRUE;
6195
                                if (vqe0 < vl-2)
6196
                                        queued2 <= TRUE;
6197
                                else
6198
                                        queued2 <= iqentry_v[tail1]==`INV;
6199
                        end
6200
                  end
6201
              end
6202
          end
6203
      end
6204
      // One available
6205
      else if (fetchbuf0_v) begin
6206
          if (fetchbuf0_instr[`INSTRUCTION_OP]!=`NOP) begin
6207
              if (iqentry_v[tail0]==`INV) begin
6208
                  canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
6209
                  queued1 <=
6210
                        (((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
6211
              end
6212
              if (iqentry_v[tail1]==`INV) begin
6213
                canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
6214
                  vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
6215
                end
6216
                if (freezePC) begin
6217
                if (IsVector(fetchbuf0_instr)) begin
6218
                        queued1 <= TRUE;
6219
                        if (vqe0 < vl-2)
6220
                                queued2 <= iqentry_v[tail1]==`INV;
6221
                end
6222
                end
6223
          end
6224
          else
6225
              queuedNop <= TRUE;
6226
      end
6227
      else if (fetchbuf1_v) begin
6228
          if (fetchbuf1_instr[`INSTRUCTION_OP]!=`NOP) begin
6229
              if (iqentry_v[tail0]==`INV) begin
6230
                  canq1 <= !IsVex(fetchbuf1_instr) || rf_vra1 || !SUP_VECTOR;
6231
                  queued1 <= (
6232
                        ((!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf1_instr))) || !SUP_VECTOR);
6233
              end
6234
              if (iqentry_v[tail1]==`INV) begin
6235
                canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
6236
                  vqueued2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2;
6237
                end
6238
                if (freezePC) begin
6239
                if (IsVector(fetchbuf1_instr)) begin
6240
                        queued1 <= TRUE;
6241
                        if (vqe1 < vl-2)
6242
                                queued2 <= iqentry_v[tail1]==`INV;
6243
                end
6244
                end
6245
          end
6246
          else
6247
              queuedNop <= TRUE;
6248
      end
6249
      //else no instructions available to queue
6250
  end
6251
  else begin
6252
    // One available
6253
    if (fetchbuf0_v && fetchbuf0_thrd != branchmiss_thrd) begin
6254
        if (fetchbuf0_instr[`INSTRUCTION_OP]!=`NOP) begin
6255
            if (iqentry_v[tail0]==`INV) begin
6256
                canq1 <= !IsVex(fetchbuf0_instr) || rf_vra0 || !SUP_VECTOR;
6257
                queued1 <= (
6258
                        ((!IsVex(fetchbuf0_instr) || rf_vra0) && (!IsVector(fetchbuf0_instr))) || !SUP_VECTOR);
6259
            end
6260
            if (iqentry_v[tail1]==`INV) begin
6261
                canq2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && SUP_VECTOR;
6262
                vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
6263
                end
6264
        end
6265
        else
6266 61 robfinch
          queuedNop <= TRUE;
6267 60 robfinch
    end
6268
    else if (fetchbuf1_v && fetchbuf1_thrd != branchmiss_thrd) begin
6269
        if (fetchbuf1_instr[`INSTRUCTION_OP]!=`NOP) begin
6270
            if (iqentry_v[tail0]==`INV) begin
6271
                canq1 <= !IsVex(fetchbuf1_instr) || rf_vra1 || !SUP_VECTOR;
6272
                queued1 <= (
6273
                        ((!IsVex(fetchbuf1_instr) || rf_vra1) && (!IsVector(fetchbuf1_instr))) || !SUP_VECTOR);
6274
            end
6275
            if (iqentry_v[tail1]==`INV) begin
6276
                canq2 <= IsVector(fetchbuf1_instr) && vqe1 < vl-2 && SUP_VECTOR;
6277
                vqueued2 <= IsVector(fetchbuf0_instr) && vqe0 < vl-2 && !vechain;
6278
                end
6279
        end
6280
        else
6281
            queuedNop <= TRUE;
6282
    end
6283
//      else
6284
//              queuedNop <= TRUE;
6285
  end
6286
end
6287
 
6288
//
6289
// Branchmiss seems to be sticky sometimes during simulation. For instance branch miss
6290
// and cache miss at same time. The branchmiss should clear before the core continues
6291
// so the positive edge is detected to avoid incrementing the sequnce number too many
6292
// times.
6293
wire pebm;
6294
edge_det uedbm (.rst(rst), .clk(clk), .ce(1'b1), .i(branchmiss), .pe(pebm), .ne(), .ee() );
6295
 
6296
reg [5:0] ld_time;
6297
reg [63:0] wc_time_dat;
6298
reg [63:0] wc_times;
6299
always @(posedge tm_clk_i)
6300
begin
6301
        if (|ld_time)
6302
                wc_time <= wc_time_dat;
6303
        else begin
6304
                wc_time[31:0] <= wc_time[31:0] + 32'd1;
6305
                if (wc_time[31:0] >= TM_CLKFREQ-1) begin
6306
                        wc_time[31:0] <= 32'd0;
6307
                        wc_time[63:32] <= wc_time[63:32] + 32'd1;
6308
                end
6309
        end
6310
end
6311
 
6312
wire writing_wb =
6313 61 robfinch
                        (mem1_available && dram0==`DRAMSLOT_BUSY && dram0_store && wbptr<`WB_DEPTH-1)
6314
         || (mem2_available && dram1==`DRAMSLOT_BUSY && dram1_store && `NUM_MEM > 1 && wbptr<`WB_DEPTH-1)
6315
         || (mem3_available && dram2==`DRAMSLOT_BUSY && dram2_store && `NUM_MEM > 2 && wbptr<`WB_DEPTH-1)
6316 60 robfinch
         ;
6317
 
6318
// Monster clock domain.
6319
// Like to move some of this to clocking under different always blocks in order
6320
// to help out the toolset's synthesis, but it ain't gonna be easy.
6321
// Simulation doesn't like it if things are under separate always blocks.
6322
// Synthesis doesn't like it if things are under the same always block.
6323
 
6324
//always @(posedge clk)
6325
//begin
6326
//      branchmiss <= excmiss|fcu_branchmiss;
6327
//    misspc <= excmiss ? excmisspc : fcu_misspc;
6328
//    missid <= excmiss ? (|iqentry_exc[heads[0]] ? heads[0] : heads[1]) : fcu_sourceid;
6329
//      branchmiss_thrd <=  excmiss ? excthrd : fcu_thrd;
6330
//end
6331
wire alu0_done_pe, alu1_done_pe, pe_wait;
6332 66 robfinch
edge_det uedalu0d (.clk(clk), .ce(1'b1), .i(alu0_done&tlb_done), .pe(alu0_done_pe), .ne(), .ee());
6333 60 robfinch
edge_det uedalu1d (.clk(clk), .ce(1'b1), .i(alu1_done), .pe(alu1_done_pe), .ne(), .ee());
6334
edge_det uedwait1 (.clk(clk), .ce(1'b1), .i((waitctr==48'd1) || signal_i[fcu_argA[4:0]|fcu_argI[4:0]]), .pe(pe_wait), .ne(), .ee());
6335
 
6336
// Bus randomization to mitigate meltdown attacks
6337 66 robfinch
wire [63:0] ralu0_bus = |alu0_exc ? {4{lfsro}} : alu0_tlb ? tlbo : alu0_bus;
6338 60 robfinch
wire [63:0] ralu1_bus = |alu1_exc ? {4{lfsro}} : alu1_bus;
6339
wire [63:0] rfpu1_bus = |fpu1_exc ? {4{lfsro}} : fpu1_bus;
6340
wire [63:0] rfpu2_bus = |fpu2_exc ? {4{lfsro}} : fpu2_bus;
6341 61 robfinch
wire [63:0] rfcu_bus  = |fcu_exc  ? {4{lfsro}} : fcu_bus;
6342
wire [63:0] rdramA_bus = dramA_bus;
6343
wire [63:0] rdramB_bus = dramB_bus;
6344
wire [63:0] rdramC_bus = dramC_bus;
6345 60 robfinch
 
6346 66 robfinch
// Hold reset for five seconds
6347
reg [31:0] rst_ctr;
6348 60 robfinch
always @(posedge clk)
6349 66 robfinch
if (rst)
6350
        rst_ctr <= 32'd0;
6351
else begin
6352
        if (rst_ctr < 32'd10)
6353
                rst_ctr <= rst_ctr + 24'd1;
6354
end
6355
 
6356
always @(posedge clk)
6357
if (rst|(rst_ctr < 32'd10)) begin
6358 60 robfinch
`ifdef SUPPORT_SMT
6359 66 robfinch
        mstatus[0] <= 64'h4000F; // select register set #16 for thread 0
6360
        mstatus[1] <= 64'h4800F;        // select register set #18 for thread 1
6361
        rs_stack[0] <= 64'd16;
6362
        brs_stack[0] <= 64'd16;
6363
        rs_stack[1] <= 64'd18;
6364
        brs_stack[1] <= 64'd18;
6365 60 robfinch
`else
6366 66 robfinch
        im_stack <= 32'hFFFFFFFF;
6367
        mstatus <= 64'h4000F;   // select register set #16 for thread 0
6368
        rs_stack <= 64'd16;
6369
        brs_stack <= 64'd16;
6370 60 robfinch
`endif
6371
    for (n = 0; n < QENTRIES; n = n + 1) begin
6372
        iqentry_state[n] <= IQS_INVALID;
6373
       iqentry_iv[n] <= `INV;
6374
       iqentry_is[n] <= 3'b00;
6375
       iqentry_sn[n] <= 4'd0;
6376
       iqentry_pt[n] <= FALSE;
6377
       iqentry_bt[n] <= FALSE;
6378
       iqentry_br[n] <= FALSE;
6379
       iqentry_aq[n] <= FALSE;
6380
       iqentry_rl[n] <= FALSE;
6381
       iqentry_alu0[n] <= FALSE;
6382
       iqentry_alu[n] <= FALSE;
6383
       iqentry_fpu[n] <= FALSE;
6384
       iqentry_fsync[n] <= FALSE;
6385
       iqentry_fc[n] <= FALSE;
6386
       iqentry_takb[n] <= FALSE;
6387
       iqentry_jmp[n] <= FALSE;
6388
       iqentry_jal[n] <= FALSE;
6389
       iqentry_ret[n] <= FALSE;
6390
       iqentry_brk[n] <= FALSE;
6391
       iqentry_irq[n] <= FALSE;
6392
       iqentry_rti[n] <= FALSE;
6393
       iqentry_ldcmp[n] <= FALSE;
6394
       iqentry_load[n] <= FALSE;
6395
       iqentry_rtop[n] <= FALSE;
6396
       iqentry_sei[n] <= FALSE;
6397
       iqentry_shft[n] <= FALSE;
6398
       iqentry_sync[n] <= FALSE;
6399
       iqentry_ven[n] <= 6'd0;
6400
       iqentry_vl[n] <= 8'd0;
6401
       iqentry_we[n] <= 8'h00;
6402
       iqentry_rfw[n] <= FALSE;
6403
       iqentry_rmw[n] <= FALSE;
6404
       iqentry_pc[n] <= RSTPC;
6405
         iqentry_instr[n] <= `NOP_INSN;
6406
         iqentry_insln[n] <= 3'd4;
6407
         iqentry_preload[n] <= FALSE;
6408
         iqentry_mem[n] <= FALSE;
6409
         iqentry_memndx[n] <= FALSE;
6410
       iqentry_memissue[n] <= FALSE;
6411
       iqentry_mem_islot[n] <= 3'd0;
6412
       iqentry_memdb[n] <= FALSE;
6413
       iqentry_memsb[n] <= FALSE;
6414
       iqentry_tgt[n] <= 6'd0;
6415
       iqentry_imm[n] <= 1'b0;
6416
       iqentry_ma[n] <= 1'b0;
6417
       iqentry_a0[n] <= 64'd0;
6418
       iqentry_a1[n] <= 64'd0;
6419
       iqentry_a2[n] <= 64'd0;
6420
       iqentry_a3[n] <= 64'd0;
6421
       iqentry_a1_v[n] <= `INV;
6422
       iqentry_a2_v[n] <= `INV;
6423
       iqentry_a3_v[n] <= `INV;
6424
       iqentry_a1_s[n] <= 5'd0;
6425
       iqentry_a2_s[n] <= 5'd0;
6426
       iqentry_a3_s[n] <= 5'd0;
6427
       iqentry_canex[n] <= FALSE;
6428
    end
6429
     bwhich <= 2'b00;
6430
     dram0 <= `DRAMSLOT_AVAIL;
6431
     dram1 <= `DRAMSLOT_AVAIL;
6432
     dram2 <= `DRAMSLOT_AVAIL;
6433
     dram0_instr <= `NOP_INSN;
6434
     dram1_instr <= `NOP_INSN;
6435
     dram2_instr <= `NOP_INSN;
6436
     dram0_addr <= 32'h0;
6437
     dram1_addr <= 32'h0;
6438
     dram2_addr <= 32'h0;
6439
     dram0_id <= 1'b0;
6440
     dram1_id <= 1'b0;
6441
     dram2_id <= 1'b0;
6442 66 robfinch
     dram0_store <= 1'b0;
6443
     dram1_store <= 1'b0;
6444
     dram2_store <= 1'b0;
6445 60 robfinch
     invic <= FALSE;
6446 66 robfinch
     invicl <= FALSE;
6447 60 robfinch
     tail0 <= 3'd0;
6448
     tail1 <= 3'd1;
6449
     for (n = 0; n < QENTRIES; n = n + 1)
6450
        heads[n] <= n;
6451
     panic = `PANIC_NONE;
6452
     alu0_dataready <= 1'b0;
6453
     alu1_dataready <= 1'b0;
6454
     alu0_sourceid <= 5'd0;
6455
     alu1_sourceid <= 5'd0;
6456
`define SIM_
6457
`ifdef SIM_
6458
                alu0_pc <= RSTPC;
6459
                alu0_instr <= `NOP_INSN;
6460
                alu0_argA <= 64'h0;
6461
                alu0_argB <= 64'h0;
6462
                alu0_argC <= 64'h0;
6463
                alu0_argI <= 64'h0;
6464
                alu0_mem <= 1'b0;
6465
                alu0_shft <= 1'b0;
6466
                alu0_thrd <= 1'b0;
6467
                alu0_tgt <= 6'h00;
6468
                alu0_ven <= 6'd0;
6469
                alu1_pc <= RSTPC;
6470
                alu1_instr <= `NOP_INSN;
6471
                alu1_argA <= 64'h0;
6472
                alu1_argB <= 64'h0;
6473
                alu1_argC <= 64'h0;
6474
                alu1_argI <= 64'h0;
6475
                alu1_mem <= 1'b0;
6476
                alu1_shft <= 1'b0;
6477
                alu1_thrd <= 1'b0;
6478
                alu1_tgt <= 6'h00;
6479
                alu1_ven <= 6'd0;
6480
`endif
6481
     fcu_dataready <= 0;
6482
     fcu_instr <= `NOP_INSN;
6483 61 robfinch
     fcu_call <= 1'b0;
6484 60 robfinch
     dramA_v <= 0;
6485
     dramB_v <= 0;
6486
     dramC_v <= 0;
6487
     I <= 0;
6488
     CC <= 0;
6489
     bstate <= BIDLE;
6490
     tick <= 64'd0;
6491
     ol_o <= 2'b0;
6492
     bte_o <= 2'b00;
6493
     cti_o <= 3'b000;
6494
     cyc <= `LOW;
6495
     stb_o <= `LOW;
6496
     we <= `LOW;
6497
     sel_o <= 8'h00;
6498
     dat_o <= 64'hFFFFFFFFFFFFFFFF;
6499
     sr_o <= `LOW;
6500
     cr_o <= `LOW;
6501
     vadr <= RSTPC;
6502
     cr0 <= 64'd0;
6503
     cr0[13:8] <= 6'd0;         // select compressed instruction group #0
6504
     cr0[30] <= TRUE;           // enable data caching
6505
     cr0[32] <= TRUE;           // enable branch predictor
6506
     cr0[16] <= 1'b0;           // disable SMT
6507
     cr0[17] <= 1'b0;           // sequence number reset = 1
6508
     cr0[34] <= FALSE;  // write buffer merging enable
6509
     cr0[35] <= TRUE;           // load speculation enable
6510
     pcr <= 32'd0;
6511
     pcr2 <= 64'd0;
6512
    for (n = 0; n < PREGS; n = n + 1) begin
6513
      rf_v[n] <= `VAL;
6514
      rf_source[n] <= {`QBIT{1'b1}};
6515
    end
6516
     fp_rm <= 3'd0;                     // round nearest even - default rounding mode
6517
     fpu_csr[37:32] <= 5'd31;   // register set #31
6518
     waitctr <= 48'd0;
6519
    for (n = 0; n < 16; n = n + 1) begin
6520
      badaddr[n] <= 64'd0;
6521
      bad_instr[n] <= `NOP_INSN;
6522
    end
6523
    // Vector
6524
     vqe0 <= 6'd0;
6525
     vqet0 <= 6'd0;
6526
     vqe1 <= 6'd0;
6527
     vqet1 <= 6'd0;
6528
     vl <= 7'd62;
6529
    for (n = 0; n < 8; n = n + 1)
6530
         vm[n] <= 64'h7FFFFFFFFFFFFFFF;
6531
     nop_fetchbuf <= 4'h0;
6532
     fcu_done <= `TRUE;
6533
     sema <= 64'h0;
6534
     tvec[0] <= RSTPC;
6535
     pmr <= 64'hFFFFFFFFFFFFFFFF;
6536
     pmr[0] <= `ID1_AVAIL;
6537
     pmr[1] <= `ID2_AVAIL;
6538
     pmr[2] <= `ID3_AVAIL;
6539
     pmr[8] <= `ALU0_AVAIL;
6540
     pmr[9] <= `ALU1_AVAIL;
6541
     pmr[16] <= `FPU1_AVAIL;
6542
     pmr[17] <= `FPU2_AVAIL;
6543
     pmr[24] <= `MEM1_AVAIL;
6544
     pmr[25] <= `MEM2_AVAIL;
6545
                 pmr[26] <= `MEM3_AVAIL;
6546
     pmr[32] <= `FCU_AVAIL;
6547
     for (n = 0; n < `WB_DEPTH; n = n + 1) begin
6548
        wb_v[n] <= 1'b0;
6549
        wb_rmw[n] <= 1'b0;
6550
        wb_id[n] <= {QENTRIES{1'b0}};
6551
        wb_ol[n] <= 2'b00;
6552
        wb_sel[n] <= 8'h00;
6553 66 robfinch
        wb_addr[n] <= 64'd0;
6554 60 robfinch
        wb_data[n] <= 64'd0;
6555
     end
6556
     wb_en <= `TRUE;
6557
     wbo_id <= {QENTRIES{1'b0}};
6558
     wbptr <= 2'd0;
6559
`ifdef SIM
6560
                wb_merges <= 32'd0;
6561
`endif
6562
                iq_ctr <= 40'd0;
6563
                icl_ctr <= 40'd0;
6564
                bm_ctr <= 40'd0;
6565 61 robfinch
                br_ctr <= 40'd0;
6566 60 robfinch
                irq_ctr <= 40'd0;
6567
                cmt_timer <= 9'd0;
6568
                StoreAck1 <= `FALSE;
6569
                keys <= 64'h0;
6570
`ifdef SUPPORT_DBG
6571
                dbg_ctrl <= 64'h0;
6572
`endif
6573
/* Initialized with initial begin above
6574
`ifdef SUPPORT_BBMS
6575
                for (n = 0; n < 64; n = n + 1) begin
6576
                        thrd_handle[n] <= 16'h0;
6577
                        prg_base[n] <= 64'h0;
6578
                        cl_barrier[n] <= 64'h0;
6579
                        cu_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
6580
                        ro_barrier[n] <= 64'h0;
6581
                        dl_barrier[n] <= 64'h0;
6582
                        du_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
6583
                        sl_barrier[n] <= 64'h0;
6584
                        su_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;
6585
                end
6586
`endif
6587
*/
6588
end
6589
else begin
6590
        if (|fb_panic)
6591
                panic <= fb_panic;
6592
 
6593
        // Only one branchmiss is allowed to be processed at a time. If a second 
6594
        // branchmiss occurs while the first is being processed, it would have
6595
        // to of occurred as a speculation in the branch shadow of the first.
6596
        // The second instruction would be stomped on by the first branchmiss so
6597
        // there is no need to process it.
6598
        // The branchmiss has to be latched, then cleared later as there could
6599
        // be a cache miss at the same time meaning the switch to the new pc
6600
        // does not take place immediately.
6601
        if (!branchmiss) begin
6602
                if (excmiss) begin
6603
                        branchmiss <= `TRUE;
6604
                        misspc <= excmisspc;
6605
                        missid <= (|iqentry_exc[heads[0]] ? heads[0] : heads[1]);
6606
                        branchmiss_thrd <= excthrd;
6607
                end
6608
                else if (fcu_branchmiss) begin
6609
                        branchmiss <= `TRUE;
6610
                        misspc <= fcu_misspc;
6611
                        missid <= fcu_sourceid;
6612
                        branchmiss_thrd <= fcu_thrd;
6613
                end
6614
        end
6615
        // Clear a branch miss when target instruction is fetched.
6616
        if (will_clear_branchmiss) begin
6617
                branchmiss <= `FALSE;
6618
        end
6619
 
6620
        // The following signals only pulse
6621
 
6622
        // Instruction decode output should only pulse once for a queue entry. We
6623
        // want the decode to be invalidated after a clock cycle so that it isn't
6624
        // inadvertently used to update the queue at a later point.
6625
        dramA_v <= `INV;
6626
        dramB_v <= `INV;
6627
        dramC_v <= `INV;
6628
        id1_vi <= `INV;
6629
        if (`NUM_IDU > 1)
6630
                id2_vi <= `INV;
6631
        if (`NUM_IDU > 2)
6632
                id3_vi <= `INV;
6633
        wb_shift <= FALSE;
6634
        ld_time <= {ld_time[4:0],1'b0};
6635
        wc_times <= wc_time;
6636
     rf_vra0 <= regIsValid[Ra0s];
6637
     rf_vra1 <= regIsValid[Ra1s];
6638
    if (vqe0 >= vl) begin
6639
         vqe0 <= 6'd0;
6640
         vqet0 <= 6'h0;
6641
    end
6642
    if (vqe1 >= vl) begin
6643
         vqe1 <= 6'd0;
6644
         vqet1 <= 6'h0;
6645
    end
6646
    // Turn off vector chaining indicator when chained instructions are done.
6647
    if ((vqe0 >= vl || vqe0==6'd0) && (vqe1 >= vl || vqe1==6'd0))
6648
`ifdef SUPPORT_SMT
6649
        mstatus[0][32] <= 1'b0;
6650
`else
6651
        mstatus[32] <= 1'b0;
6652
`endif
6653
 
6654
     nop_fetchbuf <= 4'h0;
6655
     excmiss <= FALSE;
6656
     invic <= FALSE;
6657 66 robfinch
     if (L1_invline)
6658
        invicl <= FALSE;
6659 60 robfinch
     tick <= tick + 64'd1;
6660
     alu0_ld <= FALSE;
6661
     alu1_ld <= FALSE;
6662
     fpu1_ld <= FALSE;
6663
     fpu2_ld <= FALSE;
6664
     fcu_ld <= FALSE;
6665
     cr0[17] <= 1'b0;
6666
    if (waitctr != 48'd0)
6667
         waitctr <= waitctr - 4'd1;
6668
 
6669
 
6670
    if (iqentry_fc[fcu_id[`QBITS]] && iqentry_v[fcu_id[`QBITS]] && !iqentry_done[fcu_id[`QBITS]] && iqentry_out[fcu_id[`QBITS]])
6671
        fcu_timeout <= fcu_timeout + 8'd1;
6672
 
6673
        if (branchmiss) begin
6674
        for (n = 1; n < PREGS; n = n + 1)
6675
           if (~livetarget[n]) begin
6676
                        if (branchmiss_thrd) begin
6677
                                if (n >= 128)
6678
                                rf_v[n] <= `VAL;
6679
                        end
6680
                        else begin
6681
                                if (n < 128)
6682
                                rf_v[n] <= `VAL;
6683
                end
6684
           end
6685
                        for (n = 0; n < QENTRIES; n = n + 1)
6686
                if (|iqentry_latestID[n])
6687
                        if (iqentry_thrd[n]==branchmiss_thrd) rf_source[ {iqentry_tgt[n][7:0]} ] <= { 1'b0, iqentry_mem[n], n[`QBITS] };
6688
    end
6689
 
6690
    // The source for the register file data might have changed since it was
6691
    // placed on the commit bus. So it's needed to check that the source is
6692
    // still as expected to validate the register.
6693
                if (commit0_v) begin
6694
      if (!rf_v[ {commit0_tgt[7:0]} ]) begin
6695
//         rf_v[ {commit0_tgt[7:0]} ] <= rf_source[ commit0_tgt[7:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]);
6696
        rf_v[ {commit0_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}];//rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]);
6697
        if (regIsValid[{commit0_tgt[7:0]}])
6698
                rf_source[{commit0_tgt[7:0]}] <= {`QBIT{1'b1}};
6699
      end
6700
      if (commit0_tgt[5:0] != 6'd0) $display("r%d <- %h   v[%d]<-%d", commit0_tgt, commit0_bus, regIsValid[commit0_tgt[5:0]],
6701
      rf_source[ {commit0_tgt[7:0]} ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ]));
6702
      if (commit0_tgt[5:0]==6'd30 && commit0_bus==64'd0)
6703
        $display("FP <= 0");
6704
    end
6705
    if (commit1_v && `NUM_CMT > 1) begin
6706
      if (!rf_v[ {commit1_tgt[7:0]} ]) begin
6707
        if ({commit1_tgt[7:0]}=={commit0_tgt[7:0]}) begin
6708
                rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}];
6709
                if (regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}])
6710
                rf_source[{commit1_tgt[7:0]}] <= {`QBIT{1'b1}};
6711
                /*
6712
                        (rf_source[ commit0_tgt[4:0] ] == commit0_id || (branchmiss && iqentry_source[ commit0_id[`QBITS] ])) ||
6713
                        (rf_source[ commit1_tgt[4:0] ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]));
6714
                */
6715
        end
6716
        else begin
6717
                                        rf_v[ {commit1_tgt[7:0]} ] <= regIsValid[{commit1_tgt[7:0]}];//rf_source[ commit1_tgt[4:0] ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]);
6718
          if (regIsValid[{commit1_tgt[7:0]}])
6719
                rf_source[{commit1_tgt[7:0]}] <= {`QBIT{1'b1}};
6720
        end
6721
      end
6722
      if (commit1_tgt[5:0] != 6'd0) $display("r%d <- %h   v[%d]<-%d", commit1_tgt, commit1_bus, regIsValid[commit1_tgt[5:0]],
6723
      rf_source[ {commit1_tgt[7:0]} ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]));
6724
      if (commit1_tgt[5:0]==6'd30 && commit1_bus==64'd0)
6725
        $display("FP <= 0");
6726
    end
6727
    if (commit2_v && `NUM_CMT > 2) begin
6728
      if (!rf_v[ {commit2_tgt[7:0]} ]) begin
6729
        if ({commit2_tgt[7:0]}=={commit1_tgt[7:0]} && {commit2_tgt[7:0]}=={commit0_tgt[7:0]}) begin
6730
                rf_v[ {commit2_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}];
6731
                if (regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit1_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}])
6732
                rf_source[{commit0_tgt[7:0]}] <= {`QBIT{1'b1}};
6733
        end
6734
        else if ({commit2_tgt[7:0]}=={commit0_tgt[7:0]}) begin
6735
                rf_v[ {commit2_tgt[7:0]} ] <= regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}];
6736
                if (regIsValid[{commit0_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}])
6737
                rf_source[{commit0_tgt[7:0]}] <= {`QBIT{1'b1}};
6738
        end
6739
        else if ({commit2_tgt[7:0]}=={commit1_tgt[7:0]}) begin
6740
                rf_v[ {commit2_tgt[7:0]} ] <= regIsValid[{commit1_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}];
6741
                if (regIsValid[{commit1_tgt[7:0]}] | regIsValid[{commit2_tgt[7:0]}])
6742
                rf_source[{commit1_tgt[7:0]}] <= {`QBIT{1'b1}};
6743
        end
6744
        else begin
6745
                rf_v[ {commit2_tgt[7:0]} ] <= regIsValid[{commit2_tgt[7:0]}];//rf_source[ commit1_tgt[4:0] ] == commit1_id || (branchmiss && iqentry_source[ commit1_id[`QBITS] ]);
6746
                if (regIsValid[{commit2_tgt[7:0]}])
6747
                rf_source[{commit2_tgt[7:0]}] <= {`QBIT{1'b1}};
6748
        end
6749
      end
6750
      if (commit2_tgt[5:0] != 6'd0) $display("r%d <- %h   v[%d]<-%d", commit2_tgt, commit2_bus, regIsValid[commit2_tgt[5:0]],
6751
      rf_source[ {commit2_tgt[7:0]} ] == commit2_id || (branchmiss && iqentry_source[ commit2_id[`QBITS] ]));
6752
      if (commit2_tgt[5:0]==6'd30 && commit2_bus==64'd0)
6753
        $display("FP <= 0");
6754
    end
6755
     rf_v[0] <= 1;
6756
 
6757
  //
6758
  // ENQUEUE
6759
  //
6760
  // place up to two instructions from the fetch buffer into slots in the IQ.
6761
  //   note: they are placed in-order, and they are expected to be executed
6762
  // 0, 1, or 2 of the fetch buffers may have valid data
6763
  // 0, 1, or 2 slots in the instruction queue may be available.
6764
  // if we notice that one of the instructions in the fetch buffer is a predicted branch,
6765
  // (set branchback/backpc and delete any instructions after it in fetchbuf)
6766
  //
6767
 
6768
        // enqueue fetchbuf0 and fetchbuf1, but only if there is room, 
6769
        // and ignore fetchbuf1 if fetchbuf0 has a backwards branch in it.
6770
        //
6771
        // also, do some instruction-decode ... set the operand_valid bits in the IQ
6772
        // appropriately so that the DATAINCOMING stage does not have to look at the opcode
6773
        //
6774
        if (!branchmiss)        // don't bother doing anything if there's been a branch miss
6775
 
6776
                case ({fetchbuf0_v, fetchbuf1_v})
6777
 
6778
            2'b00: ; // do nothing
6779
 
6780
            2'b01:
6781
                    if (canq1) begin
6782
                                        if (fetchbuf1_rfw) begin
6783
                                                rf_source[ Rt1s ] <= { 1'b0, fetchbuf1_mem, tail0 };    // top bit indicates ALU/MEM bus
6784
                                                rf_v [Rt1s] <= `INV;
6785
                                        end
6786
                                        if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
6787
                                                vqe1 <= vqe1 + 4'd1;
6788
                                                if (IsVCmprss(fetchbuf1_instr)) begin
6789
                                                        if (vm[fetchbuf1_instr[25:23]][vqe1])
6790
                                                                vqet1 <= vqet1 + 4'd1;
6791
                                                end
6792
                                                else
6793
                                                        vqet1 <= vqet1 + 4'd1;
6794
                                                if (vqe1 >= vl-2)
6795
                                                        nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
6796
                                                enque1(tail0, fetchbuf1_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, vqe1);
6797
                                                iq_ctr = iq_ctr + 4'd1;
6798
                                                if (canq2 && vqe1 < vl-2) begin
6799
                                                        vqe1 <= vqe1 + 4'd2;
6800
                                                        if (IsVCmprss(fetchbuf1_instr)) begin
6801
                                                                if (vm[fetchbuf1_instr[25:23]][vqe1+6'd1])
6802
                                                                        vqet1 <= vqet1 + 4'd2;
6803
                                                        end
6804
                                                        else
6805
                                                                vqet1 <= vqet1 + 4'd2;
6806
                                                        enque1(tail1, fetchbuf1_thrd ? maxsn[1] + 4'd2 : maxsn[0] + 4'd2, vqe1 + 6'd1);
6807
                                                        iq_ctr = iq_ctr + 4'd2;
6808
                                                end
6809
                                        end
6810
                                        else begin
6811
                                                enque1(tail0, fetchbuf1_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, 6'd0);
6812
                                                iq_ctr = iq_ctr + 4'd1;
6813
                                        end
6814
                    end
6815
 
6816
            2'b10:
6817
                if (canq1) begin
6818
                        enque0x();
6819
                    end
6820
 
6821
            2'b11:
6822
                    if (canq1) begin
6823
                                //
6824
                                // if the first instruction is a predicted branch, enqueue it & stomp on all following instructions
6825
                                // but only if the following instruction is in the same thread. Otherwise we want to queue two.
6826
                                //
6827
                                if (take_branch0 && fetchbuf1_thrd==fetchbuf0_thrd) begin
6828
                                        enque0x();
6829
                                end
6830
 
6831
                                else begin      // fetchbuf0 doesn't contain a predicted branch
6832
                                    //
6833
                                    // so -- we can enqueue 1 or 2 instructions, depending on space in the IQ
6834
                                    // update the rf_v and rf_source bits separately (at end)
6835
                                    //   the problem is that if we do have two instructions, 
6836
                                    //   they may interact with each other, so we have to be
6837
                                    //   careful about where things point.
6838
                                    //
6839
                                    // enqueue the first instruction ...
6840
                                    //
6841
                            if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
6842
                                 vqe0 <= vqe0 + 4'd1;
6843
                                if (IsVCmprss(fetchbuf0_instr)) begin
6844
                                    if (vm[fetchbuf0_instr[25:23]][vqe0])
6845
                                         vqet0 <= vqet0 + 4'd1;
6846
                                end
6847
                                else
6848
                                     vqet0 <= vqet0 + 4'd1;
6849
                                if (vqe0 >= vl-2)
6850
                                        nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
6851
                            end
6852
                            if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
6853
                                    enque0(tail0, fetchbuf0_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, vqe0);
6854
                                                                        iq_ctr = iq_ctr + 4'd1;
6855
                                            //
6856
                                            // if there is room for a second instruction, enqueue it
6857
                                            //
6858
                                            if (canq2) begin
6859
                                                if (vechain && IsVector(fetchbuf1_instr)
6860
                                                && Ra1s != Rt0s // And there is no dependency
6861
                                                && Rb1s != Rt0s
6862
                                                && Rc1s != Rt0s
6863
                                                ) begin
6864
`ifdef SUPPORT_SMT
6865
                                                        mstatus[0][32] <= 1'b1;
6866
`else
6867
                                                        mstatus[32] <= 1'b1;
6868
`endif
6869
                                                vqe1 <= vqe1 + 4'd1;
6870
                                                if (IsVCmprss(fetchbuf1_instr)) begin
6871
                                                    if (vm[fetchbuf1_instr[25:23]][vqe1])
6872
                                                         vqet1 <= vqet1 + 4'd1;
6873
                                                end
6874
                                                else
6875
                                                     vqet1 <= vqet1 + 4'd1;
6876
                                                if (vqe1 >= vl-2)
6877
                                                        nop_fetchbuf <= fetchbuf ? 4'b0100 : 4'b0001;
6878
                                                        enque1(tail1,
6879
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? maxsn[1] + 4'd2 :
6880
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? maxsn[0] + 4'd2 :
6881
                                                                fetchbuf1_thrd ? maxsn[1] + 4'd2: maxsn[0] + 4'd2, 6'd0);
6882
                                                                                iq_ctr = iq_ctr + 4'd2;
6883
 
6884
                                                                // SOURCE 1 ...
6885
                                                                a1_vs();
6886
 
6887
                                                                // SOURCE 2 ...
6888
                                                                a2_vs();
6889
 
6890
                                                                // SOURCE 3 ...
6891
                                                                a3_vs();
6892
 
6893
                                                                // if the two instructions enqueued target the same register, 
6894
                                                                // make sure only the second writes to rf_v and rf_source.
6895
                                                                // first is allowed to update rf_v and rf_source only if the
6896
                                                                // second has no target
6897
                                                                //
6898
                                                            if (fetchbuf0_rfw) begin
6899
                                                                     rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_mem, tail0 };
6900
                                                                     rf_v [ Rt0s] <= `INV;
6901
                                                            end
6902
                                                            if (fetchbuf1_rfw) begin
6903
                                                                     rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_mem, tail1 };
6904
                                                                     rf_v [ Rt1s ] <= `INV;
6905
                                                            end
6906
                                                end
6907
                                                // If there was a vector instruction in fetchbuf0, we really
6908
                                                // want to queue the next vector element, not the next
6909
                                                // instruction waiting in fetchbuf1.
6910
                                            else if (IsVector(fetchbuf0_instr) && SUP_VECTOR && vqe0 < vl-1) begin
6911
                                                 vqe0 <= vqe0 + 4'd2;
6912
                                                if (IsVCmprss(fetchbuf0_instr)) begin
6913
                                                    if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
6914
                                                         vqet0 <= vqet0 + 4'd2;
6915
                                                end
6916
                                                else
6917
                                                     vqet0 <= vqet0 + 4'd2;
6918
                                                if (vqe0 >= vl-3)
6919
                                                 nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
6920
                                            if (vqe0 < vl-1) begin
6921
                                                                enque0(tail1, fetchbuf0_thrd ? maxsn[1] + 4'd2 : maxsn[0] + 4'd2, vqe0 + 6'd1);
6922
                                                                                        iq_ctr = iq_ctr + 4'd2;
6923
 
6924
                                                                        // SOURCE 1 ...
6925
                                                     iqentry_a1_v [tail1] <= regIsValid[Ra0s];
6926
                                                     iqentry_a1_s [tail1] <= rf_source [Ra0s];
6927
 
6928
                                                                        // SOURCE 2 ...
6929
                                                     iqentry_a2_v [tail1] <= regIsValid[Rb0s];
6930
                                                     iqentry_a2_s [tail1] <= rf_source[ Rb0s ];
6931
 
6932
                                                                        // SOURCE 3 ...
6933
                                                     iqentry_a3_v [tail1] <= regIsValid[Rc0s];
6934
                                                     iqentry_a3_s [tail1] <= rf_source[ Rc0s ];
6935
 
6936
 
6937
                                                                        // if the two instructions enqueued target the same register, 
6938
                                                                        // make sure only the second writes to rf_v and rf_source.
6939
                                                                        // first is allowed to update rf_v and rf_source only if the
6940
                                                                        // second has no target (BEQ or SW)
6941
                                                                        //
6942
                                                                    if (fetchbuf0_rfw) begin
6943
                                                                             rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail1 };
6944
                                                                             rf_v [ Rt0s ] <= `INV;
6945
                                                                    end
6946
                                                                end
6947
                                                end
6948
                                            else if (IsVector(fetchbuf1_instr) && SUP_VECTOR) begin
6949
                                                 vqe1 <= 6'd1;
6950
                                                if (IsVCmprss(fetchbuf1_instr)) begin
6951
                                                    if (vm[fetchbuf1_instr[25:23]][IsVector(fetchbuf0_instr)? 6'd0:vqe1+6'd1])
6952
                                                         vqet1 <= 6'd1;
6953
                                                else
6954
                                                         vqet1 <= 6'd0;
6955
                                                end
6956
                                                else
6957
                                                         vqet1 <= 6'd1;
6958
                                            if (IsVector(fetchbuf0_instr) && SUP_VECTOR)
6959
                                                        nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
6960
                                                        enque1(tail1,
6961
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? maxsn[1] + 4'd2 :
6962
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? maxsn[0] + 4'd2 :
6963
                                                                fetchbuf1_thrd ? maxsn[1] + 4'd2: maxsn[0] + 4'd2, 6'd0);
6964
                                                                                iq_ctr = iq_ctr + 4'd2;
6965
 
6966
                                                                // SOURCE 1 ...
6967
                                                                a1_vs();
6968
 
6969
                                                                // SOURCE 2 ..
6970
                                                                a2_vs();
6971
 
6972
                                                                // SOURCE 3 ...
6973
                                                                a3_vs();
6974
 
6975
                                                                // if the two instructions enqueued target the same register, 
6976
                                                                // make sure only the second writes to rf_v and rf_source.
6977
                                                                // first is allowed to update rf_v and rf_source only if the
6978
                                                                // second has no target
6979
                                                                //
6980
                                                            if (fetchbuf0_rfw) begin
6981
                                                                     rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_mem, tail0 };
6982
                                                                     rf_v [ Rt0s] <= `INV;
6983
                                                            end
6984
                                                            if (fetchbuf1_rfw) begin
6985
                                                                     rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_mem, tail1 };
6986
                                                                     rf_v [ Rt1s ] <= `INV;
6987
                                                            end
6988
                                            end
6989
                                            else begin
6990
//                                                      enque1(tail1, seq_num + 5'd1, 6'd0);
6991
                                                        enque1(tail1,
6992
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b1 ? maxsn[1] + 4'd2 :
6993
                                                                fetchbuf1_thrd==fetchbuf0_thrd && fetchbuf1_thrd==1'b0 ? maxsn[0] + 4'd2 :
6994
                                                                fetchbuf1_thrd ? maxsn[1] + 4'd1: maxsn[0]+4'd1, 6'd0);
6995
                                                                                iq_ctr = iq_ctr + 4'd2;
6996
 
6997
                                                                // SOURCE 1 ...
6998
                                                                a1_vs();
6999
 
7000
                                                                // SOURCE 2 ...
7001
                                                                a2_vs();
7002
 
7003
                                                                // SOURCE 3 ...
7004
                                                                a3_vs();
7005
 
7006
 
7007
                                                                // if the two instructions enqueued target the same register, 
7008
                                                                // make sure only the second writes to regIsValid and rf_source.
7009
                                                                // first is allowed to update regIsValid and rf_source only if the
7010
                                                                // second has no target (BEQ or SW)
7011
                                                                //
7012
                                                            if (fetchbuf0_rfw) begin
7013
                                                                     rf_source[ Rt0s ] <= { 1'b0,fetchbuf0_mem, tail0 };
7014
                                                                     rf_v [ Rt0s] <= `INV;
7015
                                                                     $display("r%dx (%d) Invalidated", Rt0s, Rt0s[4:0]);
7016
                                                            end
7017
                                                            else
7018
                                                                $display("No rfw");
7019
                                                            if (fetchbuf1_rfw) begin
7020
                                                                     rf_source[ Rt1s ] <= { 1'b0,fetchbuf1_mem, tail1 };
7021
                                                                     $display("r%dx (%d) Invalidated", Rt1s, Rt1s[4:0]);
7022
                                                                     rf_v [ Rt1s ] <= `INV;
7023
                                                            end
7024
                                                            else
7025
                                                                $display("No rfw");
7026
                                                        end
7027
 
7028
                                            end // ends the "if IQ[tail1] is available" clause
7029
                                            else begin  // only first instruction was enqueued
7030
                                                        if (fetchbuf0_rfw) begin
7031
                                                             $display("r%dx (%d) Invalidated 1", Rt0s, Rt0s[4:0]);
7032
                                                             rf_source[ Rt0s ] <= {1'b0,fetchbuf0_mem, tail0};
7033
                                                             rf_v [ Rt0s ] <= `INV;
7034
                                                        end
7035
                                                end
7036
                                    end
7037
 
7038
                                end     // ends the "else fetchbuf0 doesn't have a backwards branch" clause
7039
                    end
7040
                endcase
7041
        if (pebm) begin
7042
                bm_ctr <= bm_ctr + 40'd1;
7043
        end
7044
 
7045
//
7046
// DATAINCOMING
7047
//
7048
// wait for operand/s to appear on alu busses and puts them into 
7049
// the iqentry_a1 and iqentry_a2 slots (if appropriate)
7050
// as well as the appropriate iqentry_res slots (and setting valid bits)
7051
//
7052
// put results into the appropriate instruction entries
7053
//
7054
// This chunk of code has to be before the enqueue stage so that the agen bit
7055
// can be reset to zero by enqueue.
7056
// put results into the appropriate instruction entries
7057
//
7058
if (IsMul(alu0_instr)|IsDivmod(alu0_instr)|alu0_shft|alu0_tlb) begin
7059
        if (alu0_done_pe) begin
7060
                alu0_dataready <= TRUE;
7061
        end
7062
end
7063
if (alu1_shft) begin
7064
        if (alu1_done_pe) begin
7065
                alu1_dataready <= TRUE;
7066
        end
7067
end
7068
 
7069
if (alu0_v) begin
7070
        iqentry_tgt [ alu0_id[`QBITS] ] <= alu0_tgt;
7071
        iqentry_res     [ alu0_id[`QBITS] ] <= ralu0_bus;
7072
        iqentry_exc     [ alu0_id[`QBITS] ] <= alu0_exc;
7073 66 robfinch
        if (!iqentry_mem[ alu0_id[`QBITS] ] && alu0_done && tlb_done) begin
7074 60 robfinch
//              iqentry_done[ alu0_id[`QBITS] ] <= `TRUE;
7075
                iqentry_state[alu0_id[`QBITS]] <= IQS_CMT;
7076
        end
7077
//      if (alu0_done)
7078
//              iqentry_cmt [ alu0_id[`QBITS] ] <= `TRUE;
7079
//      iqentry_out     [ alu0_id[`QBITS] ] <= `INV;
7080
//      iqentry_agen[ alu0_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]];  // RET
7081
        if (iqentry_mem[alu0_id[`QBITS]])
7082
                iqentry_state[alu0_id[`QBITS]] <= IQS_AGEN;
7083
        if (iqentry_mem[ alu0_id[`QBITS] ] && !iqentry_agen[ alu0_id[`QBITS] ]) begin
7084
                iqentry_ma[ alu0_id[`QBITS] ] <= alu0_bus;
7085
        end
7086
        if (|alu0_exc) begin
7087
//              iqentry_done[alu0_id[`QBITS]] <= `VAL;
7088
                iqentry_store[alu0_id[`QBITS]] <= `INV;
7089
                iqentry_state[alu0_id[`QBITS]] <= IQS_CMT;
7090
        end
7091
        alu0_dataready <= FALSE;
7092
end
7093
 
7094
if (alu1_v && `NUM_ALU > 1) begin
7095
        iqentry_tgt [ alu1_id[`QBITS] ] <= alu1_tgt;
7096
        iqentry_res     [ alu1_id[`QBITS] ] <= ralu1_bus;
7097
        iqentry_exc     [ alu1_id[`QBITS] ] <= alu1_exc;
7098
        if (!iqentry_mem[ alu1_id[`QBITS] ] && alu1_done) begin
7099
//              iqentry_done[ alu1_id[`QBITS] ] <= `TRUE;
7100
                iqentry_state[alu1_id[`QBITS]] <= IQS_CMT;
7101
        end
7102
//      iqentry_done[ alu1_id[`QBITS] ] <= (!iqentry_mem[ alu1_id[`QBITS] ] && alu1_done);
7103
//      if (alu1_done)
7104
//              iqentry_cmt [ alu1_id[`QBITS] ] <= `TRUE;
7105
//      iqentry_out     [ alu1_id[`QBITS] ] <= `INV;
7106
        if (iqentry_mem[alu1_id[`QBITS]])
7107
                iqentry_state[alu1_id[`QBITS]] <= IQS_AGEN;
7108
//      iqentry_agen[ alu1_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]];  // RET
7109
        if (iqentry_mem[ alu1_id[`QBITS] ] && !iqentry_agen[ alu1_id[`QBITS] ]) begin
7110
                iqentry_ma[ alu1_id[`QBITS] ] <= alu1_bus;
7111
        end
7112
        if (|alu1_exc) begin
7113
//              iqentry_done[alu1_id[`QBITS]] <= `VAL;
7114
                iqentry_store[alu1_id[`QBITS]] <= `INV;
7115
                iqentry_state[alu1_id[`QBITS]] <= IQS_CMT;
7116
        end
7117
        alu1_dataready <= FALSE;
7118
end
7119
 
7120
if (fpu1_v && `NUM_FPU > 0) begin
7121
        iqentry_res [ fpu1_id[`QBITS] ] <= rfpu1_bus;
7122
        iqentry_ares[ fpu1_id[`QBITS] ] <= fpu1_status;
7123
        iqentry_exc [ fpu1_id[`QBITS] ] <= fpu1_exc;
7124
//      iqentry_done[ fpu1_id[`QBITS] ] <= fpu1_done;
7125
//      iqentry_out [ fpu1_id[`QBITS] ] <= `INV;
7126
        iqentry_state[fpu1_id[`QBITS]] <= IQS_CMT;
7127
        fpu1_dataready <= FALSE;
7128
end
7129
 
7130
if (fpu2_v && `NUM_FPU > 1) begin
7131
        iqentry_res [ fpu2_id[`QBITS] ] <= rfpu2_bus;
7132
        iqentry_ares[ fpu2_id[`QBITS] ] <= fpu2_status;
7133
        iqentry_exc [ fpu2_id[`QBITS] ] <= fpu2_exc;
7134
//      iqentry_done[ fpu2_id[`QBITS] ] <= fpu2_done;
7135
//      iqentry_out [ fpu2_id[`QBITS] ] <= `INV;
7136
        iqentry_state[fpu2_id[`QBITS]] <= IQS_CMT;
7137
        //iqentry_agen[ fpu_id[`QBITS] ] <= `VAL;  // RET
7138
        fpu2_dataready <= FALSE;
7139
end
7140
 
7141
if (IsWait(fcu_instr)) begin
7142
        if (pe_wait)
7143
                fcu_dataready <= `TRUE;
7144
end
7145
 
7146 61 robfinch
// If the return segment is not the same as the current code segment then a
7147
// segment load is triggered via the memory unit by setting the iq state to
7148
// AGEN. Otherwise the state is set to CMT which will cause a bypass of the
7149
// segment load from memory.
7150
 
7151 60 robfinch
if (fcu_v) begin
7152
        fcu_done <= `TRUE;
7153
        iqentry_ma  [ fcu_id[`QBITS] ] <= fcu_misspc;
7154
  iqentry_res [ fcu_id[`QBITS] ] <= rfcu_bus;
7155
  iqentry_exc [ fcu_id[`QBITS] ] <= fcu_exc;
7156
        iqentry_state[fcu_id[`QBITS] ] <= IQS_CMT;
7157
        // takb is looked at only for branches to update the predictor. Here it is
7158
        // unconditionally set, the value will be ignored if it's not a branch.
7159
        iqentry_takb[ fcu_id[`QBITS] ] <= fcu_takb;
7160 61 robfinch
        br_ctr <= br_ctr + fcu_branch;
7161 60 robfinch
        fcu_dataready <= `INV;
7162
end
7163
 
7164
// dramX_v only set on a load
7165 61 robfinch
if (dramA_v && iqentry_v[ dramA_id[`QBITS] ]) begin
7166 60 robfinch
        iqentry_res     [ dramA_id[`QBITS] ] <= rdramA_bus;
7167
//      iqentry_done[ dramA_id[`QBITS] ] <= `VAL;
7168
//      iqentry_out [ dramA_id[`QBITS] ] <= `INV;
7169
        iqentry_state[dramA_id[`QBITS] ] <= IQS_CMT;
7170
        iqentry_aq  [ dramA_id[`QBITS] ] <= `INV;
7171
end
7172 61 robfinch
if (`NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ]) begin
7173 60 robfinch
        iqentry_res     [ dramB_id[`QBITS] ] <= rdramB_bus;
7174
        iqentry_state[dramB_id[`QBITS] ] <= IQS_CMT;
7175
        iqentry_aq  [ dramB_id[`QBITS] ] <= `INV;
7176
end
7177 61 robfinch
if (`NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ]) begin
7178 60 robfinch
        iqentry_res     [ dramC_id[`QBITS] ] <= rdramC_bus;
7179
        iqentry_state[dramC_id[`QBITS] ] <= IQS_CMT;
7180
        iqentry_aq  [ dramC_id[`QBITS] ] <= `INV;
7181
//          if (iqentry_lptr[dram2_id[`QBITS]])
7182
//              wbrcd[pcr[5:0]] <= 1'b1;
7183
end
7184
 
7185
//
7186
// see if anybody else wants the results ... look at lots of buses:
7187
//  - fpu_bus
7188
//  - alu0_bus
7189
//  - alu1_bus
7190
//  - fcu_bus
7191
//  - dram_bus
7192
//  - commit0_bus
7193
//  - commit1_bus
7194
//
7195
 
7196
for (n = 0; n < QENTRIES; n = n + 1)
7197
begin
7198
        if (`NUM_FPU > 0)
7199
                setargs(n,{1'b0,fpu1_id},fpu1_v,rfpu1_bus);
7200
        if (`NUM_FPU > 1)
7201
                setargs(n,{1'b0,fpu2_id},fpu2_v,rfpu2_bus);
7202
 
7203
        // The memory address generated by the ALU should not be posted to be
7204
        // recieved into waiting argument registers. The arguments will be waiting
7205
        // for the result of the memory load, picked up from the dram busses. The
7206
        // only mem operation requiring the alu result bus is the push operation.
7207
        setargs(n,{1'b0,alu0_id},alu0_v & (~alu0_mem | alu0_push),ralu0_bus);
7208
        if (`NUM_ALU > 1)
7209
                setargs(n,{1'b0,alu1_id},alu1_v & (~alu1_mem | alu1_push),ralu1_bus);
7210
 
7211
        setargs(n,{1'b0,fcu_id},fcu_v,rfcu_bus);
7212
 
7213
        setargs(n,{1'b0,dramA_id},dramA_v,rdramA_bus);
7214
        if (`NUM_MEM > 1)
7215
                setargs(n,{1'b0,dramB_id},dramB_v,rdramB_bus);
7216
        if (`NUM_MEM > 2)
7217
                setargs(n,{1'b0,dramC_id},dramC_v,rdramC_bus);
7218
 
7219
        setargs(n,commit0_id,commit0_v,commit0_bus);
7220
        if (`NUM_CMT > 1)
7221
                setargs(n,commit1_id,commit1_v,commit1_bus);
7222
        if (`NUM_CMT > 2)
7223
                setargs(n,commit2_id,commit2_v,commit2_bus);
7224
`ifndef INLINE_DECODE
7225
        setinsn(n[`QBITS],id1_ido,id1_available&id1_vo,id1_bus);
7226
        if (`NUM_IDU > 1)
7227
                setinsn(n[`QBITS],id2_ido,id2_available&id2_vo,id2_bus);
7228
        if (`NUM_IDU > 2)
7229
                setinsn(n[`QBITS],id3_ido,id3_available&id3_vo,id3_bus);
7230
`endif
7231
end
7232
 
7233
 
7234
//
7235
// ISSUE 
7236
//
7237
// determines what instructions are ready to go, then places them
7238
// in the various ALU queues.  
7239
// also invalidates instructions following a branch-miss BEQ or any JALR (STOMP logic)
7240
//
7241
`ifndef INLINE_DECODE
7242
for (n = 0; n < QENTRIES; n = n + 1)
7243
if (id1_available) begin
7244
if (iqentry_id1issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7245
                id1_vi <= `VAL;
7246
                id1_id                  <= n[4:0];
7247
                id1_instr       <= iqentry_rtop[n] ? (
7248
                                                                                iqentry_a3_v[n] ? iqentry_a3[n]
7249
`ifdef FU_BYPASS
7250
                                : (iqentry_a3_s[n] == alu0_id) ? alu0_bus
7251
                                : (iqentry_a3_s[n] == alu1_id) ? alu1_bus
7252
`endif
7253
                                : `NOP_INSN)
7254
                                                                 : iqentry_instr[n];
7255
                id1_ven    <= iqentry_ven[n];
7256
                id1_vl     <= iqentry_vl[n];
7257
                id1_thrd   <= iqentry_thrd[n];
7258
                id1_Rt     <= iqentry_tgt[n][4:0];
7259
                id1_pt                  <= iqentry_pt[n];
7260
  end
7261
end
7262
if (`NUM_IDU > 1) begin
7263
for (n = 0; n < QENTRIES; n = n + 1)
7264
        if (id2_available) begin
7265
                if (iqentry_id2issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7266
                        id2_vi <= `VAL;
7267
                        id2_id                  <= n[4:0];
7268
                        id2_instr       <= iqentry_rtop[n] ? (
7269
                                                                                        iqentry_a3_v[n] ? iqentry_a3[n]
7270
`ifdef FU_BYPASS
7271
                                        : (iqentry_a3_s[n] == alu0_id) ? alu0_bus
7272
                                        : (iqentry_a3_s[n] == alu1_id) ? alu1_bus
7273
`endif
7274
                                        : `NOP_INSN)
7275
                                                                         : iqentry_instr[n];
7276
                        id2_ven    <= iqentry_ven[n];
7277
                        id2_vl     <= iqentry_vl[n];
7278
                        id2_thrd   <= iqentry_thrd[n];
7279
                        id2_Rt     <= iqentry_tgt[n][4:0];
7280
                        id2_pt                  <= iqentry_pt[n];
7281
                end
7282
        end
7283
end
7284
if (`NUM_IDU > 2) begin
7285
for (n = 0; n < QENTRIES; n = n + 1)
7286
        if (id3_available) begin
7287
                if (iqentry_id3issue[n] && !iqentry_iv[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7288
                        id3_vi <= `VAL;
7289
                        id3_id                  <= n[4:0];
7290
                        id3_instr       <= iqentry_rtop[n] ? (
7291
                                                                                        iqentry_a3_v[n] ? iqentry_a3[n]
7292
`ifdef FU_BYPASS
7293
                                        : (iqentry_a3_s[n] == alu0_id) ? alu0_bus
7294
                                        : (iqentry_a3_s[n] == alu1_id) ? alu1_bus
7295
`endif
7296
                                        : `NOP_INSN)
7297
                                                                         : iqentry_instr[n];
7298
                        id3_ven    <= iqentry_ven[n];
7299
                        id3_vl     <= iqentry_vl[n];
7300
                        id3_thrd   <= iqentry_thrd[n];
7301
                        id3_Rt     <= iqentry_tgt[n][4:0];
7302
                        id3_pt                  <= iqentry_pt[n];
7303
                end
7304
        end
7305
end
7306
`endif  // not INLINE_DECODE
7307
 
7308
// X's on unused busses cause problems in SIM.
7309
    for (n = 0; n < QENTRIES; n = n + 1)
7310
        if (iqentry_alu0_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7311
            if (alu0_available & alu0_done) begin
7312
                 alu0_sourceid  <= {iqentry_push[n],n[`QBITS]};
7313
                 alu0_instr     <= iqentry_rtop[n] ? (
7314
`ifdef FU_BYPASS
7315
                                                                                        iqentry_a3_v[n] ? iqentry_a3[n]
7316
                                                    : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus
7317
                                                    : (iqentry_a3_s[n] == alu1_id) ? ralu1_bus
7318
                                                    : (iqentry_a3_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7319
                                                    : `NOP_INSN)
7320
`else
7321
                                                                                                                                        iqentry_a3[n])
7322
`endif
7323
                                                                         : iqentry_instr[n];
7324
                 alu0_sz    <= iqentry_sz[n];
7325
                 alu0_tlb   <= iqentry_tlb[n];
7326
                 alu0_mem   <= iqentry_mem[n];
7327
                 alu0_load  <= iqentry_load[n];
7328
                 alu0_store <= iqentry_store[n];
7329
                 alu0_push  <= iqentry_push[n];
7330
                 alu0_shft <= iqentry_shft[n];
7331
                 alu0_pc                <= iqentry_pc[n];
7332
                 alu0_argA      <=
7333
`ifdef FU_BYPASS
7334
                                                                        iqentry_a1_v[n] ? iqentry_a1[n]
7335
                            : (iqentry_a1_s[n] == alu0_id) ? ralu0_bus
7336
                            : (iqentry_a1_s[n] == alu1_id) ? ralu1_bus
7337
                            : (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7338
                            : 64'hDEADDEADDEADDEAD;
7339
`else
7340
                                                                                                                iqentry_a1[n];
7341
`endif
7342
                 alu0_argB      <= iqentry_imm[n]
7343
                            ? iqentry_a0[n]
7344
`ifdef FU_BYPASS
7345
                            : (iqentry_a2_v[n] ? iqentry_a2[n]
7346
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus
7347
                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus
7348
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7349
                            : 64'hDEADDEADDEADDEAD);
7350
`else
7351
                                                                                                                : iqentry_a2[n];
7352
`endif
7353
                 alu0_argC      <=
7354
`ifdef FU_BYPASS
7355
                                                                        iqentry_a3_v[n] ? iqentry_a3[n]
7356
                            : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus : ralu1_bus;
7357
`else
7358
                                                                                                                        iqentry_a3[n];
7359
`endif
7360
                 alu0_argI      <= iqentry_a0[n];
7361
                 alu0_tgt    <= IsVeins(iqentry_instr[n]) ?
7362
                                {6'h0,1'b1,iqentry_tgt[n][4:0]} | ((
7363
                                                                                        iqentry_a2_v[n] ? iqentry_a2[n][5:0]
7364
                                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus[5:0]
7365
                                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus[5:0]
7366
                                            : {4{16'h0000}})) << 6 :
7367
                                iqentry_tgt[n];
7368
                 alu0_ven    <= iqentry_ven[n];
7369
                 alu0_thrd   <= iqentry_thrd[n];
7370
                 alu0_dataready <= IsSingleCycle(iqentry_instr[n]);
7371
                 alu0_ld <= TRUE;
7372
                 iqentry_state[n] <= IQS_OUT;
7373
            end
7374
        end
7375
        if (`NUM_ALU > 1) begin
7376
    for (n = 0; n < QENTRIES; n = n + 1)
7377
        if (iqentry_alu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7378
            if (alu1_available && alu1_done) begin
7379
                        if (iqentry_alu0[n])
7380
                                panic <= `PANIC_ALU0ONLY;
7381
                 alu1_sourceid  <= {iqentry_push[n],n[`QBITS]};
7382
                 alu1_instr     <= iqentry_instr[n];
7383
                 alu1_sz    <= iqentry_sz[n];
7384
                 alu1_mem   <= iqentry_mem[n];
7385
                 alu1_load  <= iqentry_load[n];
7386
                 alu1_store <= iqentry_store[n];
7387
                 alu1_push  <= iqentry_push[n];
7388
                 alu1_shft  <= iqentry_shft[n];
7389
                 alu1_pc                <= iqentry_pc[n];
7390
                 alu1_argA      <=
7391
`ifdef FU_BYPASS
7392
                                                                        iqentry_a1_v[n] ? iqentry_a1[n]
7393
                            : (iqentry_a1_s[n] == alu0_id) ? ralu0_bus
7394
                            : (iqentry_a1_s[n] == alu1_id) ? ralu1_bus
7395
                            : (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7396
                            : 64'hDEADDEADDEADDEAD;
7397
`else
7398
                                                                                                                        iqentry_a1[n];
7399
`endif
7400
                 alu1_argB      <= iqentry_imm[n]
7401
                            ? iqentry_a0[n]
7402
`ifdef FU_BYPASS
7403
                            : (iqentry_a2_v[n] ? iqentry_a2[n]
7404
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus
7405
                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus
7406
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7407
                            : 64'hDEADDEADDEADDEAD);
7408
`else
7409
                                                                                                                : iqentry_a2[n];
7410
`endif
7411
                 alu1_argC      <=
7412
`ifdef FU_BYPASS
7413
                                                                        iqentry_a3_v[n] ? iqentry_a3[n]
7414
                            : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus : ralu1_bus;
7415
`else
7416
                                                                                                                        iqentry_a3[n];
7417
`endif
7418
                 alu1_argI      <= iqentry_a0[n];
7419
                 alu1_tgt    <= IsVeins(iqentry_instr[n]) ?
7420
                                {6'h0,1'b1,iqentry_tgt[n][4:0]} | ((iqentry_a2_v[n] ? iqentry_a2[n][5:0]
7421
                                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus[5:0]
7422
                                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus[5:0]
7423
                                            : {4{16'h0000}})) << 6 :
7424
                                iqentry_tgt[n];
7425
                 alu1_ven    <= iqentry_ven[n];
7426
                 alu1_dataready <= IsSingleCycle(iqentry_instr[n]);
7427
                 alu1_ld <= TRUE;
7428
                 iqentry_state[n] <= IQS_OUT;
7429
            end
7430
        end
7431
  end
7432
 
7433
    for (n = 0; n < QENTRIES; n = n + 1)
7434
        if (iqentry_fpu1_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7435
            if (fpu1_available & fpu1_done) begin
7436
                 fpu1_sourceid  <= n[`QBITS];
7437
                 fpu1_instr     <= iqentry_instr[n];
7438
                 fpu1_pc                <= iqentry_pc[n];
7439
                 fpu1_argA      <=
7440
`ifdef FU_BYPASS
7441
                                                                        iqentry_a1_v[n] ? iqentry_a1[n]
7442
                            : (iqentry_a1_s[n] == alu0_id) ? ralu0_bus
7443
                            : (iqentry_a1_s[n] == alu1_id) ? ralu1_bus
7444
                            : (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7445
                            : 64'hDEADDEADDEADDEAD;
7446
`else
7447
                                                                                                                        iqentry_a1[n];
7448
`endif
7449
                 fpu1_argB      <=
7450
`ifdef FU_BYPASS
7451
                                                                        (iqentry_a2_v[n] ? iqentry_a2[n]
7452
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus
7453
                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus
7454
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7455
                            : 64'hDEADDEADDEADDEAD);
7456
`else
7457
                                                                                                                        iqentry_a2[n];
7458
`endif
7459
                 fpu1_argC      <=
7460
`ifdef FU_BYPASS
7461
                                                                         iqentry_a3_v[n] ? iqentry_a3[n]
7462
                            : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus : ralu1_bus;
7463
`else
7464
                                                                                                                        iqentry_a3[n];
7465
`endif
7466
                 fpu1_argI      <= iqentry_a0[n];
7467
                 fpu1_dataready <= `VAL;
7468
                 fpu1_ld <= TRUE;
7469
                 iqentry_state[n] <= IQS_OUT;
7470
            end
7471
        end
7472
 
7473
    for (n = 0; n < QENTRIES; n = n + 1)
7474
        if (`NUM_FPU > 1 && iqentry_fpu2_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7475
            if (fpu2_available & fpu2_done) begin
7476
                 fpu2_sourceid  <= n[`QBITS];
7477
                 fpu2_instr     <= iqentry_instr[n];
7478
                 fpu2_pc                <= iqentry_pc[n];
7479
                 fpu2_argA      <=
7480
`ifdef FU_BYPASS
7481
                                                                        iqentry_a1_v[n] ? iqentry_a1[n]
7482
                            : (iqentry_a1_s[n] == alu0_id) ? ralu0_bus
7483
                            : (iqentry_a1_s[n] == alu1_id) ? ralu1_bus
7484
                            : (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7485
                            : 64'hDEADDEADDEADDEAD;
7486
`else
7487
                                                                                                                        iqentry_a1[n];
7488
`endif
7489
                 fpu2_argB      <=
7490
`ifdef FU_BYPASS
7491
                                                                        (iqentry_a2_v[n] ? iqentry_a2[n]
7492
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus
7493
                            : (iqentry_a2_s[n] == alu1_id) ? ralu1_bus
7494
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7495
                            : 64'hDEADDEADDEADDEAD);
7496
`else
7497
                                                                                                                        iqentry_a2[n];
7498
`endif
7499
                 fpu2_argC      <=
7500
`ifdef FU_BYPASS
7501
                                                                         iqentry_a3_v[n] ? iqentry_a3[n]
7502
                            : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus : ralu1_bus;
7503
`else
7504
                                                                                                                        iqentry_a3[n];
7505
`endif
7506
                 fpu2_argI      <= iqentry_a0[n];
7507
                 fpu2_dataready <= `VAL;
7508
                 fpu2_ld <= TRUE;
7509
                 iqentry_state[n] <= IQS_OUT;
7510
            end
7511
        end
7512
 
7513
    for (n = 0; n < QENTRIES; n = n + 1)
7514
        if (iqentry_fcu_issue[n] && !(iqentry_v[n] && iqentry_stomp[n])) begin
7515
            if (fcu_done) begin
7516
                 fcu_sourceid   <= n[`QBITS];
7517
                 fcu_prevInstr <= fcu_instr;
7518
                 fcu_instr      <= iqentry_instr[n];
7519
                 fcu_insln  <= iqentry_insln[n];
7520
                 fcu_pc         <= iqentry_pc[n];
7521
                 fcu_nextpc <= iqentry_pc[n] + iqentry_insln[n];
7522
                 fcu_pt     <= iqentry_pt[n];
7523 61 robfinch
                 fcu_brdisp <= iqentry_instr[n][6] ? {{36{iqentry_instr[n][47]}},iqentry_instr[n][47:23],iqentry_instr[n][17:16],1'b0}
7524
                                                                         : {{52{iqentry_instr[n][31]}},iqentry_instr[n][31:23],iqentry_instr[n][17:16],1'b0};
7525 60 robfinch
                 fcu_branch <= iqentry_br[n];
7526
                 fcu_call    <= IsCall(iqentry_instr[n])|iqentry_jal[n];
7527
                 fcu_jal     <= iqentry_jal[n];
7528
                 fcu_ret    <= iqentry_ret[n];
7529
                 fcu_brk  <= iqentry_brk[n];
7530
                 fcu_rti  <= iqentry_rti[n];
7531
                 fcu_pc         <= iqentry_pc[n];
7532
                 fcu_argA       <= iqentry_a1_v[n] ? iqentry_a1[n]
7533
                            : (iqentry_a1_s[n] == alu0_id) ? ralu0_bus
7534
                            : (iqentry_a1_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7535
                            : ralu1_bus;
7536
`ifdef SUPPORT_SMT
7537 61 robfinch
//                 fcu_argB     <= iqentry_rti[n] ? epc0[iqentry_thrd[n]]
7538
                 fcu_epc  <= epc0[iqentry_thrd[n]];
7539 60 robfinch
`else
7540 61 robfinch
                                                                 fcu_epc  <= epc0;
7541
//                 fcu_argB     <= iqentry_rti[n] ? epc0
7542 60 robfinch
`endif
7543 61 robfinch
                                                                        fcu_argB        <=
7544
                                          (iqentry_a2_v[n] ? iqentry_a2[n]
7545 60 robfinch
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus
7546
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus
7547
                            : ralu1_bus);
7548
                 // argB
7549
                 waitctr  <=  (iqentry_a2_v[n] ? iqentry_a2[n][47:0]
7550
                            : (iqentry_a2_s[n] == alu0_id) ? ralu0_bus[47:0]
7551
                            : (iqentry_a2_s[n] == fpu1_id && `NUM_FPU > 0) ? rfpu1_bus[47:0]
7552
                            : ralu1_bus[47:0]);
7553
                 fcu_argC       <= iqentry_a3_v[n] ? iqentry_a3[n]
7554
                            : (iqentry_a3_s[n] == alu0_id) ? ralu0_bus : ralu1_bus;
7555
                 fcu_argI       <= iqentry_a0[n];
7556
                 fcu_thrd   <= iqentry_thrd[n];
7557
                 fcu_dataready <= !IsWait(iqentry_instr[n]);
7558
                 fcu_clearbm <= `FALSE;
7559
                 fcu_ld <= TRUE;
7560
                 fcu_timeout <= 8'h00;
7561
                 iqentry_state[n] <= IQS_OUT;
7562
                 fcu_done <= `FALSE;
7563
            end
7564
        end
7565
//
7566
// MEMORY
7567
//
7568
// update the memory queues and put data out on bus if appropriate
7569
//
7570
 
7571
//
7572
// dram0, dram1, dram2 are the "state machines" that keep track
7573
// of three pipelined DRAM requests.  if any has the value "000", 
7574
// then it can accept a request (which bumps it up to the value "001"
7575
// at the end of the cycle).  once it hits the value "111" the request
7576
// is finished and the dram_bus takes the value.  if it is a store, the 
7577
// dram_bus value is not used, but the dram_v value along with the
7578
// dram_id value signals the waiting memq entry that the store is
7579
// completed and the instruction can commit.
7580
//
7581
 
7582
//      if (dram0 != `DRAMSLOT_AVAIL)   dram0 <= dram0 + 2'd1;
7583
//      if (dram1 != `DRAMSLOT_AVAIL)   dram1 <= dram1 + 2'd1;
7584
//      if (dram2 != `DRAMSLOT_AVAIL)   dram2 <= dram2 + 2'd1;
7585
 
7586
// Flip the ready status to available. Used for loads or stores.
7587
 
7588
if (dram0 == `DRAMREQ_READY)
7589
        dram0 <= `DRAMSLOT_AVAIL;
7590
if (dram1 == `DRAMREQ_READY && `NUM_MEM > 1)
7591
        dram1 <= `DRAMSLOT_AVAIL;
7592
if (dram2 == `DRAMREQ_READY && `NUM_MEM > 2)
7593
        dram2 <= `DRAMSLOT_AVAIL;
7594
 
7595
// grab requests that have finished and put them on the dram_bus
7596 61 robfinch
// If stomping on the instruction don't place the value on the argument
7597
// bus to be loaded.
7598 60 robfinch
if (dram0 == `DRAMREQ_READY && dram0_load) begin
7599 61 robfinch
        dramA_v <= !iqentry_stomp[dram0_id[`QBITS]];
7600 60 robfinch
        dramA_id <= dram0_id;
7601
        dramA_bus <= fnDatiAlign(dram0_instr,dram0_addr,rdat0);
7602
end
7603
if (dram1 == `DRAMREQ_READY && dram1_load && `NUM_MEM > 1) begin
7604 61 robfinch
        dramB_v <= !iqentry_stomp[dram1_id[`QBITS]];
7605 60 robfinch
        dramB_id <= dram1_id;
7606
        dramB_bus <= fnDatiAlign(dram1_instr,dram1_addr,rdat1);
7607
end
7608
if (dram2 == `DRAMREQ_READY && dram2_load && `NUM_MEM > 2) begin
7609 61 robfinch
        dramC_v <= !iqentry_stomp[dram2_id[`QBITS]];
7610 60 robfinch
        dramC_id <= dram2_id;
7611
        dramC_bus <= fnDatiAlign(dram2_instr,dram2_addr,rdat2);
7612
end
7613
 
7614
if (dram0 == `DRAMREQ_READY && dram0_store)
7615
        $display("m[%h] <- %h", dram0_addr, dram0_data);
7616
if (dram1 == `DRAMREQ_READY && dram1_store && `NUM_MEM > 1)
7617
        $display("m[%h] <- %h", dram1_addr, dram1_data);
7618
if (dram2 == `DRAMREQ_READY && dram2_store && `NUM_MEM > 2)
7619
        $display("m[%h] <- %h", dram2_addr, dram2_data);
7620
 
7621
//
7622
// determine if the instructions ready to issue can, in fact, issue.
7623
// "ready" means that the instruction has valid operands but has not gone yet
7624 61 robfinch
for (n = 0; n < QENTRIES; n = n + 1)
7625
if (memissue[n])
7626
        iqentry_memissue[n] <= `VAL;
7627
//iqentry_memissue <= memissue;
7628 60 robfinch
missue_count <= issue_count;
7629
 
7630
for (n = 0; n < QENTRIES; n = n + 1)
7631
        if (iqentry_v[n] && iqentry_stomp[n]) begin
7632
                iqentry_iv[n] <= `INV;
7633
                iqentry_mem[n] <= `INV;
7634
                iqentry_load[n] <= `INV;
7635
                iqentry_store[n] <= `INV;
7636
                iqentry_state[n] <= IQS_INVALID;
7637
//              iqentry_agen[n] <= `INV;
7638
//              iqentry_out[n] <= `INV;
7639
//              iqentry_done[n] <= `INV;
7640
//              iqentry_cmt[n] <= `INV;
7641
        end
7642
 
7643 61 robfinch
// A store can't be stomped on, because a store won't issue unless there are
7644
// no instructions that could change the flow of execution before it. Meaning
7645
// stomp would never be true for a store.
7646
// A load could be stomped on, but the memory access is allowed to complete
7647
// to ensure the bus acknowledge doesn't get out of sync.
7648
/*
7649
if (iqentry_stomp[dram0_id[`QBITS]])  begin
7650
        if (dram0==`DRAMSLOT_HASBUS)
7651
                wb_nack();
7652
        dram0_load <= `FALSE;
7653
        dram0_store <= `FALSE;
7654
        dram0_rmw <= `FALSE;
7655
        dram0 <= `DRAMSLOT_AVAIL;
7656
end
7657
if (iqentry_stomp[dram1_id[`QBITS]])  begin
7658
        if (dram1==`DRAMSLOT_HASBUS)
7659
                wb_nack();
7660
        dram1_load <= `FALSE;
7661
        dram1_store <= `FALSE;
7662
        dram1_rmw <= `FALSE;
7663
        dram1 <= `DRAMSLOT_AVAIL;
7664
end
7665
if (iqentry_stomp[dram2_id[`QBITS]])  begin
7666
        if (dram2==`DRAMSLOT_HASBUS)
7667
                wb_nack();
7668
        dram2_load <= `FALSE;
7669
        dram2_store <= `FALSE;
7670
        dram2_rmw <= `FALSE;
7671
        dram2 <= `DRAMSLOT_AVAIL;
7672
end
7673
*/
7674
 
7675 60 robfinch
if (last_issue0 < QENTRIES)
7676
        tDram0Issue(last_issue0);
7677
if (last_issue1 < QENTRIES)
7678
        tDram1Issue(last_issue1);
7679
if (last_issue2 < QENTRIES)
7680
        tDram2Issue(last_issue2);
7681
 
7682
 
7683
//for (n = 0; n < QENTRIES; n = n + 1)
7684
//begin
7685
//      if (!iqentry_v[n])
7686
//              iqentry_done[n] <= FALSE;
7687
//end
7688
 
7689
if (ohead[0]==heads[0])
7690
        cmt_timer <= cmt_timer + 12'd1;
7691
else
7692
        cmt_timer <= 12'd0;
7693
 
7694 61 robfinch
if (cmt_timer==12'd1000 && icstate==IDLE) begin
7695 60 robfinch
        iqentry_state[heads[0]] <= IQS_CMT;
7696
        iqentry_exc[heads[0]] <= `FLT_CMT;
7697
        cmt_timer <= 12'd0;
7698
end
7699
 
7700
//
7701
// COMMIT PHASE (dequeue only ... not register-file update)
7702
//
7703
// look at heads[0] and heads[1] and let 'em write to the register file if they are ready
7704
//
7705
//    always @(posedge clk) begin: commit_phase
7706
ohead[0] <= heads[0];
7707
ohead[1] <= heads[1];
7708
ohead[2] <= heads[2];
7709
ocommit0_v <= commit0_v;
7710
ocommit1_v <= commit1_v;
7711
ocommit2_v <= commit2_v;
7712
 
7713
oddball_commit(commit0_v, heads[0], 2'd0);
7714
if (`NUM_CMT > 1)
7715
        oddball_commit(commit1_v, heads[1], 2'd1);
7716
if (`NUM_CMT > 2)
7717
        oddball_commit(commit2_v, heads[2], 2'd2);
7718
 
7719
// Fetch and queue are limited to two instructions per cycle, so we might as
7720
// well limit retiring to two instructions max to conserve logic.
7721
//
7722
if (~|panic)
7723
  casez ({ iqentry_v[heads[0]],
7724
                iqentry_state[heads[0]] == IQS_CMT,
7725
                iqentry_v[heads[1]],
7726
                iqentry_state[heads[1]] == IQS_CMT,
7727
                iqentry_v[heads[2]],
7728
                iqentry_state[heads[2]] == IQS_CMT})
7729
 
7730
        // retire 3
7731
        6'b0?_0?_0?:
7732
                if (heads[0] != tail0 && heads[1] != tail0 && heads[2] != tail0)
7733
                        head_inc(3);
7734
                else if (heads[0] != tail0 && heads[1] != tail0)
7735
            head_inc(2);
7736
                else if (heads[0] != tail0)
7737
            head_inc(1);
7738
        6'b0?_0?_10:
7739
                if (heads[0] != tail0 && heads[1] != tail0)
7740
                        head_inc(2);
7741
                else if (heads[0] != tail0)
7742
                        head_inc(1);
7743
        6'b0?_0?_11:
7744
                if (`NUM_CMT > 2 || cmt_head2)  // and it's not an oddball?
7745
      head_inc(3);
7746
                else
7747
      head_inc(2);
7748
 
7749
        // retire 1 (wait for regfile for heads[1])
7750
        6'b0?_10_??:
7751
                head_inc(1);
7752
 
7753
        // retire 2
7754
        6'b0?_11_0?,
7755
        6'b0?_11_10:
7756
    if (`NUM_CMT > 1 || cmt_head1)
7757
      head_inc(2);
7758
    else
7759
        head_inc(1);
7760
  6'b0?_11_11:
7761
    if (`NUM_CMT > 2 || (`NUM_CMT > 1 && cmt_head2))
7762
        head_inc(3);
7763
        else if (`NUM_CMT > 1 || cmt_head1)
7764
        head_inc(2);
7765
        else
7766
                head_inc(1);
7767
  6'b10_??_??:  ;
7768
  6'b11_0?_0?:
7769
        if (heads[1] != tail0 && heads[2] != tail0)
7770
                        head_inc(3);
7771
        else if (heads[1] != tail0)
7772
                        head_inc(2);
7773
        else
7774
                        head_inc(1);
7775
  6'b11_0?_10:
7776
        if (heads[1] != tail0)
7777
                        head_inc(2);
7778
        else
7779
                        head_inc(1);
7780
  6'b11_0?_11:
7781
        if (heads[1] != tail0) begin
7782
                if (`NUM_CMT > 2 || cmt_head2)
7783
                                head_inc(3);
7784
                else
7785
                                head_inc(2);
7786
        end
7787
        else
7788
                        head_inc(1);
7789
  6'b11_10_??:
7790
                        head_inc(1);
7791
  6'b11_11_0?:
7792
        if (`NUM_CMT > 1 && heads[2] != tail0)
7793
                        head_inc(3);
7794
        else if (cmt_head1 && heads[2] != tail0)
7795
                        head_inc(3);
7796
                else if (`NUM_CMT > 1 || cmt_head1)
7797
                        head_inc(2);
7798
        else
7799
                        head_inc(1);
7800
  6'b11_11_10:
7801
                if (`NUM_CMT > 1 || cmt_head1)
7802
                        head_inc(2);
7803
        else
7804
                        head_inc(1);
7805
        6'b11_11_11:
7806
                if (`NUM_CMT > 2 || (`NUM_CMT > 1 && cmt_head2))
7807
                        head_inc(3);
7808
                else if (`NUM_CMT > 1 || cmt_head1)
7809
                        head_inc(2);
7810
                else
7811
                        head_inc(1);
7812
        default:
7813
                begin
7814
                        $display("head_inc: Uncoded case %h",{ iqentry_v[heads[0]],
7815
                                iqentry_state[heads[0]],
7816
                                iqentry_v[heads[1]],
7817
                                iqentry_state[heads[1]],
7818
                                iqentry_v[heads[2]],
7819
                                iqentry_state[heads[2]]});
7820
                        $stop;
7821
                end
7822
  endcase
7823
 
7824
 
7825
rf_source[0] <= 0;
7826
 
7827 66 robfinch
// A store will never be stomped on because they aren't issued until it's
7828
// guarenteed there will be no change of flow.
7829
// A load or other long running instruction might be stomped on by a change
7830
// of program flow. Stomped on loads already in progress can be aborted early.
7831
// In the case of an aborted load, random data is returned and any exceptions
7832
// are nullified.
7833 61 robfinch
if (dram0_load)
7834 60 robfinch
case(dram0)
7835
`DRAMSLOT_AVAIL:        ;
7836
`DRAMSLOT_BUSY:
7837 66 robfinch
        if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]])
7838 60 robfinch
                dram0 <= dram0 + !dram0_unc;
7839 66 robfinch
        else begin
7840
                dram0 <= `DRAMREQ_READY;
7841
                dram0_load <= `FALSE;
7842
                xdati[63:0] <= {4{lfsro}};
7843
        end
7844
3'd2,3'd3:
7845
        if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]])
7846 60 robfinch
                dram0 <= dram0 + 3'd1;
7847 66 robfinch
        else begin
7848
                dram0 <= `DRAMREQ_READY;
7849
                dram0_load <= `FALSE;
7850
                xdati[63:0] <= {4{lfsro}};
7851
        end
7852 60 robfinch
3'd4:
7853 66 robfinch
        if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]]) begin
7854 60 robfinch
                if (dhit0)
7855
                        dram0 <= `DRAMREQ_READY;
7856
                else
7857
                        dram0 <= `DRAMSLOT_REQBUS;
7858 66 robfinch
        end
7859
        else begin
7860
                dram0 <= `DRAMREQ_READY;
7861
                dram0_load <= `FALSE;
7862
                xdati[63:0] <= {4{lfsro}};
7863
        end
7864
`DRAMSLOT_REQBUS:
7865
        if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]])
7866
                ;
7867
        else begin
7868
                dram0 <= `DRAMREQ_READY;
7869
                dram0_load <= `FALSE;
7870
                xdati[63:0] <= {4{lfsro}};
7871
        end
7872
`DRAMSLOT_HASBUS:
7873
        if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]])
7874
                ;
7875
        else begin
7876
                dram0 <= `DRAMREQ_READY;
7877
                dram0_load <= `FALSE;
7878
                xdati[63:0] <= {4{lfsro}};
7879
        end
7880 60 robfinch
`DRAMREQ_READY:         dram0 <= `DRAMSLOT_AVAIL;
7881
endcase
7882
 
7883 61 robfinch
if (dram1_load && `NUM_MEM > 1)
7884 60 robfinch
case(dram1)
7885
`DRAMSLOT_AVAIL:        ;
7886
`DRAMSLOT_BUSY:
7887
        dram1 <= dram1 + !dram1_unc;
7888
3'd2:
7889
        dram1 <= dram1 + 3'd1;
7890
3'd3:
7891
        dram1 <= dram1 + 3'd1;
7892
3'd4:
7893 61 robfinch
//      if (iqentry_v[dram1_id[`QBITS]] && !iqentry_stomp[dram1_id[`QBITS]]) begin
7894 60 robfinch
                if (dhit1)
7895
                        dram1 <= `DRAMREQ_READY;
7896
                else
7897
                        dram1 <= `DRAMSLOT_REQBUS;
7898 61 robfinch
//      end
7899
/*      else begin
7900 60 robfinch
                dram1 <= `DRAMSLOT_AVAIL;
7901
                dram1_load <= `FALSE;
7902 61 robfinch
        end*/
7903 60 robfinch
`DRAMSLOT_REQBUS:       ;
7904
`DRAMSLOT_HASBUS:       ;
7905
`DRAMREQ_READY:         dram1 <= `DRAMSLOT_AVAIL;
7906
endcase
7907
 
7908 61 robfinch
if (dram2_load && `NUM_MEM > 2)
7909 60 robfinch
case(dram2)
7910
`DRAMSLOT_AVAIL:        ;
7911
`DRAMSLOT_BUSY:
7912
        dram2 <= dram2 + !dram2_unc;
7913
3'd2:
7914
        dram2 <= dram2 + 3'd1;
7915
3'd3:
7916
        dram2 <= dram2 + 3'd1;
7917
3'd4:
7918
                if (dhit2)
7919
                        dram2 <= `DRAMREQ_READY;
7920
                else
7921
                        dram2 <= `DRAMSLOT_REQBUS;
7922
`DRAMSLOT_REQBUS:       ;
7923
`DRAMSLOT_HASBUS:       ;
7924
`DRAMREQ_READY:         dram2 <= `DRAMSLOT_AVAIL;
7925
endcase
7926
 
7927
 
7928
// Bus Interface Unit (BIU)
7929
// Interfaces to the external bus which is WISHBONE compatible.
7930
// Stores take precedence over other operations.
7931
// Next data cache read misses are serviced.
7932
// Uncached data reads are serviced.
7933
// Finally L2 instruction cache misses are serviced.//
7934
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
7935
//
7936
`ifndef HAS_WB
7937
if (mem1_available && dram0 == `DRAMSLOT_BUSY && dram0_store) begin
7938
        if ((alu0_v && (dram0_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram0_id[`QBITS] == alu1_id[`QBITS])))      panic <= `PANIC_MEMORYRACE;
7939
//      iqentry_done[ dram0_id[`QBITS] ] <= `VAL;
7940
//      iqentry_out[ dram0_id[`QBITS] ] <= `INV;
7941
        iqentry_state[ dram0_id[`QBITS] ] <= IQS_DONE;
7942
end
7943
if (mem2_available && `NUM_MEM > 1 && dram1 == `DRAMSLOT_BUSY && dram1_store) begin
7944
        if ((alu0_v && (dram1_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram1_id[`QBITS] == alu1_id[`QBITS])))      panic <= `PANIC_MEMORYRACE;
7945
        iqentry_state[ dram1_id[`QBITS] ] <= IQS_DONE;
7946
end
7947
if (mem3_available && `NUM_MEM > 2 && dram2 == `DRAMSLOT_BUSY && dram2_store) begin
7948
        if ((alu0_v && (dram2_id[`QBITS] == alu0_id[`QBITS])) || (alu1_v && (dram2_id[`QBITS] == alu1_id[`QBITS])))      panic <= `PANIC_MEMORYRACE;
7949
        iqentry_state[ dram2_id[`QBITS] ] <= IQS_DONE;
7950
end
7951
`endif
7952
 
7953
`ifdef HAS_WB
7954 61 robfinch
  if (dram0==`DRAMSLOT_BUSY && dram0_store) begin
7955 60 robfinch
                if (wbptr<`WB_DEPTH-1) begin
7956
                        dram0 <= `DRAMSLOT_AVAIL;
7957
                        dram0_instr[`INSTRUCTION_OP] <= `NOP;
7958
                        wb_update(
7959
                                dram0_id,
7960
                                `FALSE,
7961
                                fnSelect(dram0_instr,dram0_addr),
7962
                                dram0_ol,
7963
                                dram0_addr,
7964 66 robfinch
                                fnDato(dram0_instr,dram0_data),
7965
                                wbptr
7966 60 robfinch
                        );
7967 66 robfinch
                        wbptr <= wbptr + 2'd1;
7968 60 robfinch
                        iqentry_state[ dram0_id[`QBITS] ] <= IQS_DONE;
7969
                end
7970
  end
7971 61 robfinch
  else if (dram1==`DRAMSLOT_BUSY && dram1_store && `NUM_MEM > 1) begin
7972 60 robfinch
                if (wbptr<`WB_DEPTH-1) begin
7973
                        dram1 <= `DRAMSLOT_AVAIL;
7974
      dram1_instr[`INSTRUCTION_OP] <= `NOP;
7975
                        wb_update(
7976
                                dram1_id,
7977
                                `FALSE,
7978
                                fnSelect(dram1_instr,dram1_addr),
7979
                                dram1_ol,
7980
                                dram1_addr,
7981 66 robfinch
                                fnDato(dram1_instr,dram1_data),
7982
                                wbptr
7983 60 robfinch
                        );
7984 66 robfinch
                        wbptr <= wbptr + 2'd1;
7985 60 robfinch
                        iqentry_state[ dram1_id[`QBITS] ] <= IQS_DONE;
7986
                end
7987
  end
7988 61 robfinch
  else if (dram2==`DRAMSLOT_BUSY && dram2_store && `NUM_MEM > 2) begin
7989 60 robfinch
                if (wbptr<`WB_DEPTH-1) begin
7990
                        dram2 <= `DRAMSLOT_AVAIL;
7991
      dram2_instr[`INSTRUCTION_OP] <= `NOP;
7992
                        wb_update(
7993
                                dram2_id,
7994
                                `FALSE,
7995
                                fnSelect(dram2_instr,dram2_addr),
7996
                                dram2_ol,
7997
                                dram2_addr,
7998 66 robfinch
                                fnDato(dram2_instr,dram2_data),
7999
                                wbptr
8000 60 robfinch
                        );
8001 66 robfinch
                        wbptr <= wbptr + 2'd1;
8002 60 robfinch
                        iqentry_state[ dram2_id[`QBITS] ] <= IQS_DONE;
8003
                end
8004
  end
8005
`endif
8006
 
8007
case(bstate)
8008
BIDLE:
8009
        begin
8010
                isCAS <= FALSE;
8011
                isAMO <= FALSE;
8012
                isInc <= FALSE;
8013
                isSpt <= FALSE;
8014
                isRMW <= FALSE;
8015
                rdvq <= 1'b0;
8016
                errq <= 1'b0;
8017
                exvq <= 1'b0;
8018
                bwhich <= 2'b00;
8019
                preload <= FALSE;
8020
`ifdef HAS_WB
8021
                if (wb_v[0] & wb_en & ~acki & ~cyc) begin
8022
                        cyc <= `HIGH;
8023
                        stb_o <= `HIGH;
8024
                        we <= `HIGH;
8025
                        sel_o <= wb_sel[0];
8026
                        vadr <= wb_addr[0];
8027
                        dat_o <= wb_data[0];
8028 66 robfinch
                        dcbuf <= {4{wb_data[0]}};
8029
                        dcsel <= wb_sel[0] << {wb_addr[0][4:3],3'b0};
8030 60 robfinch
                        ol_o  <= wb_ol[0];
8031
                        wbo_id <= wb_id[0];
8032
        isStore <= TRUE;
8033 66 robfinch
                        bstate <= wb_rmw[0] ? B_RMWAck : B_StoreAck;
8034 60 robfinch
                        wb_v[0] <= `INV;
8035
                end
8036
                if (wb_v[0]==`INV && !writing_wb) begin
8037
                        for (j = 1; j < `WB_DEPTH; j = j + 1) begin
8038
                wb_v[j-1] <= wb_v[j];
8039
                wb_id[j-1] <= wb_id[j];
8040
                wb_rmw[j-1] <= wb_rmw[j];
8041
                wb_sel[j-1] <= wb_sel[j];
8042
                wb_addr[j-1] <= wb_addr[j];
8043
                wb_data[j-1] <= wb_data[j];
8044
                wb_ol[j-1] <= wb_ol[j];
8045
                if (wbptr > 2'd0)
8046
                        wbptr <= wbptr - 2'd1;
8047
        end
8048
        wb_v[`WB_DEPTH-1] <= `INV;
8049
        wb_rmw[`WB_DEPTH-1] <= `FALSE;
8050
    end
8051
 
8052
`endif
8053 66 robfinch
      if (~|wb_v && dram0==`DRAMSLOT_BUSY && dram0_rmw
8054
        && !iqentry_stomp[dram0_id[`QBITS]]) begin
8055 60 robfinch
`ifdef SUPPORT_DBG
8056
            if (dbg_smatch0|dbg_lmatch0) begin
8057
                 dramA_v <= `TRUE;
8058
                 dramA_id <= dram0_id;
8059
                 dramA_bus <= 64'h0;
8060 61 robfinch
                 iqentry_exc[dram0_id[`QBITS]] <= `FLT_DBG;
8061 60 robfinch
                 dram0 <= `DRAMSLOT_AVAIL;
8062
            end
8063
            else
8064
`endif
8065
            if (!acki) begin
8066
                 isRMW <= dram0_rmw;
8067
                 isCAS <= IsCAS(dram0_instr);
8068
                 isAMO <= IsAMO(dram0_instr);
8069
                 isInc <= IsInc(dram0_instr);
8070
                 casid <= dram0_id;
8071
                 bwhich <= 2'b00;
8072
                 dram0 <= `DRAMSLOT_HASBUS;
8073
                 cyc <= `HIGH;
8074
                 stb_o <= `HIGH;
8075
                 sel_o <= fnSelect(dram0_instr,dram0_addr);
8076 66 robfinch
                 dcbuf <= {4{fnDato(dram0_instr,dram0_data)}};
8077
                 dcsel <= fnSelect(dram0_instr,dram0_addr) << {dram0_addr[4:3],3'b0};
8078 60 robfinch
                 vadr <= dram0_addr;
8079
                 dat_o <= fnDato(dram0_instr,dram0_data);
8080
                 ol_o  <= dram0_ol;
8081 66 robfinch
                 bstate <= B_RMWAck;
8082 60 robfinch
            end
8083
        end
8084 66 robfinch
        else if (~|wb_v && dram1==`DRAMSLOT_BUSY && dram1_rmw && `NUM_MEM > 1
8085
                && !iqentry_stomp[dram1_id[`QBITS]]) begin
8086 60 robfinch
`ifdef SUPPORT_DBG
8087
            if (dbg_smatch1|dbg_lmatch1) begin
8088
                 dramB_v <= `TRUE;
8089
                 dramB_id <= dram1_id;
8090
                 dramB_bus <= 64'h0;
8091 61 robfinch
                 iqentry_exc[dram1_id[`QBITS]] <= `FLT_DBG;
8092 60 robfinch
                 dram1 <= `DRAMSLOT_AVAIL;
8093
            end
8094
            else
8095
`endif
8096
            if (!acki) begin
8097
                 isRMW <= dram1_rmw;
8098
                 isCAS <= IsCAS(dram1_instr);
8099
                 isAMO <= IsAMO(dram1_instr);
8100
                 isInc <= IsInc(dram1_instr);
8101
                 casid <= dram1_id;
8102
                 bwhich <= 2'b01;
8103
                 dram1 <= `DRAMSLOT_HASBUS;
8104
                 cyc <= `HIGH;
8105
                 stb_o <= `HIGH;
8106
                 sel_o <= fnSelect(dram1_instr,dram1_addr);
8107
                 vadr <= dram1_addr;
8108
                 dat_o <= fnDato(dram1_instr,dram1_data);
8109
                 ol_o  <= dram1_ol;
8110 66 robfinch
                 dcbuf <= {4{fnDato(dram1_instr,dram1_data)}};
8111
                 dcsel <= fnSelect(dram1_instr,dram1_addr) << {dram1_addr[4:3],3'b0};
8112
                 bstate <= B_RMWAck;
8113 60 robfinch
            end
8114
        end
8115 66 robfinch
        else if (~|wb_v && dram2==`DRAMSLOT_BUSY && dram2_rmw && `NUM_MEM > 2
8116
                && !iqentry_stomp[dram2_id[`QBITS]]) begin
8117 60 robfinch
`ifdef SUPPORT_DBG
8118
            if (dbg_smatch2|dbg_lmatch2) begin
8119
                 dramC_v <= `TRUE;
8120
                 dramC_id <= dram2_id;
8121
                 dramC_bus <= 64'h0;
8122 61 robfinch
                 iqentry_exc[dram2_id[`QBITS]] <= `FLT_DBG;
8123 60 robfinch
                 dram2 <= `DRAMSLOT_AVAIL;
8124
            end
8125
            else
8126
`endif
8127
            if (!acki) begin
8128
                 isRMW <= dram2_rmw;
8129
                 isCAS <= IsCAS(dram2_instr);
8130
                 isAMO <= IsAMO(dram2_instr);
8131
                 isInc <= IsInc(dram2_instr);
8132
                 casid <= dram2_id;
8133
                 bwhich <= 2'b10;
8134
                 dram2 <= `DRAMSLOT_HASBUS;
8135
                 cyc <= `HIGH;
8136
                 stb_o <= `HIGH;
8137
                 sel_o <= fnSelect(dram2_instr,dram2_addr);
8138
                 vadr <= dram2_addr;
8139
                 dat_o <= fnDato(dram2_instr,dram2_data);
8140
                 ol_o  <= dram2_ol;
8141 66 robfinch
                 dcbuf <= {4{fnDato(dram2_instr,dram2_data)}};
8142
                 dcsel <= fnSelect(dram2_instr,dram2_addr) << {dram2_addr[4:3],3'b0};
8143
                 bstate <= B_RMWAck;
8144 60 robfinch
            end
8145
        end
8146
`ifndef HAS_WB
8147
                                // Check write buffer enable ?
8148 61 robfinch
        else if (dram0==`DRAMSLOT_BUSY && dram0_store) begin
8149 60 robfinch
`ifdef SUPPORT_DBG
8150
            if (dbg_smatch0) begin
8151
                 dramA_v <= `TRUE;
8152
                 dramA_id <= dram0_id;
8153
                 dramA_bus <= 64'h0;
8154 61 robfinch
                 iqentry_exc[dram0_id[`QBITS]] <= `FLT_DBG;
8155 60 robfinch
                 dram0 <= `DRAMSLOT_AVAIL;
8156
            end
8157
            else
8158
`endif
8159
            begin
8160
                                                        bwhich <= 2'b00;
8161
                                                        if (!acki) begin
8162
                                                                dram0 <= `DRAMSLOT_HASBUS;
8163
                                                                dram0_instr[`INSTRUCTION_OP] <= `NOP;
8164
                cyc <= `HIGH;
8165
                stb_o <= `HIGH;
8166 61 robfinch
                we <= `HIGH;
8167 60 robfinch
                sel_o <= fnSelect(dram0_instr,dram0_addr);
8168
                vadr <= dram0_addr;
8169
                dat_o <= fnDato(dram0_instr,dram0_data);
8170
                ol_o  <= dram0_ol;
8171
                                        isStore <= TRUE;
8172
                bstate <= B_StoreAck;
8173 66 robfinch
                 dcbuf <= {4{fnDato(dram0_instr,dram0_data)}};
8174
                 dcsel <= fnSelect(dram0_instr,dram0_addr) << {dram0_addr[4:3],3'b0};
8175 60 robfinch
              end
8176
//                 cr_o <= IsSWC(dram0_instr);
8177
            end
8178
        end
8179 61 robfinch
        else if (dram1==`DRAMSLOT_BUSY && dram1_store && `NUM_MEM > 1) begin
8180 60 robfinch
`ifdef SUPPORT_DBG
8181
            if (dbg_smatch1) begin
8182
                 dramB_v <= `TRUE;
8183
                 dramB_id <= dram1_id;
8184
                 dramB_bus <= 64'h0;
8185 61 robfinch
                 iqentry_exc[dram1_id[`QBITS]] <= `FLT_DBG;
8186 60 robfinch
                 dram1 <= `DRAMSLOT_AVAIL;
8187
            end
8188
            else
8189
`endif
8190
            begin
8191
                 bwhich <= 2'b01;
8192
                                                        if (!acki) begin
8193
                dram1 <= `DRAMSLOT_HASBUS;
8194
                dram1_instr[`INSTRUCTION_OP] <= `NOP;
8195
                cyc <= `HIGH;
8196
                stb_o <= `HIGH;
8197 61 robfinch
                we <= `HIGH;
8198 60 robfinch
                sel_o <= fnSelect(dram1_instr,dram1_addr);
8199
                vadr <= dram1_addr;
8200
                dat_o <= fnDato(dram1_instr,dram1_data);
8201
                ol_o  <= dram1_ol;
8202
                                        isStore <= TRUE;
8203 66 robfinch
                 dcbuf <= {4{fnDato(dram1_instr,dram1_data)}};
8204
                 dcsel <= fnSelect(dram1_instr,dram1_addr) << {dram1_addr[4:3],3'b0};
8205 60 robfinch
                bstate <= B_StoreAck;
8206
              end
8207
//                 cr_o <= IsSWC(dram0_instr);
8208
            end
8209
        end
8210 61 robfinch
        else if (dram2==`DRAMSLOT_BUSY && dram2_store && `NUM_MEM > 2) begin
8211 60 robfinch
`ifdef SUPPORT_DBG
8212
            if (dbg_smatch2) begin
8213
                 dramC_v <= `TRUE;
8214
                 dramC_id <= dram2_id;
8215
                 dramC_bus <= 64'h0;
8216 61 robfinch
                 iqentry_exc[dram2_id[`QBITS]] <= `FLT_DBG;
8217 60 robfinch
                 dram2 <= `DRAMSLOT_AVAIL;
8218
            end
8219
            else
8220
`endif
8221
            begin
8222
                 bwhich <= 2'b10;
8223
                                                        if (!acki) begin
8224
                dram2 <= `DRAMSLOT_HASBUS;
8225
                dram2_instr[`INSTRUCTION_OP] <= `NOP;
8226
                cyc <= `HIGH;
8227
                stb_o <= `HIGH;
8228 61 robfinch
                we <= `HIGH;
8229 60 robfinch
                sel_o <= fnSelect(dram2_instr,dram2_addr);
8230
                vadr <= dram2_addr;
8231
                dat_o <= fnDato(dram2_instr,dram2_data);
8232
                ol_o  <= dram2_ol;
8233
                                        isStore <= TRUE;
8234 66 robfinch
                 dcbuf <= {4{fnDato(dram2_instr,dram2_data)}};
8235
                 dcsel <= fnSelect(dram2_instr,dram2_addr) << {dram2_addr[4:3],3'b0};
8236 60 robfinch
                bstate <= B_StoreAck;
8237
              end
8238
//                 cr_o <= IsSWC(dram0_instr);
8239
            end
8240
        end
8241
`endif
8242
        // Check for read misses on the data cache
8243 66 robfinch
        else if (~|wb_v && !dram0_unc && dram0==`DRAMSLOT_REQBUS && dram0_load
8244
                && !iqentry_stomp[dram0_id[`QBITS]]) begin
8245 60 robfinch
`ifdef SUPPORT_DBG
8246
            if (dbg_lmatch0) begin
8247
               dramA_v <= `TRUE;
8248
               dramA_id <= dram0_id;
8249
               dramA_bus <= 64'h0;
8250 61 robfinch
               iqentry_exc[dram0_id[`QBITS]] <= `FLT_DBG;
8251 60 robfinch
               dram0 <= `DRAMSLOT_AVAIL;
8252
            end
8253
            else
8254
`endif
8255
            begin
8256
               dram0 <= `DRAMSLOT_HASBUS;
8257
               bwhich <= 2'b00;
8258
               preload <= dram0_preload;
8259
               bstate <= B_DCacheLoadStart;
8260
            end
8261
        end
8262 66 robfinch
        else if (~|wb_v && !dram1_unc && dram1==`DRAMSLOT_REQBUS && dram1_load && `NUM_MEM > 1
8263
                && !iqentry_stomp[dram1_id[`QBITS]]) begin
8264 60 robfinch
`ifdef SUPPORT_DBG
8265
            if (dbg_lmatch1) begin
8266
               dramB_v <= `TRUE;
8267
               dramB_id <= dram1_id;
8268
               dramB_bus <= 64'h0;
8269 61 robfinch
               iqentry_exc[dram1_id[`QBITS]] <= `FLT_DBG;
8270 60 robfinch
               dram1 <= `DRAMSLOT_AVAIL;
8271
            end
8272
            else
8273
`endif
8274
            begin
8275
               dram1 <= `DRAMSLOT_HASBUS;
8276
               bwhich <= 2'b01;
8277
               preload <= dram1_preload;
8278
               bstate <= B_DCacheLoadStart;
8279
            end
8280
        end
8281 66 robfinch
        else if (~|wb_v && !dram2_unc && dram2==`DRAMSLOT_REQBUS && dram2_load && `NUM_MEM > 2
8282
                && !iqentry_stomp[dram2_id[`QBITS]]) begin
8283 60 robfinch
`ifdef SUPPORT_DBG
8284
            if (dbg_lmatch2) begin
8285
               dramC_v <= `TRUE;
8286
               dramC_id <= dram2_id;
8287
               dramC_bus <= 64'h0;
8288 61 robfinch
               iqentry_exc[dram2_id[`QBITS]] <= `FLT_DBG;
8289 60 robfinch
               dram2 <= `DRAMSLOT_AVAIL;
8290
            end
8291
            else
8292
`endif
8293
            begin
8294
               dram2 <= `DRAMSLOT_HASBUS;
8295
               preload <= dram2_preload;
8296
               bwhich <= 2'b10;
8297
               bstate <= B_DCacheLoadStart;
8298
            end
8299
        end
8300 66 robfinch
        else if (~|wb_v && dram0_unc && dram0==`DRAMSLOT_BUSY && dram0_load
8301
                && !iqentry_stomp[dram0_id[`QBITS]]) begin
8302 60 robfinch
`ifdef SUPPORT_DBG
8303
            if (dbg_lmatch0) begin
8304
               dramA_v <= `TRUE;
8305
               dramA_id <= dram0_id;
8306
               dramA_bus <= 64'h0;
8307 61 robfinch
               iqentry_exc[dram0_id[`QBITS]] <= `FLT_DBG;
8308 60 robfinch
               dram0 <= `DRAMSLOT_AVAIL;
8309
            end
8310
            else
8311
`endif
8312
            if (!acki) begin
8313
               bwhich <= 2'b00;
8314 66 robfinch
               dram0 <= `DRAMSLOT_HASBUS;
8315 60 robfinch
               cyc <= `HIGH;
8316
               stb_o <= `HIGH;
8317
               sel_o <= fnSelect(dram0_instr,dram0_addr);
8318
               vadr <= {dram0_addr[AMSB:3],3'b0};
8319
               sr_o <=  IsLWR(dram0_instr);
8320
               ol_o  <= dram0_ol;
8321 61 robfinch
               dccnt <= 2'd0;
8322 60 robfinch
               bstate <= B_DLoadAck;
8323
            end
8324
        end
8325 66 robfinch
        else if (~|wb_v && dram1_unc && dram1==`DRAMSLOT_BUSY && dram1_load && `NUM_MEM > 1
8326
                && !iqentry_stomp[dram1_id[`QBITS]]) begin
8327 60 robfinch
`ifdef SUPPORT_DBG
8328
            if (dbg_lmatch1) begin
8329
               dramB_v <= `TRUE;
8330
               dramB_id <= dram1_id;
8331
               dramB_bus <= 64'h0;
8332 61 robfinch
               iqentry_exc[dram1_id[`QBITS]] <= `FLT_DBG;
8333 60 robfinch
               dram1 <= `DRAMSLOT_AVAIL;
8334
            end
8335
            else
8336
`endif
8337
            if (!acki) begin
8338
               bwhich <= 2'b01;
8339 66 robfinch
               dram1 <= `DRAMSLOT_HASBUS;
8340 60 robfinch
               cyc <= `HIGH;
8341
               stb_o <= `HIGH;
8342
               sel_o <= fnSelect(dram1_instr,dram1_addr);
8343
               vadr <= {dram1_addr[AMSB:3],3'b0};
8344
               sr_o <=  IsLWR(dram1_instr);
8345
               ol_o  <= dram1_ol;
8346 61 robfinch
               dccnt <= 2'd0;
8347 60 robfinch
               bstate <= B_DLoadAck;
8348
            end
8349
        end
8350 66 robfinch
        else if (~|wb_v && dram2_unc && dram2==`DRAMSLOT_BUSY && dram2_load && `NUM_MEM > 2
8351
                && !iqentry_stomp[dram2_id[`QBITS]]) begin
8352 60 robfinch
`ifdef SUPPORT_DBG
8353
            if (dbg_lmatch2) begin
8354
               dramC_v <= `TRUE;
8355
               dramC_id <= dram2_id;
8356
               dramC_bus <= 64'h0;
8357 61 robfinch
               iqentry_exc[dram2_id[`QBITS]] <= `FLT_DBG;
8358 60 robfinch
               dram2 <= 2'd0;
8359
            end
8360
            else
8361
`endif
8362
            if (!acki) begin
8363
               bwhich <= 2'b10;
8364 66 robfinch
               dram2 <= `DRAMSLOT_HASBUS;
8365 60 robfinch
               cyc <= `HIGH;
8366
               stb_o <= `HIGH;
8367
               sel_o <= fnSelect(dram2_instr,dram2_addr);
8368
               vadr <= {dram2_addr[AMSB:3],3'b0};
8369
               sr_o <=  IsLWR(dram2_instr);
8370
               ol_o  <= dram2_ol;
8371 61 robfinch
               dccnt <= 2'd0;
8372 60 robfinch
               bstate <= B_DLoadAck;
8373
            end
8374
        end
8375
        // Check for L2 cache miss
8376 61 robfinch
        else if (~|wb_v && !ihitL2 && !acki)
8377
        begin
8378 66 robfinch
                bstate <= B_WaitIC;
8379
                /*
8380 60 robfinch
           cti_o <= 3'b001;
8381
           bte_o <= 2'b00;//2'b01;      // 4 beat burst wrap
8382
           cyc <= `HIGH;
8383
           stb_o <= `HIGH;
8384
           sel_o <= 8'hFF;
8385
           icl_o <= `HIGH;
8386
           iccnt <= 3'd0;
8387 61 robfinch
           icack <= 1'b0;
8388 60 robfinch
//            adr_o <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
8389
//            L2_adr <= icwhich ? {pc0[31:5],5'b0} : {pc1[31:5],5'b0};
8390 66 robfinch
           vadr <= {L1_adr[AMSB:5],5'h0};
8391 61 robfinch
`ifdef SUPPORT_SMT
8392
`else
8393
           ol_o  <= ol;//???
8394
`endif
8395 66 robfinch
           L2_adr <= {L1_adr[AMSB:5],5'h0};
8396 60 robfinch
           L2_xsel <= 1'b0;
8397 66 robfinch
           selL2 <= TRUE;
8398 60 robfinch
           bstate <= B_ICacheAck;
8399 66 robfinch
           */
8400 60 robfinch
        end
8401
    end
8402 66 robfinch
B_WaitIC:
8403
        begin
8404
                cti_o <= icti;
8405
                bte_o <= ibte;
8406
                cyc <= icyc;
8407
                stb_o <= istb;
8408
                sel_o <= isel;
8409
                vadr <= iadr;
8410
                we <= 1'b0;
8411
                if (L2_nxt)
8412
                        bstate <= BIDLE;
8413
        end
8414 60 robfinch
 
8415
// Terminal state for a store operation.
8416
// Note that if only a single memory channel is selected, bwhich will be a
8417
// constant 0. This should cause the extra code to be removed.
8418
B_StoreAck:
8419
        begin
8420
                StoreAck1 <= `TRUE;
8421
                isStore <= `TRUE;
8422
        if (acki|err_i|tlb_miss|wrv_i) begin
8423
                wb_nack();
8424
                cr_o <= 1'b0;
8425
    // This isn't a good way of doing things; the state should be propagated
8426
    // to the commit stage, however since this is a store we know there will
8427
    // be no change of program flow. So the reservation status bit is set
8428
    // here. The author wanted to avoid the complexity of propagating the
8429
    // input signal to the commit stage. It does mean that the SWC
8430
    // instruction should be surrounded by SYNC's.
8431
    if (cr_o)
8432
                        sema[0] <= rbi_i;
8433
`ifdef HAS_WB
8434
                for (n = 0; n < QENTRIES; n = n + 1) begin
8435
                        if (wbo_id[n]) begin
8436
        iqentry_exc[n] <= tlb_miss ? `FLT_TLB : wrv_i ? `FLT_DWF : err_i ? `FLT_IBE : `FLT_NONE;
8437
        if (err_i|wrv_i) begin
8438
                wb_v <= 1'b0;                   // Invalidate write buffer if there is a problem with the store
8439
                wb_en <= `FALSE;        // and disable write buffer
8440
        end
8441 61 robfinch
        iqentry_state[n] <= IQS_CMT;
8442 60 robfinch
                                iqentry_aq[n] <= `INV;
8443
                        end
8444
                end
8445
`else
8446
    case(bwhich)
8447
    2'd0:   begin
8448
                dram0 <= `DRAMSLOT_AVAIL;
8449
                iqentry_exc[dram0_id[`QBITS]] <= (wrv_i|err_i) ? `FLT_DWF : `FLT_NONE;
8450
                                iqentry_state[dram0_id[`QBITS]] <= IQS_CMT;
8451
                                                        iqentry_aq[ dram0_id[`QBITS] ] <= `INV;
8452
                //iqentry_out[ dram0_id[`QBITS] ] <= `INV;
8453
            end
8454
    2'd1:   if (`NUM_MEM > 1) begin
8455
                dram1 <= `DRAMSLOT_AVAIL;
8456
                iqentry_exc[dram1_id[`QBITS]] <= (wrv_i|err_i) ? `FLT_DWF : `FLT_NONE;
8457
                                iqentry_state[dram1_id[`QBITS]] <= IQS_CMT;
8458
                                                        iqentry_aq[ dram1_id[`QBITS] ] <= `INV;
8459
                //iqentry_out[ dram1_id[`QBITS] ] <= `INV;
8460
            end
8461
    2'd2:   if (`NUM_MEM > 2) begin
8462
                dram2 <= `DRAMSLOT_AVAIL;
8463
                iqentry_exc[dram2_id[`QBITS]] <= (wrv_i|err_i) ? `FLT_DWF : `FLT_NONE;
8464
                                iqentry_state[dram2_id[`QBITS]] <= IQS_CMT;
8465
                                                        iqentry_aq[ dram2_id[`QBITS] ] <= `INV;
8466
                //iqentry_out[ dram2_id[`QBITS] ] <= `INV;
8467
            end
8468
    default:    ;
8469
    endcase
8470
`endif
8471 61 robfinch
                bstate <= B_LSNAck;
8472 60 robfinch
  end
8473
        end
8474
 
8475
B_DCacheLoadStart:
8476
  if (~acki & ~cyc) begin       // check for idle bus - it should be
8477
    dccnt <= 2'd0;
8478
    bstate <= B_DCacheLoadAck;
8479
                cti_o <= 3'b001;        // constant address burst
8480
                bte_o <= 2'b00;         // linear burst, non-wrapping
8481
                cyc <= `HIGH;
8482
                stb_o <= `HIGH;
8483
                // Select should be selecting all byte lanes for a cache load
8484
    sel_o <= 8'hFF;
8485
                // bwhich should always be one of the three channels.
8486 66 robfinch
                // If single bit upset, continue to select channel zero when
8487
                // there's only one available.
8488 60 robfinch
    case(bwhich)
8489
    2'd1:   if (`NUM_MEM > 1) begin
8490
             vadr <= {dram1_addr[AMSB:5],5'b0};
8491
             ol_o  <= dram1_ol;
8492 66 robfinch
                if (iqentry_stomp[dram1_id[`QBITS]]) begin
8493
                        wb_nack();
8494
                        dram1 <= `DRAMREQ_READY;
8495
                        bstate <= BIDLE;
8496
                        end
8497 60 robfinch
            end
8498 66 robfinch
            else begin
8499
             vadr <= {dram0_addr[AMSB:5],5'b0};
8500
             ol_o  <= dram0_ol;
8501
                if (iqentry_stomp[dram0_id[`QBITS]]) begin
8502
                        wb_nack();
8503
                        dram0 <= `DRAMREQ_READY;
8504
                        bstate <= BIDLE;
8505
                        end
8506
            end
8507 60 robfinch
    2'd2:   if (`NUM_MEM > 2) begin
8508
             vadr <= {dram2_addr[AMSB:5],5'b0};
8509
             ol_o  <= dram2_ol;
8510 66 robfinch
                if (iqentry_stomp[dram2_id[`QBITS]]) begin
8511
                        wb_nack();
8512
                        dram2 <= `DRAMREQ_READY;
8513
                        bstate <= BIDLE;
8514
                        end
8515 60 robfinch
            end
8516 66 robfinch
                                                else if (`NUM_MEM > 1) begin
8517
             vadr <= {dram1_addr[AMSB:5],5'b0};
8518
             ol_o  <= dram1_ol;
8519
                if (iqentry_stomp[dram1_id[`QBITS]]) begin
8520
                        wb_nack();
8521
                        dram1 <= `DRAMREQ_READY;
8522
                        bstate <= BIDLE;
8523
                        end
8524
            end
8525
            else begin
8526
             vadr <= {dram0_addr[AMSB:5],5'b0};
8527
             ol_o  <= dram0_ol;
8528
                if (iqentry_stomp[dram0_id[`QBITS]]) begin
8529
                        wb_nack();
8530
                        dram0 <= `DRAMREQ_READY;
8531
                        bstate <= BIDLE;
8532
                        end
8533
            end
8534 60 robfinch
    default:
8535
      begin
8536 66 robfinch
                                vadr <= {dram0_addr[AMSB:5],5'b0};
8537
                                ol_o  <= dram0_ol;
8538
        if (iqentry_stomp[dram0_id[`QBITS]]) begin
8539
                wb_nack();
8540
                dram0 <= `DRAMREQ_READY;
8541
                bstate <= BIDLE;
8542
                end
8543 60 robfinch
        end
8544
    endcase
8545
  end
8546
 
8547
// Data cache load terminal state
8548
B_DCacheLoadAck:
8549 66 robfinch
        begin
8550
                dcsel <= 32'hFFFFFFFF;
8551
          if (acki|err_i|tlb_miss|rdv_i) begin
8552
                if (!bok_i) begin
8553
                        stb_o <= `LOW;
8554
                        bstate <= B_DCacheLoadStb;
8555
                end
8556
            errq <= errq | err_i;
8557
            rdvq <= rdvq | rdv_i;
8558
            if (!preload)       // A preload instruction ignores any error
8559
            if (dccnt==3'd3)
8560
                    case(bwhich)
8561
                    2'd0:
8562
                        if (iqentry_stomp[dram0_id[`QBITS]])
8563
                                iqentry_exc[dram0_id[`QBITS]] <= `FLT_NONE;
8564
                        else
8565
                                iqentry_exc[dram0_id[`QBITS]] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DBE : rdv_i ? `FLT_DRF : `FLT_NONE;
8566
                    2'd1:
8567
                        if (iqentry_stomp[dram1_id[`QBITS]])
8568
                                iqentry_exc[dram1_id[`QBITS]] <= `FLT_NONE;
8569
                        else
8570
                                                iqentry_exc[dram1_id[`QBITS]] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DBE : rdv_i ? `FLT_DRF : `FLT_NONE;
8571
                    2'd2:
8572
                        if (iqentry_stomp[dram2_id[`QBITS]])
8573
                                iqentry_exc[dram2_id[`QBITS]] <= `FLT_NONE;
8574
                        else
8575
                                                iqentry_exc[dram2_id[`QBITS]] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DBE : rdv_i ? `FLT_DRF : `FLT_NONE;
8576
                    default:
8577
                        if (iqentry_stomp[dram0_id[`QBITS]])
8578
                                iqentry_exc[dram0_id[`QBITS]] <= `FLT_NONE;
8579
                        else
8580
                                iqentry_exc[dram0_id[`QBITS]] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DBE : rdv_i ? `FLT_DRF : `FLT_NONE;
8581
                    endcase
8582
            case(dccnt)
8583
            2'd0:       dcbuf[63:0] <= dat_i;
8584
            2'd1:       dcbuf[127:64] <= dat_i;
8585
            2'd2:       dcbuf[191:128] <= dat_i;
8586
            2'd3:       dcbuf[255:192] <= dat_i;
8587
                endcase
8588
            dccnt <= dccnt + 2'd1;
8589
            vadr[4:3] <= vadr[4:3] + 2'd1;
8590
            if (dccnt==2'd2)
8591
                                cti_o <= 3'b111;
8592
            if (dccnt==2'd3) begin
8593
                wb_nack();
8594
                                dcwr <= 1'b1;
8595
                                dcwait_ctr <= dcwait;
8596
                                bstate <= B_DCacheLoadWait;
8597
            end
8598
          end
8599
        end
8600 60 robfinch
B_DCacheLoadStb:
8601
        begin
8602
                stb_o <= `HIGH;
8603
                bstate <= B_DCacheLoadAck;
8604 66 robfinch
    case(bwhich)
8605
    2'd0:
8606
        if (iqentry_stomp[dram0_id[`QBITS]]) begin
8607
                wb_nack();
8608
                dram0 <= `DRAMREQ_READY;
8609
                bstate <= BIDLE;
8610
                end
8611
        2'd1:
8612
        if (iqentry_stomp[dram1_id[`QBITS]]) begin
8613
                wb_nack();
8614
                dram1 <= `DRAMREQ_READY;
8615
                bstate <= BIDLE;
8616
                end
8617
        2'd2:
8618
        if (iqentry_stomp[dram2_id[`QBITS]]) begin
8619
                wb_nack();
8620
                dram2 <= `DRAMREQ_READY;
8621
                bstate <= BIDLE;
8622
                end
8623
        default:
8624
        if (iqentry_stomp[dram0_id[`QBITS]]) begin
8625
                wb_nack();
8626
                dram0 <= `DRAMREQ_READY;
8627
                bstate <= BIDLE;
8628
                end
8629
        endcase
8630 60 robfinch
  end
8631 66 robfinch
B_DCacheLoadWait:
8632
        begin
8633
                dcsel <= 32'h0;
8634
                dcwr <= 1'b0;
8635
                dcwait_ctr <= dcwait_ctr - 4'd1;
8636
                if (dcwait_ctr[3])      // detect underflow
8637
                        bstate <= B_DCacheLoadResetBusy;
8638
        end
8639 61 robfinch
// There could be more than one memory cycle active. We reset the state
8640 66 robfinch
// of the other machines to retest for a hit because otherwise sequential
8641 61 robfinch
// loading of memory will cause successive machines to miss resulting in 
8642
// multiple dcache loads that aren't needed.
8643
B_DCacheLoadResetBusy:
8644
        begin
8645 66 robfinch
    if (`NUM_MEM > 1)
8646
                  case(bwhich)
8647
                  2'b01:
8648
                        begin
8649
                                dram1 <= `DRAMREQ_READY;
8650
                            if (dram0 != `DRAMSLOT_AVAIL && dram0_addr[AMSB:5]==vadr[AMSB:5]) dram0 <= `DRAMSLOT_BUSY;  // causes retest of dhit
8651
                            if (dram2 != `DRAMSLOT_AVAIL && dram2_addr[AMSB:5]==vadr[AMSB:5]) dram2 <= `DRAMSLOT_BUSY;
8652
                        end
8653
                  2'b10:
8654
                    if (`NUM_MEM > 2) begin
8655
                                        dram2 <= `DRAMREQ_READY;
8656
                            if (dram0 != `DRAMSLOT_AVAIL && dram0_addr[AMSB:5]==vadr[AMSB:5]) dram0 <= `DRAMSLOT_BUSY;  // causes retest of dhit
8657
                            if (dram1 != `DRAMSLOT_AVAIL && dram1_addr[AMSB:5]==vadr[AMSB:5]) dram1 <= `DRAMSLOT_BUSY;
8658
                        end
8659
                                else begin
8660
                                        dram0 <= `DRAMREQ_READY;
8661
                            if (dram1 != `DRAMSLOT_AVAIL && dram1_addr[AMSB:5]==vadr[AMSB:5]) dram1 <= `DRAMSLOT_BUSY;
8662
                            if (dram2 != `DRAMSLOT_AVAIL && dram2_addr[AMSB:5]==vadr[AMSB:5]) dram2 <= `DRAMSLOT_BUSY;
8663
                        end
8664
                  default:
8665
                        begin
8666
                                dram0 <= `DRAMREQ_READY;
8667
                            if (dram1 != `DRAMSLOT_AVAIL && dram1_addr[AMSB:5]==vadr[AMSB:5]) dram1 <= `DRAMSLOT_BUSY;
8668
                            if (dram2 != `DRAMSLOT_AVAIL && dram2_addr[AMSB:5]==vadr[AMSB:5]) dram2 <= `DRAMSLOT_BUSY;
8669
                        end
8670
                  endcase
8671
                else begin
8672
                        dram0 <= `DRAMREQ_READY;
8673
                end
8674 61 robfinch
    bstate <= BIDLE;
8675
  end
8676 60 robfinch
 
8677 66 robfinch
B_RMWAck:
8678
  if (acki|err_i|tlb_miss|rdv_i) begin
8679
    if (isCAS) begin
8680
             iqentry_res        [ casid[`QBITS] ] <= (dat_i == cas);
8681
         iqentry_exc [ casid[`QBITS] ] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
8682
//             iqentry_done[ casid[`QBITS] ] <= `VAL;
8683
//           iqentry_out [ casid[`QBITS] ] <= `INV;
8684
             iqentry_state [ casid[`QBITS] ] <= IQS_DONE;
8685
             iqentry_instr[ casid[`QBITS]] <= `NOP_INSN;
8686
            if (err_i | rdv_i)
8687
                iqentry_ma[casid[`QBITS]] <= vadr;
8688
      if (dat_i == cas) begin
8689
        stb_o <= `LOW;
8690
        we <= `TRUE;
8691
        bstate <= B15;
8692
                                check_abort_load();
8693
      end
8694
      else begin
8695
                                cas <= dat_i;
8696
                                cyc <= `LOW;
8697
                                stb_o <= `LOW;
8698
                                case(bwhich)
8699
                                2'b00:   dram0 <= `DRAMREQ_READY;
8700
                                2'b01:   dram1 <= `DRAMREQ_READY;
8701
                                2'b10:   dram2 <= `DRAMREQ_READY;
8702
                                default:    ;
8703
                                endcase
8704
                                bstate <= B_LSNAck;
8705
                                check_abort_load();
8706
      end
8707 60 robfinch
    end
8708 66 robfinch
    else if (isRMW) begin
8709
             rmw_instr <= iqentry_instr[casid[`QBITS]];
8710
             rmw_argA <= dat_i;
8711
         if (isSpt) begin
8712
                rmw_argB <= 64'd1 << iqentry_a1[casid[`QBITS]][63:58];
8713
                rmw_argC <= iqentry_instr[casid[`QBITS]][5:0]==`R2 ?
8714
                                        iqentry_a3[casid[`QBITS]][64] << iqentry_a1[casid[`QBITS]][63:58] :
8715
                                        iqentry_a2[casid[`QBITS]][64] << iqentry_a1[casid[`QBITS]][63:58];
8716
         end
8717
         else if (isInc) begin
8718
                rmw_argB <= iqentry_instr[casid[`QBITS]][5:0]==`R2 ? {{59{iqentry_instr[casid[`QBITS]][22]}},iqentry_instr[casid[`QBITS]][22:18]} :
8719
                                                                                                                         {{59{iqentry_instr[casid[`QBITS]][17]}},iqentry_instr[casid[`QBITS]][17:13]};
8720
         end
8721
         else begin // isAMO
8722
             iqentry_res [ casid[`QBITS] ] <= dat_i;
8723
             rmw_argB <= iqentry_instr[casid[`QBITS]][31] ? {{59{iqentry_instr[casid[`QBITS]][20:16]}},iqentry_instr[casid[`QBITS]][20:16]} : iqentry_a2[casid[`QBITS]];
8724
       end
8725
         iqentry_exc [ casid[`QBITS] ] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
8726
         stb_o <= `LOW;
8727
         bstate <= B20;
8728
                                check_abort_load();
8729 60 robfinch
                end
8730
  end
8731 61 robfinch
 
8732 60 robfinch
// Regular load
8733
B_DLoadAck:
8734 61 robfinch
  if (acki|err_i|tlb_miss|rdv_i) begin
8735 60 robfinch
        wb_nack();
8736
                sr_o <= `LOW;
8737 61 robfinch
                case(dccnt)
8738
                2'd0:   xdati[63:0] <= dat_i;
8739
                2'd1:   xdati[127:64] <= dat_i;
8740
                endcase
8741 60 robfinch
    case(bwhich)
8742
    2'b00:  begin
8743 61 robfinch
                                        if (dram0_memsize==hexi) begin
8744
                                                if (dccnt==2'd1) begin
8745
                                     dram0 <= `DRAMREQ_READY;
8746
                                     iqentry_seg_base[dram0_id[`QBITS]] <= xdati[63:0];
8747
                                     iqentry_seg_acr[dram0_id[`QBITS]] <= dat_i;
8748
                                  end
8749
                                  else begin
8750
                                        dccnt <= dccnt + 2'd1;
8751
                                        cyc <= `HIGH;
8752
                                        sel_o <= 8'hFF;
8753
                                        vadr <= vadr + 64'd8;
8754
                                        bstate <= B_DLoadNack;
8755
                                        end
8756
                                        end
8757
                                        else
8758
                        dram0 <= `DRAMREQ_READY;
8759 66 robfinch
                if (iqentry_stomp[dram0_id[`QBITS]])
8760
                        iqentry_exc [dram0_id[`QBITS]] <= `FLT_NONE;
8761
                else
8762
                        iqentry_exc [ dram0_id[`QBITS] ] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
8763 60 robfinch
            end
8764
    2'b01:  if (`NUM_MEM > 1) begin
8765
             dram1 <= `DRAMREQ_READY;
8766 66 robfinch
                if (iqentry_stomp[dram1_id[`QBITS]])
8767
                        iqentry_exc [dram1_id[`QBITS]] <= `FLT_NONE;
8768
                else
8769
                     iqentry_exc [ dram1_id[`QBITS] ] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
8770 60 robfinch
            end
8771
    2'b10:  if (`NUM_MEM > 2) begin
8772
             dram2 <= `DRAMREQ_READY;
8773 66 robfinch
                if (iqentry_stomp[dram2_id[`QBITS]])
8774
                        iqentry_exc [dram2_id[`QBITS]] <= `FLT_NONE;
8775
                else
8776
                     iqentry_exc [ dram2_id[`QBITS] ] <= tlb_miss ? `FLT_TLB : err_i ? `FLT_DRF : rdv_i ? `FLT_DRF : `FLT_NONE;
8777 60 robfinch
            end
8778
    default:    ;
8779
    endcase
8780 61 robfinch
                bstate <= B_LSNAck;
8781 66 robfinch
                check_abort_load();
8782 60 robfinch
        end
8783 61 robfinch
B_DLoadNack:
8784
        if (~acki) begin
8785
                stb_o <= `HIGH;
8786
                bstate <= B_DLoadAck;
8787 66 robfinch
                check_abort_load();
8788 61 robfinch
        end
8789 60 robfinch
 
8790
// Three cycles to detemrine if there's a cache hit during a store.
8791 66 robfinch
B16:
8792
        begin
8793
    case(bwhich)
8794
    2'd0:      if (dhit0) begin  dram0 <= `DRAMREQ_READY; bstate <= B17; end
8795
    2'd1:      if (dhit1) begin  dram1 <= `DRAMREQ_READY; bstate <= B17; end
8796
    2'd2:      if (dhit2) begin  dram2 <= `DRAMREQ_READY; bstate <= B17; end
8797
    default:    bstate <= BIDLE;
8798
    endcase
8799
                check_abort_load();
8800
  end
8801
B17:
8802
        begin
8803
    bstate <= B18;
8804
                check_abort_load();
8805
  end
8806
B18:
8807
        begin
8808
        bstate <= B_LSNAck;
8809
                check_abort_load();
8810
        end
8811 61 robfinch
B_LSNAck:
8812 66 robfinch
        begin
8813
                bstate <= BIDLE;
8814
                StoreAck1 <= `FALSE;
8815
                isStore <= `FALSE;
8816
                check_abort_load();
8817
        end
8818 60 robfinch
B20:
8819 61 robfinch
        if (~acki) begin
8820 60 robfinch
                stb_o <= `HIGH;
8821
                we  <= `HIGH;
8822
                dat_o <= fnDato(rmw_instr,rmw_res);
8823
                bstate <= B_StoreAck;
8824 66 robfinch
                check_abort_load();
8825 60 robfinch
        end
8826
B21:
8827 61 robfinch
        if (~acki) begin
8828 60 robfinch
                stb_o <= `HIGH;
8829 66 robfinch
                bstate <= B_RMWAck;
8830
                check_abort_load();
8831 60 robfinch
        end
8832
default:     bstate <= BIDLE;
8833
endcase
8834
 
8835 61 robfinch
 
8836 60 robfinch
if (!branchmiss) begin
8837 61 robfinch
  case({fetchbuf0_v, fetchbuf1_v})
8838
  2'b00:  ;
8839
  2'b01:
8840
    if (canq1) begin
8841
        tail0 <= (tail0+2'd1) % QENTRIES;
8842
        tail1 <= (tail1+2'd1) % QENTRIES;
8843
    end
8844
  2'b10:
8845
    if (canq1) begin
8846
        tail0 <= (tail0+2'd1) % QENTRIES;
8847
        tail1 <= (tail1+2'd1) % QENTRIES;
8848
    end
8849
  2'b11:
8850
    if (canq1) begin
8851
      if (IsBranch(fetchbuf0_instr) && predict_taken0 && fetchbuf0_thrd==fetchbuf1_thrd) begin
8852
        tail0 <= (tail0+2'd1) % QENTRIES;
8853
        tail1 <= (tail1+2'd1) % QENTRIES;
8854
      end
8855
      else begin
8856
                                if (vqe0 < vl || !IsVector(fetchbuf0_instr)) begin
8857
          if (canq2) begin
8858
            tail0 <= (tail0 + 3'd2) % QENTRIES;
8859
            tail1 <= (tail1 + 3'd2) % QENTRIES;
8860
          end
8861
          else begin    // queued1 will be true
8862 60 robfinch
                tail0 <= (tail0+2'd1) % QENTRIES;
8863 61 robfinch
                                        tail1 <= (tail1+2'd1) % QENTRIES;
8864
          end
8865
        end
8866
      end
8867
    end
8868
  endcase
8869 60 robfinch
end
8870
else if (!thread_en) begin      // if branchmiss
8871
        for (n = QENTRIES-1; n >= 0; n = n - 1)
8872
                // (QENTRIES-1) is needed to ensure that n increments forwards so that the modulus is
8873
                // a positive number.
8874
                if (iqentry_stomp[n] & ~iqentry_stomp[(n+(QENTRIES-1))%QENTRIES]) begin
8875
                        tail0 <= n;
8876
                        tail1 <= (n + 1) % QENTRIES;
8877
                end
8878
    // otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
8879
end
8880
 
8881
//      #5 rf[0] = 0; rf_v[0] = 1; rf_source[0] = 0;
8882
`ifdef SIM
8883
        $display("\n\n\n\n\n\n\n\n");
8884
        $display("TIME %0d", $time);
8885
        $display("%h #", pc0);
8886
`ifdef SUPPORT_SMT
8887
    $display ("Regfile: %d", rgs[0]);
8888
        for (n=0; n < 32; n=n+4) begin
8889
            $display("%d: %h %d %o   %d: %h %d %o   %d: %h %d %o   %d: %h %d %o#",
8890
               n[4:0]+0, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
8891
               n[4:0]+1, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
8892
               n[4:0]+2, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
8893
               n[4:0]+3, urf1.urf10.mem[{rgs[0],1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
8894
               );
8895
        end
8896
    $display ("Regfile: %d", rgs[1]);
8897
        for (n=128; n < 160; n=n+4) begin
8898
            $display("%d: %h %d %o   %d: %h %d %o   %d: %h %d %o   %d: %h %d %o#",
8899
               n[4:0]+0, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
8900
               n[4:0]+1, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
8901
               n[4:0]+2, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
8902
               n[4:0]+3, urf1.urf10.mem[{rgs[1],1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
8903
               );
8904
        end
8905
`else
8906
    $display ("Regfile: %d", rgs);
8907
        for (n=0; n < 32; n=n+4) begin
8908
            $display("%d: %h %d %o   %d: %h %d %o   %d: %h %d %o   %d: %h %d %o#",
8909
               n[4:0]+0, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b00}], regIsValid[n+0], rf_source[n+0],
8910
               n[4:0]+1, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b01}], regIsValid[n+1], rf_source[n+1],
8911
               n[4:0]+2, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b10}], regIsValid[n+2], rf_source[n+2],
8912
               n[4:0]+3, gRegfileInst.gb1.urf1.urf10.mem[{rgs,1'b0,n[4:2],2'b11}], regIsValid[n+3], rf_source[n+3]
8913
               );
8914
        end
8915
`endif
8916
`ifdef FCU_ENH
8917
        $display("Call Stack:");
8918
        for (n = 0; n < 16; n = n + 4)
8919
                $display("%c%d: %h   %c%d: %h   %c%d: %h   %c%d: %h",
8920
                        gFetchbufInst.gb1.ufb1.ursb1.rasp==n+0 ?">" : " ", n[4:0]+0, gFetchbufInst.gb1.ufb1.ursb1.ras[n+0],
8921
                        gFetchbufInst.gb1.ufb1.ursb1.rasp==n+1 ?">" : " ", n[4:0]+1, gFetchbufInst.gb1.ufb1.ursb1.ras[n+1],
8922
                        gFetchbufInst.gb1.ufb1.ursb1.rasp==n+2 ?">" : " ", n[4:0]+2, gFetchbufInst.gb1.ufb1.ursb1.ras[n+2],
8923
                        gFetchbufInst.gb1.ufb1.ursb1.rasp==n+3 ?">" : " ", n[4:0]+3, gFetchbufInst.gb1.ufb1.ursb1.ras[n+3]
8924
                );
8925
        $display("\n");
8926
`endif
8927
//    $display("Return address stack:");
8928
//    for (n = 0; n < 16; n = n + 1)
8929
//        $display("%d %h", rasp+n[3:0], ras[rasp+n[3:0]]);
8930
        $display("TakeBr:%d #", take_branch);//, backpc);
8931
        $display("Insn%d: %h", 0, insn0);
8932
        if (`WAYS==1) begin
8933
        $display("%c%c A: %d %h %h #",
8934
            45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
8935
        $display("%c%c B: %d %h %h #",
8936
            45, fetchbuf?62:45, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
8937
        end
8938
        else if (`WAYS > 1) begin
8939
                $display("Insn%d: %h", 1, insn1);
8940
        $display("%c%c A: %d %h %h #",
8941
            45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
8942
        $display("%c%c B: %d %h %h #",
8943
            45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
8944
        end
8945
        else if (`WAYS > 2) begin
8946
                $display("%c%c C: %d %h %h #",
8947
                    45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
8948
                $display("%c%c D: %d %h %h #",
8949
                    45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
8950
        end
8951
        for (i=0; i<QENTRIES; i=i+1)
8952
            $display("%c%c %d: %c%c%c%c %d %d %c%c %c %c%h %d %o %h %h %h %d %o %h %d %o %h %d %o %d:%h %h %d#",
8953
                 (i[`QBITS]==heads[0])?"C":".",
8954
                 (i[`QBITS]==tail0)?"Q":".",
8955
                  i[`QBITS],
8956 61 robfinch
                  iqentry_state[i]==IQS_INVALID ? "-" :
8957
                  iqentry_state[i]==IQS_QUEUED ? "Q" :
8958
                  iqentry_state[i]==IQS_OUT ? "O"  :
8959
                  iqentry_state[i]==IQS_AGEN ? "A"  :
8960
                  iqentry_state[i]==IQS_MEM ? "M"  :
8961
                  iqentry_state[i]==IQS_DONE ? "D"  :
8962
                  iqentry_state[i]==IQS_CMT ? "C"  : "?",
8963
//               iqentry_v[i] ? "v" : "-",
8964 60 robfinch
                 iqentry_iv[i] ? "I" : "-",
8965
                 iqentry_done[i]?"d":"-",
8966
                 iqentry_out[i]?"o":"-",
8967
                 iqentry_bt[i],
8968
                 iqentry_memissue[i],
8969
                 iqentry_agen[i] ? "a": "-",
8970
                 iqentry_alu0_issue[i]?"0":iqentry_alu1_issue[i]?"1":"-",
8971
                 iqentry_stomp[i]?"s":"-",
8972
                iqentry_fc[i] ? "F" : iqentry_mem[i] ? "M" : (iqentry_alu[i]==1'b1) ? "a" : (iqentry_alu[i]==1'bx) ? "X" : iqentry_fpu[i] ? "f" : "O",
8973
                iqentry_instr[i], iqentry_tgt[i][4:0],
8974
                iqentry_exc[i], iqentry_res[i], iqentry_a0[i], iqentry_a1[i], iqentry_a1_v[i],
8975
                iqentry_a1_s[i],
8976
                iqentry_a2[i], iqentry_a2_v[i], iqentry_a2_s[i],
8977
                iqentry_a3[i], iqentry_a3_v[i], iqentry_a3_s[i],
8978
                iqentry_thrd[i],
8979
                iqentry_pc[i],
8980
                iqentry_sn[i], iqentry_ven[i]
8981
                );
8982
    $display("DRAM");
8983
        $display("%d %h %h %c%h %o #",
8984
            dram0, dram0_addr, dram0_data, (IsFlowCtrl(dram0_instr) ? 98 : (IsMem(dram0_instr)) ? 109 : 97),
8985
            dram0_instr, dram0_id);
8986
          if (`NUM_MEM > 1)
8987
        $display("%d %h %h %c%h %o #",
8988
            dram1, dram1_addr, dram1_data, (IsFlowCtrl(dram1_instr) ? 98 : (IsMem(dram1_instr)) ? 109 : 97),
8989
            dram1_instr, dram1_id);
8990
          if (`NUM_MEM > 2)
8991
        $display("%d %h %h %c%h %o #",
8992
            dram2, dram2_addr, dram2_data, (IsFlowCtrl(dram2_instr) ? 98 : (IsMem(dram2_instr)) ? 109 : 97),
8993
            dram2_instr, dram2_id);
8994 61 robfinch
        $display("%d %h %o #", dramA_v, dramA_bus, dramA_id);
8995 60 robfinch
        if (`NUM_MEM > 1)
8996 61 robfinch
        $display("%d %h %o #", dramB_v, dramB_bus, dramB_id);
8997 60 robfinch
        if (`NUM_MEM > 2)
8998 61 robfinch
        $display("%d %h %o #", dramC_v, dramC_bus, dramC_id);
8999 60 robfinch
    $display("ALU");
9000
        $display("%d %h %h %h %c%h %o %h #",
9001
                alu0_dataready, alu0_argI, alu0_argA, alu0_argB,
9002
                 (IsFlowCtrl(alu0_instr) ? 98 : IsMem(alu0_instr) ? 109 : 97),
9003
                alu0_instr, alu0_sourceid, alu0_pc);
9004
        $display("%d %h %o 0 #", alu0_v, alu0_bus, alu0_id);
9005
        if (`NUM_ALU > 1) begin
9006
                $display("%d %h %h %h %c%h %o %h #",
9007
                        alu1_dataready, alu1_argI, alu1_argA, alu1_argB,
9008
                        (IsFlowCtrl(alu1_instr) ? 98 : IsMem(alu1_instr) ? 109 : 97),
9009
                        alu1_instr, alu1_sourceid, alu1_pc);
9010
                $display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
9011
        end
9012
        $display("FCU");
9013
        $display("%d %h %h %h %h %c%c #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB, fcu_takb?"T":"-", fcu_pt?"T":"-");
9014
        $display("%c %h %h %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc, fcu_nextpc, fcu_brdisp);
9015
    $display("Commit");
9016
        $display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
9017
        $display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
9018
    $display("instructions committed: %d valid committed: %d ticks: %d ", CC, I, tick);
9019
  $display("Write Buffer:");
9020
  for (n = `WB_DEPTH-1; n >= 0; n = n - 1)
9021
        $display("%c adr: %h dat: %h", wb_v[n]?" ":"*", wb_addr[n], wb_data[n]);
9022
    $display("Write merges: %d", wb_merges);
9023
`endif  // SIM
9024
 
9025
//
9026
//      $display("\n\n\n\n\n\n\n\n");
9027
//      $display("TIME %0d", $time);
9028
//      $display("  pc0=%h", pc0);
9029
//      $display("  pc1=%h", pc1);
9030
//      $display("  reg0=%h, v=%d, src=%o", rf[0], rf_v[0], rf_source[0]);
9031
//      $display("  reg1=%h, v=%d, src=%o", rf[1], rf_v[1], rf_source[1]);
9032
//      $display("  reg2=%h, v=%d, src=%o", rf[2], rf_v[2], rf_source[2]);
9033
//      $display("  reg3=%h, v=%d, src=%o", rf[3], rf_v[3], rf_source[3]);
9034
//      $display("  reg4=%h, v=%d, src=%o", rf[4], rf_v[4], rf_source[4]);
9035
//      $display("  reg5=%h, v=%d, src=%o", rf[5], rf_v[5], rf_source[5]);
9036
//      $display("  reg6=%h, v=%d, src=%o", rf[6], rf_v[6], rf_source[6]);
9037
//      $display("  reg7=%h, v=%d, src=%o", rf[7], rf_v[7], rf_source[7]);
9038
 
9039
//      $display("Fetch Buffers:");
9040
//      $display("  %c%c fbA: v=%d instr=%h pc=%h     %c%c fbC: v=%d instr=%h pc=%h", 
9041
//          fetchbuf?32:45, fetchbuf?32:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc,
9042
//          fetchbuf?45:32, fetchbuf?62:32, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
9043
//      $display("  %c%c fbB: v=%d instr=%h pc=%h     %c%c fbD: v=%d instr=%h pc=%h", 
9044
//          fetchbuf?32:45, fetchbuf?32:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc,
9045
//          fetchbuf?45:32, fetchbuf?62:32, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
9046
//      $display("  branchback=%d backpc=%h", branchback, backpc);
9047
 
9048
//      $display("Instruction Queue:");
9049
//      for (i=0; i<8; i=i+1) 
9050
//          $display(" %c%c%d: v=%d done=%d out=%d agen=%d res=%h op=%d bt=%d tgt=%d a1=%h (v=%d/s=%o) a2=%h (v=%d/s=%o) im=%h pc=%h exc=%h",
9051
//              (i[`QBITS]==heads[0])?72:32, (i[`QBITS]==tail0)?84:32, i,
9052
//              iqentry_v[i], iqentry_done[i], iqentry_out[i], iqentry_agen[i], iqentry_res[i], iqentry_op[i], 
9053
//              iqentry_bt[i], iqentry_tgt[i], iqentry_a1[i], iqentry_a1_v[i], iqentry_a1_s[i], iqentry_a2[i], iqentry_a2_v[i], 
9054
//              iqentry_a2_s[i], iqentry_a0[i], iqentry_pc[i], iqentry_exc[i]);
9055
 
9056
//      $display("Scheduling Status:");
9057
//      $display("  iqentry0 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b", 
9058
//              iqentry_0_issue, iqentry_0_islot, iqentry_stomp[0], iqentry_source[0], iqentry_memready[0], iqentry_memissue[0]);
9059
//      $display("  iqentry1 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
9060
//              iqentry_1_issue, iqentry_1_islot, iqentry_stomp[1], iqentry_source[1], iqentry_memready[1], iqentry_memissue[1]);
9061
//      $display("  iqentry2 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
9062
//              iqentry_2_issue, iqentry_2_islot, iqentry_stomp[2], iqentry_source[2], iqentry_memready[2], iqentry_memissue[2]);
9063
//      $display("  iqentry3 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b", 
9064
//              iqentry_3_issue, iqentry_3_islot, iqentry_stomp[3], iqentry_source[3], iqentry_memready[3], iqentry_memissue[3]);
9065
//      $display("  iqentry4 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b", 
9066
//              iqentry_4_issue, iqentry_4_islot, iqentry_stomp[4], iqentry_source[4], iqentry_memready[4], iqentry_memissue[4]);
9067
//      $display("  iqentry5 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b", 
9068
//              iqentry_5_issue, iqentry_5_islot, iqentry_stomp[5], iqentry_source[5], iqentry_memready[5], iqentry_memissue[5]);
9069
//      $display("  iqentry6 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
9070
//              iqentry_6_issue, iqentry_6_islot, iqentry_stomp[6], iqentry_source[6], iqentry_memready[6], iqentry_memissue[6]);
9071
//      $display("  iqentry7 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
9072
//              iqentry_7_issue, iqentry_7_islot, iqentry_stomp[7], iqentry_source[7], iqentry_memready[7], iqentry_memissue[7]);
9073
 
9074
//      $display("ALU Inputs:");
9075
//      $display("  0: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
9076
//              alu0_available, alu0_dataready, alu0_sourceid, alu0_op, alu0_argA,
9077
//              alu0_argB, alu0_argI, alu0_bt);
9078
//      $display("  1: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
9079
//              alu1_available, alu1_dataready, alu1_sourceid, alu1_op, alu1_argA,
9080
//              alu1_argB, alu1_argI, alu1_bt);
9081
 
9082
//      $display("ALU Outputs:");
9083
//      $display("  0: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
9084
//              alu0_v, alu0_bus, alu0_id, alu0_branchmiss, alu0_misspc, alu0_sourceid);
9085
//      $display("  1: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
9086
//              alu1_v, alu1_bus, alu1_id, alu1_branchmiss, alu1_misspc, alu1_sourceid);
9087
 
9088
//      $display("DRAM Status:");
9089
//      $display("  OUT: v=%d data=%h tgt=%d id=%o", dram_v, dram_bus, dram_tgt, dram_id);
9090
//      $display("  dram0: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
9091
//          dram0, dram0_addr, dram0_data, dram0_op, dram0_tgt, dram0_id);
9092
//      $display("  dram1: status=%h addr=%h data=%h op=%d tgt=%d id=%o", 
9093
//          dram1, dram1_addr, dram1_data, dram1_op, dram1_tgt, dram1_id);
9094
//      $display("  dram2: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
9095
//          dram2, dram2_addr, dram2_data, dram2_op, dram2_tgt, dram2_id);
9096
 
9097
//      $display("Commit Buses:");
9098
//      $display("  0: v=%d id=%o data=%h", commit0_v, commit0_id, commit0_bus);
9099
//      $display("  1: v=%d id=%o data=%h", commit1_v, commit1_id, commit1_bus);
9100
 
9101
//
9102
//      $display("Memory Contents:");
9103
//      for (j=0; j<64; j=j+16)
9104
//          $display("  %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h", 
9105
//              m[j+0], m[j+1], m[j+2], m[j+3], m[j+4], m[j+5], m[j+6], m[j+7],
9106
//              m[j+8], m[j+9], m[j+10], m[j+11], m[j+12], m[j+13], m[j+14], m[j+15]);
9107
 
9108
        $display("");
9109
 
9110
        if (|panic) begin
9111
            $display("");
9112
            $display("-----------------------------------------------------------------");
9113
            $display("-----------------------------------------------------------------");
9114
            $display("---------------     PANIC:%s     -----------------", message[panic]);
9115
            $display("-----------------------------------------------------------------");
9116
            $display("-----------------------------------------------------------------");
9117
            $display("");
9118
            $display("instructions committed: %d", I);
9119
            $display("total execution cycles: %d", $time / 10);
9120
            $display("");
9121
        end
9122
        if (|panic && ~outstanding_stores) begin
9123
            $finish;
9124
        end
9125
/*
9126
    for (n = 0; n < QENTRIES; n = n + 1)
9127
        if (branchmiss) begin
9128
            if (!setpred[n]) begin
9129
                 iqentry_instr[n][`INSTRUCTION_OP] <= `NOP;
9130
                 iqentry_done[n] <= iqentry_v[n];
9131
                 iqentry_cmt[n] <= iqentry_v[n];
9132
            end
9133
        end
9134
*/
9135
        rf_source[ 0] <= {`QBIT{1'b1}};
9136
        rf_source[32] <= {`QBIT{1'b1}};
9137
        rf_source[64] <= {`QBIT{1'b1}};
9138
        rf_source[96] <= {`QBIT{1'b1}};
9139
`ifdef SUPPORTSMT
9140
        rf_source[128] <= {`QBIT{1'b1}};
9141
        rf_source[160] <= {`QBIT{1'b1}};
9142
        rf_source[192] <= {`QBIT{1'b1}};
9143
        rf_source[224] <= {`QBIT{1'b1}};
9144
`endif
9145
 
9146
end // clock domain
9147
/*
9148
always @(posedge clk)
9149
if (rst) begin
9150
     tail0 <= 3'd0;
9151
     tail1 <= 3'd1;
9152
end
9153
else begin
9154
if (!branchmiss) begin
9155
    case({fetchbuf0_v, fetchbuf1_v})
9156
    2'b00:  ;
9157
    2'b01:
9158
        if (canq1) begin
9159
             tail0 <= idp1(tail0);
9160
             tail1 <= idp1(tail1);
9161
        end
9162
    2'b10:
9163
        if (canq1) begin
9164
             tail0 <= idp1(tail0);
9165
             tail1 <= idp1(tail1);
9166
        end
9167
    2'b11:
9168
        if (canq1) begin
9169
            if (IsBranch(fetchbuf0_instr) && predict_taken0) begin
9170
                 tail0 <= idp1(tail0);
9171
                 tail1 <= idp1(tail1);
9172
            end
9173
            else begin
9174
                                if (vqe < vl || !IsVector(fetchbuf0_instr)) begin
9175
                        if (canq2) begin
9176
                             tail0 <= idp2(tail0);
9177
                             tail1 <= idp2(tail1);
9178
                        end
9179
                        else begin    // queued1 will be true
9180
                             tail0 <= idp1(tail0);
9181
                             tail1 <= idp1(tail1);
9182
                        end
9183
                end
9184
            end
9185
        end
9186
    endcase
9187
end
9188
else begin      // if branchmiss
9189
    if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
9190
         tail0 <= 3'd0;
9191
         tail1 <= 3'd1;
9192
    end
9193
    else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
9194
         tail0 <= 3'd1;
9195
         tail1 <= 3'd2;
9196
    end
9197
    else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
9198
         tail0 <= 3'd2;
9199
         tail1 <= 3'd3;
9200
    end
9201
    else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
9202
         tail0 <= 3'd3;
9203
         tail1 <= 3'd4;
9204
    end
9205
    else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
9206
         tail0 <= 3'd4;
9207
         tail1 <= 3'd5;
9208
    end
9209
    else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
9210
         tail0 <= 3'd5;
9211
         tail1 <= 3'd6;
9212
    end
9213
    else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
9214
         tail0 <= 3'd6;
9215
         tail1 <= 3'd7;
9216
    end
9217
    else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
9218
         tail0 <= 3'd7;
9219
         tail1 <= 3'd0;
9220
    end
9221
    // otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
9222
end
9223
end
9224
*/
9225 61 robfinch
assign exc_o = iqentry_exc[heads[0]][7:0];
9226 60 robfinch
 
9227 66 robfinch
task check_abort_load;
9228
begin
9229
  case(bwhich)
9230
  2'd0: if (iqentry_stomp[dram0_id[`QBITS]]) begin bstate <= BIDLE; dram0 <= `DRAMREQ_READY; end
9231
  2'd1: if (iqentry_stomp[dram1_id[`QBITS]]) begin bstate <= BIDLE; dram1 <= `DRAMREQ_READY; end
9232
  2'd2: if (iqentry_stomp[dram2_id[`QBITS]]) begin bstate <= BIDLE; dram2 <= `DRAMREQ_READY; end
9233
  default:      if (iqentry_stomp[dram0_id[`QBITS]]) begin bstate <= BIDLE; dram0 <= `DRAMREQ_READY; end
9234
  endcase
9235
end
9236
endtask
9237
 
9238 60 robfinch
// Update the write buffer.
9239
task wb_update;
9240
input [`QBITS] id;
9241
input rmw;
9242
input [7:0] sel;
9243
input [1:0] ol;
9244
input [`ABITS] addr;
9245
input [63:0] data;
9246 66 robfinch
input [2:0] wbptr;
9247 60 robfinch
begin
9248
        if (wbm && wbptr > 1 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3]
9249
         && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw && wb_v[wbptr-1]) begin
9250
                // The write buffer is always shifted during the bus IDLE state. That means
9251
                // the data is out of place by a slot. The slot the data is moved from is
9252
                // invalidated.
9253
                wb_v[wbptr-2] <= `INV;
9254
                wb_v[wbptr-1] <= wb_en;
9255
                wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
9256
                wb_rmw[wbptr-1] <= rmw;
9257
                wb_ol[wbptr-1] <= ol;
9258
                wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
9259
                wb_addr[wbptr-1] <= wb_addr[wbptr-1];
9260
                wb_data[wbptr-1] <= wb_data[wbptr-1];
9261
                if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
9262
                if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
9263
                if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
9264
                if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
9265
                if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
9266
                if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
9267
                if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
9268
                if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
9269
                wb_merges <= wb_merges + 32'd1;
9270
        end
9271
        else begin
9272
                wb_v[wbptr] <= wb_en;
9273
                wb_id[wbptr] <= (16'd1 << id);
9274
                wb_rmw[wbptr] <= rmw;
9275
                wb_ol[wbptr] <= ol;
9276
                wb_sel[wbptr] <= sel;
9277
                wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
9278
                wb_data[wbptr] <= data;
9279
        end
9280
end
9281
endtask
9282
 
9283
// Increment the head pointers
9284
// Also increments the instruction counter
9285
// Used when instructions are committed.
9286
// Also clear any outstanding state bits that foul things up.
9287
//
9288
task head_inc;
9289
input [`QBITS] amt;
9290
begin
9291
        for (n = 0; n < QENTRIES; n = n + 1)
9292
     heads[n] <= (heads[n] + amt) % QENTRIES;
9293
        CC <= CC + amt;
9294
    if (amt==3'd3) begin
9295
        I = I + iqentry_v[heads[0]] + iqentry_v[heads[1]] + iqentry_v[heads[2]];
9296
        iqentry_state[heads[0]] <= IQS_INVALID;
9297
        iqentry_state[heads[1]] <= IQS_INVALID;
9298
        iqentry_state[heads[2]] <= IQS_INVALID;
9299
        iqentry_mem[heads[0]] <= `FALSE;
9300
        iqentry_mem[heads[1]] <= `FALSE;
9301
        iqentry_mem[heads[2]] <= `FALSE;
9302
        iqentry_iv[heads[0]] <= `INV;
9303
        iqentry_iv[heads[1]] <= `INV;
9304
        iqentry_iv[heads[2]] <= `INV;
9305
        iqentry_alu[heads[0]] <= `FALSE;
9306
        iqentry_alu[heads[1]] <= `FALSE;
9307
        iqentry_alu[heads[2]] <= `FALSE;
9308
                for (n = 0; n < QENTRIES; n = n + 1)
9309
                        if (iqentry_v[n])
9310
                                iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[2]] ? iqentry_sn[heads[2]]
9311
                                                                                                                                                         : iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
9312
                                                                                                                                                         : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
9313
                                                                                                                                                         : 4'b0);
9314
        end
9315
    else if (amt==3'd2) begin
9316
        I = I + iqentry_v[heads[0]] + iqentry_v[heads[1]];
9317
        iqentry_state[heads[0]] <= IQS_INVALID;
9318
        iqentry_state[heads[1]] <= IQS_INVALID;
9319
     iqentry_mem[heads[0]] <= `FALSE;
9320
     iqentry_mem[heads[1]] <= `FALSE;
9321
     iqentry_iv[heads[0]] <= `INV;
9322
     iqentry_iv[heads[1]] <= `INV;
9323
        iqentry_alu[heads[0]] <= `FALSE;
9324
     iqentry_alu[heads[1]] <= `FALSE;
9325
                for (n = 0; n < QENTRIES; n = n + 1)
9326
                        if (iqentry_v[n])
9327
                                iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
9328
                                                                                                                                                         : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
9329
                                                                                                                                                         : 4'b0);
9330
    end else if (amt==3'd1) begin
9331
        I = I + iqentry_v[heads[0]];
9332
        iqentry_state[heads[0]] <= IQS_INVALID;
9333
            iqentry_mem[heads[0]] <= `FALSE;
9334
        iqentry_iv[heads[0]] <= `INV;
9335
        iqentry_alu[heads[0]] <= `FALSE;
9336
                for (n = 0; n < QENTRIES; n = n + 1)
9337
                        if (iqentry_v[n])
9338
                                iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
9339
                                                                                                                                                         : 4'b0);
9340
        end
9341
end
9342
endtask
9343
 
9344
task setargs;
9345
input [`QBITS] nn;
9346
input [`QBITSP1] id;
9347
input v;
9348
input [63:0] bus;
9349
begin
9350
  if (iqentry_a1_v[nn] == `INV && iqentry_a1_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
9351
                iqentry_a1[nn] <= bus;
9352
                iqentry_a1_v[nn] <= `VAL;
9353
  end
9354
  if (iqentry_a2_v[nn] == `INV && iqentry_a2_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
9355
                iqentry_a2[nn] <= bus;
9356
                iqentry_a2_v[nn] <= `VAL;
9357
  end
9358
  if (iqentry_a3_v[nn] == `INV && iqentry_a3_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
9359
                iqentry_a3[nn] <= bus;
9360
                iqentry_a3_v[nn] <= `VAL;
9361
  end
9362
end
9363
endtask
9364
 
9365
task setinsn1;
9366
input [`QBITS] nn;
9367
input [143:0] bus;
9368
begin
9369
        iqentry_iv   [nn]  <= `VAL;
9370
//      iqentry_Rt   [nn]  <= bus[`IB_RT];
9371
//      iqentry_Rc   [nn]  <= bus[`IB_RC];
9372
//      iqentry_Ra   [nn]  <= bus[`IB_RA];
9373
        iqentry_a0       [nn]  <= bus[`IB_CONST];
9374
        iqentry_imm  [nn]  <= bus[`IB_IMM];
9375
//              iqentry_insln[nn]  <= bus[`IB_LN];
9376
`ifndef INLINE_DECODE
9377
        if (iqentry_insln[nn] != bus[`IB_LN]) begin
9378
                $display("Insn length mismatch.");
9379
                $stop;
9380
        end
9381
`endif
9382
        iqentry_cmp      [nn]  <= bus[`IB_CMP];
9383
        iqentry_tlb  [nn]  <= bus[`IB_TLB];
9384
        iqentry_sz   [nn]  <= bus[`IB_SZ];
9385
        iqentry_jal      [nn]  <= bus[`IB_JAL];
9386
        iqentry_ret  [nn]  <= bus[`IB_RET];
9387
        iqentry_irq  [nn]  <= bus[`IB_IRQ];
9388
        iqentry_brk      [nn]  <= bus[`IB_BRK];
9389
        iqentry_rti  [nn]  <= bus[`IB_RTI];
9390
        iqentry_bt   [nn]  <= bus[`IB_BT];
9391
        iqentry_alu  [nn]  <= bus[`IB_ALU];
9392
        iqentry_alu0 [nn]  <= bus[`IB_ALU0];
9393
        iqentry_fpu  [nn]  <= bus[`IB_FPU];
9394
        iqentry_fc   [nn]  <= bus[`IB_FC];
9395
        iqentry_canex[nn]  <= bus[`IB_CANEX];
9396
        iqentry_loadv[nn]  <= bus[`IB_LOADV];
9397
        iqentry_load [nn]  <= bus[`IB_LOAD];
9398 61 robfinch
        iqentry_loadseg[nn]<= bus[`IB_LOADSEG];
9399 60 robfinch
        iqentry_preload[nn]<= bus[`IB_PRELOAD];
9400
        iqentry_store[nn]  <= bus[`IB_STORE];
9401
        iqentry_push [nn]  <= bus[`IB_PUSH];
9402
        iqentry_oddball[nn] <= bus[`IB_ODDBALL];
9403
        iqentry_memsz[nn]  <= bus[`IB_MEMSZ];
9404
        iqentry_mem  [nn]  <= bus[`IB_MEM];
9405
        iqentry_memndx[nn] <= bus[`IB_MEMNDX];
9406
        iqentry_rmw  [nn]  <= bus[`IB_RMW];
9407
        iqentry_memdb[nn]  <= bus[`IB_MEMDB];
9408
        iqentry_memsb[nn]  <= bus[`IB_MEMSB];
9409
        iqentry_shft [nn]  <= bus[`IB_SHFT];    // 48 bit shift instructions
9410
        iqentry_sei      [nn]    <= bus[`IB_SEI];
9411
        iqentry_aq   [nn]  <= bus[`IB_AQ];
9412
        iqentry_rl   [nn]  <= bus[`IB_RL];
9413
        iqentry_jmp  [nn]  <= bus[`IB_JMP];
9414
        iqentry_br   [nn]  <= bus[`IB_BR];
9415
        iqentry_sync [nn]  <= bus[`IB_SYNC];
9416
        iqentry_fsync[nn]  <= bus[`IB_FSYNC];
9417
        iqentry_rfw  [nn]  <= bus[`IB_RFW];
9418
        iqentry_we   [nn]  <= bus[`IB_WE];
9419
end
9420
endtask
9421
 
9422
task setinsn;
9423
input [`QBITS] nn;
9424
input [4:0] id;
9425
input v;
9426
input [143:0] bus;
9427
begin
9428
  if (iqentry_iv[nn] == `INV && iqentry_is[nn] == id && iqentry_v[nn] == `VAL && v == `VAL)
9429
        setinsn1(nn,bus);
9430
end
9431
endtask
9432
 
9433
task a1_vs;
9434
begin
9435
        // if there is not an overlapping write to the register file.
9436
        if (Ra1s != Rt0s || !fetchbuf0_rfw) begin
9437
                iqentry_a1_v [tail1] <= regIsValid[Ra1s];
9438
                iqentry_a1_s [tail1] <= rf_source [Ra1s];
9439
        end
9440
        else begin
9441
                iqentry_a1_v [tail1] <= `INV;
9442
                iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
9443
        end
9444
end
9445
endtask
9446
 
9447
task a2_vs;
9448
begin
9449
        // if there is not an overlapping write to the register file.
9450
        if (Rb1s != Rt0s || !fetchbuf0_rfw) begin
9451
                iqentry_a2_v [tail1] <= regIsValid[Rb1s];
9452
                iqentry_a2_s [tail1] <= rf_source [Rb1s];
9453
        end
9454
        else begin
9455
                iqentry_a2_v [tail1] <= `INV;
9456
                iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
9457
        end
9458
end
9459
endtask
9460
 
9461
task a3_vs;
9462
begin
9463
        // if there is not an overlapping write to the register file.
9464
        if (Rc1s != Rt0s || !fetchbuf0_rfw) begin
9465
                iqentry_a3_v [tail1] <= regIsValid[Rc1s];
9466
                iqentry_a3_s [tail1] <= rf_source [Rc1s];
9467
        end
9468
        else begin
9469
                iqentry_a3_v [tail1] <= `INV;
9470
                iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
9471
        end
9472
end
9473
endtask
9474
 
9475
task enque0x;
9476
begin
9477
        if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
9478
                vqe0 <= vqe0 + 4'd1;
9479
                if (IsVCmprss(fetchbuf0_instr)) begin
9480
                        if (vm[fetchbuf0_instr[25:23]][vqe0])
9481
                        vqet0 <= vqet0 + 4'd1;
9482
                end
9483
                else
9484
                        vqet0 <= vqet0 + 4'd1;
9485
                if (vqe0 >= vl-2)
9486
                        nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
9487
                enque0(tail0, fetchbuf0_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, vqe0);
9488
                iq_ctr = iq_ctr + 4'd1;
9489
                if (fetchbuf0_rfw) begin
9490
                        rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail0 };    // top bit indicates ALU/MEM bus
9491
                        rf_v[Rt0s] <= `INV;
9492
                end
9493
                if (canq2) begin
9494
                        if (vqe0 < vl-2) begin
9495
                                vqe0 <= vqe0 + 4'd2;
9496
                                if (IsVCmprss(fetchbuf0_instr)) begin
9497
                                        if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
9498
                                                vqet0 <= vqet0 + 4'd2;
9499
                                end
9500
                                else
9501
                                        vqet0 <= vqet0 + 4'd2;
9502
                                enque0(tail1, fetchbuf0_thrd ? maxsn[1] + 4'd2 : maxsn[0]+4'd2, vqe0 + 6'd1);
9503
                                iq_ctr = iq_ctr + 4'd2;
9504
                                if (fetchbuf0_rfw) begin
9505
                                        rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail1 };    // top bit indicates ALU/MEM bus
9506
                                        rf_v[Rt0s] <= `INV;
9507
                                end
9508
                        end
9509
                end
9510
        end
9511
        else begin
9512
                enque0(tail0, fetchbuf0_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, 6'd0);
9513
                iq_ctr = iq_ctr + 4'd1;
9514
                if (fetchbuf0_rfw) begin
9515
                        rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail0 };    // top bit indicates ALU/MEM bus
9516
                        rf_v[Rt0s] <= `INV;
9517
                end
9518
        end
9519
end
9520
endtask
9521
 
9522
// Enqueue fetchbuf0 onto the tail of the instruction queue
9523
task enque0;
9524
input [`QBITS] tail;
9525
input [`SNBITS] seqnum;
9526
input [5:0] venno;
9527
begin
9528 61 robfinch
        iqentry_exc[tail] <= `FLT_NONE;
9529 60 robfinch
`ifdef SUPPORT_DBG
9530
    if (dbg_imatchA)
9531
        iqentry_exc[tail] <= `FLT_DBG;
9532
    else if (dbg_ctrl[63])
9533
        iqentry_exc[tail] <= `FLT_SSM;
9534
`endif
9535
        iqentry_state[tail]    <= IQS_QUEUED;
9536
        iqentry_sn   [tail]    <=  seqnum;
9537
        iqentry_iv       [tail]    <=   `INV;
9538
        iqentry_is   [tail]    <= tail;
9539
        iqentry_thrd [tail]    <=   fetchbuf0_thrd;
9540
        iqentry_res  [tail]    <=    `ZERO;
9541
        iqentry_instr[tail]    <=    IsVLS(fetchbuf0_instr) ? (vm[fnM2(fetchbuf0_instr)] ? fetchbuf0_instr : `NOP_INSN) : fetchbuf0_instr;
9542
        iqentry_insln[tail]              <=  fetchbuf0_insln;
9543
        iqentry_fc   [tail]    <=  `INV;
9544
        iqentry_mem      [tail]          <=  `INV;
9545 61 robfinch
        iqentry_memissue[tail] <=  `INV;
9546 60 robfinch
        iqentry_alu      [tail]          <=  `INV;
9547
        iqentry_fpu      [tail]          <=  `INV;
9548
        iqentry_load [tail]              <=  `INV;
9549
        iqentry_pt   [tail]    <=  predict_taken0;
9550
// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
9551
// inherit the previous pc.
9552
//if (IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15] &&
9553
//   (IsBrk(iqentry_instr[idm1(tail)]) && !iqentry_instr[idm1(tail1)][15] && iqentry_v[idm1(tail)]))
9554
//   iqentry_pc   [tail]    <= iqentry_pc[idm1(tail)];
9555
//else
9556
         iqentry_pc   [tail] <= fetchbuf0_pc;
9557
        iqentry_rtop [tail]    <=   IsRtop(fetchbuf0_instr);
9558
        iqentry_tgt  [tail]    <=       Rt0;
9559
        iqentry_Ra   [tail]    <= Ra0;
9560
        iqentry_Rb   [tail]    <= Rb0;
9561
        iqentry_Rc   [tail]    <= Rc0;
9562
        iqentry_vl   [tail]    <=  vl;
9563
        iqentry_ven  [tail]    <=   venno;
9564
        iqentry_exc  [tail]    <=    `EXC_NONE;
9565
        iqentry_a1   [tail]    <=    rfoa0;
9566
        iqentry_a1_v [tail]    <=    Source1Valid(fetchbuf0_instr) | regIsValid[Ra0s];
9567
        iqentry_a1_s [tail]    <=    rf_source[Ra0s];
9568
        iqentry_a2   [tail]    <=    rfob0;
9569
        iqentry_a2_v [tail]    <=    Source2Valid(fetchbuf0_instr) | regIsValid[Rb0s];
9570
        iqentry_a2_s [tail]    <=    rf_source[Rb0s];
9571
        iqentry_a3   [tail]    <=    rfoc0;
9572
        iqentry_a3_v [tail]    <=    Source3Valid(fetchbuf0_instr) | regIsValid[Rc0s];
9573
        iqentry_a3_s [tail]    <=    rf_source[Rc0s];
9574
`ifdef INLINE_DECODE
9575
/* This decoding cannot be done here because it'll introduce a 1 cycle delay
9576
        id1_Rt <= Rt0[4:0];
9577
        id1_vl <= vl;
9578
        id1_ven <= venno;
9579
        id1_id <= tail;
9580
        id1_pt <= predict_taken0;
9581
        id1_thrd <= fetchbuf0_thrd;
9582
*/
9583
        setinsn1(tail,id1_bus);
9584
`endif
9585
end
9586
endtask
9587
 
9588
// Enque fetchbuf1. Fetchbuf1 might be the second instruction to queue so some
9589
// of this code checks to see which tail it is being queued on.
9590
task enque1;
9591
input [`QBITS] tail;
9592
input [`SNBITS] seqnum;
9593
input [5:0] venno;
9594
begin
9595
 iqentry_exc[tail] <= `FLT_NONE;
9596
`ifdef SUPPORT_DBG
9597
    if (dbg_imatchB)
9598
        iqentry_exc[tail] <= `FLT_DBG;
9599
    else if (dbg_ctrl[63])
9600
        iqentry_exc[tail] <= `FLT_SSM;
9601
`endif
9602
        iqentry_state[tail]    <= IQS_QUEUED;
9603
        iqentry_sn   [tail]    <=   seqnum;
9604
        iqentry_iv       [tail]    <=   `INV;
9605
        iqentry_is   [tail]    <= tail;
9606
        iqentry_thrd [tail]    <=   fetchbuf1_thrd;
9607
        iqentry_res  [tail]    <=   `ZERO;
9608
        iqentry_instr[tail]    <=   IsVLS(fetchbuf1_instr) ? (vm[fnM2(fetchbuf1_instr)] ? fetchbuf1_instr : `NOP_INSN) : fetchbuf1_instr;
9609
        iqentry_insln[tail]              <=  fetchbuf1_insln;
9610
        iqentry_fc   [tail]    <=  `INV;
9611
        iqentry_mem      [tail]          <=  `INV;
9612 61 robfinch
        iqentry_memissue[tail] <=  `INV;
9613 60 robfinch
        iqentry_alu      [tail]          <=  `INV;
9614
        iqentry_fpu      [tail]          <=  `INV;
9615
        iqentry_load [tail]              <=  `INV;
9616
        iqentry_pt   [tail]    <=  predict_taken1;
9617
// If queing 2nd instruction must read from first
9618
if (tail==tail1) begin
9619
    // If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
9620
    // inherit the previous pc.
9621
//    if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
9622
//        IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15])
9623
//       iqentry_pc   [tail]    <= fetchbuf0_pc;
9624
//    else
9625
                iqentry_pc   [tail] <= fetchbuf1_pc;
9626
end
9627
else begin
9628
    // If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
9629
    // inherit the previous pc.
9630
//    if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
9631
//       (IsBrk(iqentry_instr[idp7(tail)]) && !iqentry_instr[idm1(tail)][15] && iqentry_v[idm1(tail)]))
9632
//       iqentry_pc   [tail]    <= iqentry_pc[idm1(tail)];
9633
//    else
9634
                iqentry_pc   [tail] <= fetchbuf1_pc;
9635
end
9636
        iqentry_rtop [tail]    <=   IsRtop(fetchbuf1_instr);
9637
        iqentry_tgt  [tail]    <= Rt1;
9638
        iqentry_Ra   [tail]    <= Ra1;
9639
        iqentry_Rb   [tail]    <= Rb1;
9640
        iqentry_Rc   [tail]    <= Rc1;
9641
        iqentry_vl   [tail]    <=  vl;
9642
        iqentry_ven  [tail]    <=   venno;
9643
        iqentry_exc  [tail]    <=   `EXC_NONE;
9644
        iqentry_a1   [tail]    <=       rfoa1;
9645
        iqentry_a1_v [tail]    <=       Source1Valid(fetchbuf1_instr) | regIsValid[Ra1s];
9646
        iqentry_a1_s [tail]    <=       rf_source[Ra1s];
9647
        iqentry_a2   [tail]    <=       rfob1;
9648
        iqentry_a2_v [tail]    <=       Source2Valid(fetchbuf1_instr) | regIsValid[Rb1s];
9649
        iqentry_a2_s [tail]    <=       rf_source[Rb1s];
9650
        iqentry_a3   [tail]    <=       rfoc1;
9651
        iqentry_a3_v [tail]    <=       Source3Valid(fetchbuf1_instr) | regIsValid[Rc1s];
9652
        iqentry_a3_s [tail]    <=       rf_source[Rc1s];
9653
`ifdef INLINE_DECODE
9654
/* This decoding cannot be done here because it'll introduce a 1 cycle delay
9655
        id2_Rt <= Rt1[4:0];
9656
        id2_vl <= vl;
9657
        id2_ven <= venno;
9658
        id2_id <= tail;
9659
        id2_pt <= predict_taken1;
9660
        id2_thrd <= fetchbuf1_thrd;
9661
*/
9662
        setinsn1(tail,id2_bus);
9663
`endif
9664
end
9665
endtask
9666
 
9667 61 robfinch
task exc;
9668
input [`QBITS] head;
9669
input thread;
9670
input [7:0] causecd;
9671
begin
9672
  excmiss <= TRUE;
9673
        excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol[thread],5'h00};
9674
  badaddr[{thread,2'd0}] <= iqentry_ma[head];
9675
  bad_instr[{thread,2'd0}] <= iqentry_instr[head];
9676 66 robfinch
  im_stack <= {im_stack[27:0],4'hF};
9677
`ifdef SUPPORT_SMT
9678
  excthrd <= iqentry_thrd[head];
9679
  ol_stack[thread] <= {ol_stack[thread][13:0],2'b00};
9680
  dl_stack[thread] <= {dl_stack[thread][13:0],2'b00};
9681 61 robfinch
  epc0[thread] <= iqentry_pc[head];
9682
  epc1[thread] <= epc0[thread];
9683
  epc2[thread] <= epc1[thread];
9684
  epc3[thread] <= epc2[thread];
9685
  epc4[thread] <= epc3[thread];
9686
  epc5[thread] <= epc4[thread];
9687
  epc6[thread] <= epc5[thread];
9688
  epc7[thread] <= epc6[thread];
9689
  epc8[thread] <= epc7[thread];
9690
  pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
9691
  rs_stack[thread] <= {rs_stack[thread][59:0],`EXC_RGS};
9692
  brs_stack[thread] <= {brs_stack[thread][59:0],`EXC_RGS};
9693
  cause[{thread,2'd0}] <= {8'd0,causecd};
9694
  mstatus[thread][5:4] <= 2'd0;
9695
  mstatus[thread][13:6] <= 8'h00;
9696
  mstatus[thread][19:14] <= `EXC_RGS;
9697
`else
9698
  excthrd <= 1'b0;
9699 66 robfinch
  ol_stack <= {ol_stack[13:0],2'b00};
9700
  dl_stack <= {dl_stack[13:0],2'b00};
9701 61 robfinch
  epc0 <= iqentry_pc[head];
9702
  epc1 <= epc0;
9703
  epc2 <= epc1;
9704
  epc3 <= epc2;
9705
  epc4 <= epc3;
9706
  epc5 <= epc4;
9707
  epc6 <= epc5;
9708
  epc7 <= epc6;
9709
  epc8 <= epc7;
9710
  pl_stack <= {pl_stack[55:0],cpl};
9711
  rs_stack <= {rs_stack[59:0],`EXC_RGS};
9712
  brs_stack <= {rs_stack[59:0],`EXC_RGS};
9713
  cause[3'd0] <= {8'd0,causecd};
9714
  mstatus[5:4] <= 2'd0;
9715
  mstatus[13:6] <= 8'h00;
9716
  mstatus[19:14] <= `EXC_RGS;
9717
`endif
9718
        wb_en <= `TRUE;
9719
  sema[0] <= 1'b0;
9720
  ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
9721
`ifdef SUPPORT_DBG
9722
  dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
9723
  dbg_ctrl[63] <= FALSE;
9724
`endif
9725
end
9726
endtask
9727
 
9728 60 robfinch
// This task takes care of commits for things other than the register file.
9729
task oddball_commit;
9730
input v;
9731
input [`QBITS] head;
9732
input [1:0] which;
9733
reg thread;
9734
begin
9735
    thread = iqentry_thrd[head];
9736
    if (v) begin
9737
        if (|iqentry_exc[head]) begin
9738 61 robfinch
                exc(head,thread,iqentry_exc[head]);
9739 60 robfinch
        end
9740
        else
9741
        case(iqentry_instr[head][`INSTRUCTION_OP])
9742
        `BRK:
9743
                        // BRK is treated as a nop unless it's a software interrupt or a
9744
                        // hardware interrupt at a higher priority than the current priority.
9745
            if ((|iqentry_instr[head][25:21]) || iqentry_instr[head][20:17] > im) begin
9746
                    excmiss <= TRUE;
9747 66 robfinch
              im_stack <= {im_stack[27:0],4'hF};
9748 60 robfinch
`ifdef SUPPORT_SMT
9749 66 robfinch
              ol_stack[thread] <= {ol_stack[thread][13:0],2'b00};
9750
              dl_stack[thread] <= {dl_stack[thread][13:0],2'b00};
9751 60 robfinch
                        excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol[thread],5'h00};
9752
                        excthrd <= iqentry_thrd[head];
9753
              epc0[thread] <= iqentry_pc[head] + {iqentry_instr[head][25:21],1'b0};
9754
              epc1[thread] <= epc0[thread];
9755
              epc2[thread] <= epc1[thread];
9756
              epc3[thread] <= epc2[thread];
9757
              epc4[thread] <= epc3[thread];
9758
              epc5[thread] <= epc4[thread];
9759
              epc6[thread] <= epc5[thread];
9760
              epc7[thread] <= epc6[thread];
9761
              epc8[thread] <= epc7[thread];
9762
              pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
9763
              rs_stack[thread] <= {rs_stack[thread][59:0],`BRK_RGS};
9764
              brs_stack[thread] <= {brs_stack[thread][59:0],`BRK_RGS};
9765
              cause[{thread,2'd0}] <= iqentry_res[head][7:0];
9766
              mstatus[thread][5:4] <= 2'd0;
9767
              mstatus[thread][13:6] <= 8'h00;
9768
              // For hardware interrupts only, set a new mask level. Setting a
9769
              // new mask level will effectively prevent subsequent brks that
9770
              // are streaming from an interrupt from being processed.
9771
              // Select register set according to interrupt level
9772
              if (iqentry_instr[head][25:21]==5'd0) begin
9773
                mstatus[thread][ 3: 0] <= iqentry_instr[head][20:17];
9774
                mstatus[thread][31:28] <= iqentry_instr[head][20:17];
9775
                mstatus[thread][19:14] <= {2'b0,iqentry_instr[head][20:17]};
9776
                rs_stack[thread][5:0] <= {2'b0,iqentry_instr[head][20:17]};
9777
                brs_stack[thread][5:0] <= {2'b0,iqentry_instr[head][20:17]};
9778
              end
9779
              else begin
9780
                mstatus[thread][19:14] <= `BRK_RGS;
9781
                rs_stack[thread][5:0] <= `BRK_RGS;
9782
                brs_stack[thread][5:0] <= `BRK_RGS;
9783
              end
9784
`else
9785 66 robfinch
              ol_stack <= {ol_stack[13:0],2'b00};
9786
              dl_stack <= {dl_stack[13:0],2'b00};
9787 60 robfinch
                        excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol,5'h00};
9788
                        excthrd <= 1'b0;
9789
              epc0 <= iqentry_pc[head] + {iqentry_instr[head][25:21],1'b0};
9790
              epc1 <= epc0;
9791
              epc2 <= epc1;
9792
              epc3 <= epc2;
9793
              epc4 <= epc3;
9794
              epc5 <= epc4;
9795
              epc6 <= epc5;
9796
              epc7 <= epc6;
9797
              epc8 <= epc7;
9798
              pl_stack <= {pl_stack[55:0],cpl};
9799
              rs_stack <= {rs_stack[59:0],`BRK_RGS};
9800
              brs_stack <= {brs_stack[59:0],`BRK_RGS};
9801
              cause[3'd0] <= iqentry_res[head][7:0];
9802
              mstatus[5:4] <= 2'd0;
9803
              mstatus[13:6] <= 8'h00;
9804
              // For hardware interrupts only, set a new mask level. Setting a
9805
              // new mask level will effectively prevent subsequent brks that
9806
              // are streaming from an interrupt from being processed.
9807
              // Select register set according to interrupt level
9808
              if (iqentry_instr[head][25:21]==5'd0) begin
9809
                mstatus[ 3: 0] <= iqentry_instr[head][20:17];
9810
                mstatus[31:28] <= iqentry_instr[head][20:17];
9811
                mstatus[19:14] <= {2'b0,iqentry_instr[head][20:17]};
9812
                rs_stack[5:0] <= {2'b0,iqentry_instr[head][20:17]};
9813
                brs_stack[5:0] <= {2'b0,iqentry_instr[head][20:17]};
9814
              end
9815
              else begin
9816
                mstatus[19:14] <= `BRK_RGS;
9817
                rs_stack[5:0] <= `BRK_RGS;
9818
                brs_stack[5:0] <= `BRK_RGS;
9819
              end
9820
`endif
9821
              sema[0] <= 1'b0;
9822
              ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
9823
`ifdef SUPPORT_DBG
9824
              dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
9825
              dbg_ctrl[63] <= FALSE;
9826
`endif
9827
            end
9828
        `IVECTOR:
9829
            casez(iqentry_tgt[head])
9830
            8'b00100???:  vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
9831
            8'b00101111:  vl <= iqentry_res[head];
9832
            default:    ;
9833
            endcase
9834
        `R2:
9835
            case(iqentry_instr[head][`INSTRUCTION_S2])
9836
            `R1:        case(iqentry_instr[head][20:16])
9837
                        `CHAIN_OFF:     cr0[18] <= 1'b0;
9838
                        `CHAIN_ON:      cr0[18] <= 1'b1;
9839
                        //`SETWB:               wbrcd[pcr[5:0]] <= 1'b1;
9840
                        default:        ;
9841
                                endcase
9842
            `VMOV:  casez(iqentry_tgt[head])
9843
                    12'b1111111_00???:  vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
9844
                    12'b1111111_01111:  vl <= iqentry_res[head];
9845
                    default:    ;
9846
                    endcase
9847
`ifdef SUPPORT_SMT
9848
            `SEI:   mstatus[thread][3:0] <= iqentry_res[head][3:0];   // S1
9849
`else
9850
            `SEI:   mstatus[3:0] <= iqentry_res[head][3:0];   // S1
9851
`endif
9852
            `RTI:   begin
9853
                            excmiss <= TRUE;
9854 61 robfinch
                        excthrd <= thread;
9855
                                                excmisspc <= iqentry_ma[head];
9856 60 robfinch
`ifdef SUPPORT_SMT
9857 61 robfinch
//                      excmisspc <= epc0[thread];
9858 60 robfinch
                        mstatus[thread][3:0] <= im_stack[thread][3:0];
9859
                        mstatus[thread][5:4] <= ol_stack[thread][1:0];
9860
                        mstatus[thread][21:20] <= dl_stack[thread][1:0];
9861
                        mstatus[thread][13:6] <= pl_stack[thread][7:0];
9862
                        mstatus[thread][19:14] <= rs_stack[thread][5:0];
9863
                        im_stack[thread] <= {4'd15,im_stack[thread][31:4]};
9864
                        ol_stack[thread] <= {2'd0,ol_stack[thread][15:2]};
9865
                        dl_stack[thread] <= {2'd0,dl_stack[thread][15:2]};
9866
                        pl_stack[thread] <= {8'h00,pl_stack[thread][63:8]};
9867
                        rs_stack[thread] <= {6'h00,rs_stack[thread][59:6]};
9868
                        brs_stack[thread] <= {6'h00,brs_stack[thread][59:6]};
9869
                epc0[thread] <= epc1[thread];
9870
                epc1[thread] <= epc2[thread];
9871
                epc2[thread] <= epc3[thread];
9872
                epc3[thread] <= epc4[thread];
9873
                epc4[thread] <= epc5[thread];
9874
                epc5[thread] <= epc6[thread];
9875
                epc6[thread] <= epc7[thread];
9876
                epc7[thread] <= epc8[thread];
9877
                epc8[thread] <= {tvec[0][AMSB:8], 1'b0, ol[thread], 5'h0};
9878
`else
9879 61 robfinch
//                      excmisspc <= epc0;
9880 60 robfinch
                        mstatus[3:0] <= im_stack[3:0];
9881
                        mstatus[5:4] <= ol_stack[1:0];
9882
                        mstatus[21:20] <= dl_stack[1:0];
9883
                        mstatus[13:6] <= pl_stack[7:0];
9884
                        mstatus[19:14] <= rs_stack[5:0];
9885
                        im_stack <= {4'd15,im_stack[31:4]};
9886
                        ol_stack <= {2'd0,ol_stack[15:2]};
9887
                        dl_stack <= {2'd0,dl_stack[15:2]};
9888
                        pl_stack <= {8'h00,pl_stack[63:8]};
9889
                        rs_stack <= {6'h00,rs_stack[59:6]};
9890
                        brs_stack <= {6'h00,brs_stack[59:6]};
9891
                epc0 <= epc1;
9892
                epc1 <= epc2;
9893
                epc2 <= epc3;
9894
                epc3 <= epc4;
9895
                epc4 <= epc5;
9896
                epc5 <= epc6;
9897
                epc6 <= epc7;
9898
                epc7 <= epc8;
9899
                epc8 <= {tvec[0][AMSB:8], 1'b0, ol, 5'h0};
9900
`endif
9901
                sema[0] <= 1'b0;
9902
                sema[iqentry_res[head][5:0]] <= 1'b0;
9903
                vqe0  <= ve_hold[ 5: 0];
9904
                vqet0 <= ve_hold[21:16];
9905
                vqe1  <= ve_hold[37:32];
9906
                vqet1 <= ve_hold[53:48];
9907
`ifdef SUPPORT_DBG
9908
                      dbg_ctrl[62:55] <= {FALSE,dbg_ctrl[62:56]};
9909
                      dbg_ctrl[63] <= dbg_ctrl[55];
9910
`endif
9911
              end
9912
            default: ;
9913
            endcase
9914
        `MEMNDX:
9915
            case(iqentry_instr[head][`INSTRUCTION_S2])
9916
            `CACHEX:
9917
                    case(iqentry_instr[head][22:18])
9918 66 robfinch
                                            5'h02:      begin invicl <= TRUE; invlineAddr <= {ASID,iqentry_res[head]}; end
9919 60 robfinch
                    5'h03:  invic <= TRUE;
9920
                    5'h10:  cr0[30] <= FALSE;
9921
                    5'h11:  cr0[30] <= TRUE;
9922
                    default:    ;
9923
                    endcase
9924
            default: ;
9925
            endcase
9926
        `CSRRW:
9927
                        begin
9928
                        write_csr(iqentry_instr[head][31:18],iqentry_a1[head],thread);
9929
                        end
9930
        `REX:
9931
`ifdef SUPPORT_SMT
9932
            // Can only redirect to a lower level
9933
            if (ol[thread] < iqentry_instr[head][14:13]) begin
9934
                mstatus[thread][5:4] <= iqentry_instr[head][14:13];
9935
                badaddr[{thread,iqentry_instr[head][14:13]}] <= badaddr[{thread,ol[thread]}];
9936
                bad_instr[{thread,iqentry_instr[head][14:13]}] <= bad_instr[{thread,ol[thread]}];
9937
                cause[{thread,iqentry_instr[head][14:13]}] <= cause[{thread,ol[thread]}];
9938
                mstatus[thread][13:6] <= iqentry_instr[head][25:18] | iqentry_a1[head][7:0];
9939
            end
9940
`else
9941
            if (ol < iqentry_instr[head][14:13]) begin
9942
                mstatus[5:4] <= iqentry_instr[head][14:13];
9943
                badaddr[{1'b0,iqentry_instr[head][14:13]}] <= badaddr[{1'b0,ol}];
9944
                bad_instr[{1'b0,iqentry_instr[head][14:13]}] <= bad_instr[{1'b0,ol}];
9945
                cause[{1'b0,iqentry_instr[head][14:13]}] <= cause[{1'b0,ol}];
9946
                mstatus[13:6] <= iqentry_instr[head][25:18] | iqentry_a1[head][7:0];
9947
            end
9948
`endif
9949
        `CACHE:
9950
            case(iqentry_instr[head][17:13])
9951 66 robfinch
            5'h02:      begin invicl <= TRUE; invlineAddr <= {ASID,iqentry_res[head]}; end
9952 60 robfinch
            5'h03:  invic <= TRUE;
9953
            5'h10:  cr0[30] <= FALSE;
9954
            5'h11:  cr0[30] <= TRUE;
9955
            default:    ;
9956
            endcase
9957
        `FLOAT:
9958
            case(iqentry_instr[head][`INSTRUCTION_S2])
9959
            `FRM: begin
9960
                                fp_rm <= iqentry_res[head][2:0];
9961
                                end
9962
            `FCX:
9963
                begin
9964
                    fp_sx <= fp_sx & ~iqentry_res[head][5];
9965
                    fp_inex <= fp_inex & ~iqentry_res[head][4];
9966
                    fp_dbzx <= fp_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
9967
                    fp_underx <= fp_underx & ~iqentry_res[head][2];
9968
                    fp_overx <= fp_overx & ~iqentry_res[head][1];
9969
                    fp_giopx <= fp_giopx & ~iqentry_res[head][0];
9970
                    fp_infdivx <= fp_infdivx & ~iqentry_res[head][0];
9971
                    fp_zerozerox <= fp_zerozerox & ~iqentry_res[head][0];
9972
                    fp_subinfx   <= fp_subinfx   & ~iqentry_res[head][0];
9973
                    fp_infzerox  <= fp_infzerox  & ~iqentry_res[head][0];
9974
                    fp_NaNCmpx   <= fp_NaNCmpx   & ~iqentry_res[head][0];
9975
                    fp_swtx <= 1'b0;
9976
                end
9977
            `FDX:
9978
                begin
9979
                    fp_inexe <= fp_inexe     & ~iqentry_res[head][4];
9980
                    fp_dbzxe <= fp_dbzxe     & ~iqentry_res[head][3];
9981
                    fp_underxe <= fp_underxe & ~iqentry_res[head][2];
9982
                    fp_overxe <= fp_overxe   & ~iqentry_res[head][1];
9983
                    fp_invopxe <= fp_invopxe & ~iqentry_res[head][0];
9984
                end
9985
            `FEX:
9986
                begin
9987
                    fp_inexe <= fp_inexe     | iqentry_res[head][4];
9988
                    fp_dbzxe <= fp_dbzxe     | iqentry_res[head][3];
9989
                    fp_underxe <= fp_underxe | iqentry_res[head][2];
9990
                    fp_overxe <= fp_overxe   | iqentry_res[head][1];
9991
                    fp_invopxe <= fp_invopxe | iqentry_res[head][0];
9992
                end
9993
            default:
9994
                begin
9995
                    // 31 to 29 is rounding mode
9996
                    // 28 to 24 are exception enables
9997
                    // 23 is nsfp
9998
                    // 22 is a fractie
9999
                    fp_fractie <= iqentry_ares[head][22];
10000
                    fp_raz <= iqentry_ares[head][21];
10001
                    // 20 is a 0
10002
                    fp_neg <= iqentry_ares[head][19];
10003
                    fp_pos <= iqentry_ares[head][18];
10004
                    fp_zero <= iqentry_ares[head][17];
10005
                    fp_inf <= iqentry_ares[head][16];
10006
                    // 15 swtx
10007
                    // 14 
10008
                    fp_inex <= fp_inex | (fp_inexe & iqentry_ares[head][14]);
10009
                    fp_dbzx <= fp_dbzx | (fp_dbzxe & iqentry_ares[head][13]);
10010
                    fp_underx <= fp_underx | (fp_underxe & iqentry_ares[head][12]);
10011
                    fp_overx <= fp_overx | (fp_overxe & iqentry_ares[head][11]);
10012
                    //fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
10013
                    //fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
10014
                    //
10015
                    fp_cvtx <= fp_cvtx |  (fp_giopxe & iqentry_ares[head][7]);
10016
                    fp_sqrtx <= fp_sqrtx |  (fp_giopxe & iqentry_ares[head][6]);
10017
                    fp_NaNCmpx <= fp_NaNCmpx |  (fp_giopxe & iqentry_ares[head][5]);
10018
                    fp_infzerox <= fp_infzerox |  (fp_giopxe & iqentry_ares[head][4]);
10019
                    fp_zerozerox <= fp_zerozerox |  (fp_giopxe & iqentry_ares[head][3]);
10020
                    fp_infdivx <= fp_infdivx | (fp_giopxe & iqentry_ares[head][2]);
10021
                    fp_subinfx <= fp_subinfx | (fp_giopxe & iqentry_ares[head][1]);
10022
                    fp_snanx <= fp_snanx | (fp_giopxe & iqentry_ares[head][0]);
10023
 
10024
                end
10025
            endcase
10026
        default:    ;
10027
        endcase
10028
        // Once the flow control instruction commits, NOP it out to allow
10029
        // pending stores to be issued.
10030
        iqentry_instr[head][5:0] <= `NOP;
10031
    end
10032
end
10033
endtask
10034
 
10035
// CSR access tasks
10036
// This task does not work. Possibly because the always block @* doesn't
10037
// evaluate into the task to see which signals are changing. The following
10038
// code is simply included as an always block above.
10039
task read_csr;
10040
input [11:0] csrno;
10041
output [63:0] dat;
10042
input thread;
10043
begin
10044
`ifdef SUPPORT_SMT
10045
    if (csrno[11:10] >= ol[thread])
10046
`else
10047
    if (csrno[11:10] >= ol)
10048
`endif
10049
    casez(csrno[9:0])
10050
    `CSR_CR0:       dat <= cr0;
10051
    `CSR_HARTID:    dat <= hartid;
10052
    `CSR_TICK:      dat <= tick;
10053
    `CSR_PCR:       dat <= pcr;
10054
    `CSR_PCR2:      dat <= pcr2;
10055
    `CSR_PMR:                           dat <= pmr;
10056
    `CSR_WBRCD:         dat <= wbrcd;
10057
    `CSR_SEMA:      dat <= sema;
10058
    `CSR_KEYS:                  dat <= keys;
10059
    `CSR_TCB:           dat <= tcb;
10060
    `CSR_FSTAT:     dat <= {fp_rgs,fp_status};
10061
`ifdef SUPPORT_DBG
10062
    `CSR_DBAD0:     dat <= dbg_adr0;
10063
    `CSR_DBAD1:     dat <= dbg_adr1;
10064
    `CSR_DBAD2:     dat <= dbg_adr2;
10065
    `CSR_DBAD3:     dat <= dbg_adr3;
10066
    `CSR_DBCTRL:    dat <= dbg_ctrl;
10067
    `CSR_DBSTAT:    dat <= dbg_stat;
10068
`endif
10069
    `CSR_CAS:       dat <= cas;
10070
    `CSR_TVEC:      dat <= tvec[csrno[2:0]];
10071
    `CSR_BADADR:    dat <= badaddr[{thread,csrno[11:10]}];
10072
    `CSR_BADINSTR:      dat <= bad_instr[{thread,csrno[11:10]}];
10073
    `CSR_CAUSE:     dat <= {48'd0,cause[{thread,csrno[11:10]}]};
10074
`ifdef SUPPORT_SMT
10075
    `CSR_IM_STACK:      dat <= im_stack[thread];
10076 66 robfinch
    `CSR_OL_STACK:      dat <= {16'h0,dl_stack[thread],16'h0,ol_stack[thread]};
10077 60 robfinch
    `CSR_PL_STACK:      dat <= pl_stack[thread];
10078
    `CSR_RS_STACK:      dat <= rs_stack[thread];
10079
    `CSR_STATUS:    dat <= mstatus[thread][63:0];
10080
    `CSR_EPC0:      dat <= epc0[thread];
10081
    `CSR_EPC1:      dat <= epc1[thread];
10082
    `CSR_EPC2:      dat <= epc2[thread];
10083
    `CSR_EPC3:      dat <= epc3[thread];
10084
    `CSR_EPC4:      dat <= epc4[thread];
10085
    `CSR_EPC5:      dat <= epc5[thread];
10086
    `CSR_EPC6:      dat <= epc6[thread];
10087
    `CSR_EPC7:      dat <= epc7[thread];
10088
`else
10089
    `CSR_IM_STACK:      dat <= im_stack;
10090 66 robfinch
    `CSR_ODL_STACK:     dat <= {16'h0,dl_stack,16'h0,ol_stack};
10091 60 robfinch
    `CSR_PL_STACK:      dat <= pl_stack;
10092
    `CSR_RS_STACK:      dat <= rs_stack;
10093
    `CSR_STATUS:    dat <= mstatus[63:0];
10094
    `CSR_EPC0:      dat <= epc0;
10095
    `CSR_EPC1:      dat <= epc1;
10096
    `CSR_EPC2:      dat <= epc2;
10097
    `CSR_EPC3:      dat <= epc3;
10098
    `CSR_EPC4:      dat <= epc4;
10099
    `CSR_EPC5:      dat <= epc5;
10100
    `CSR_EPC6:      dat <= epc6;
10101
    `CSR_EPC7:      dat <= epc7;
10102
`endif
10103
    `CSR_CODEBUF:   dat <= codebuf[csrno[5:0]];
10104
`ifdef SUPPORT_BBMS
10105
                `CSR_TB:                        dat <= tb;
10106
                `CSR_CBL:                       dat <= cbl;
10107
                `CSR_CBU:                       dat <= cbu;
10108
                `CSR_RO:                        dat <= ro;
10109
                `CSR_DBL:                       dat <= dbl;
10110
                `CSR_DBU:                       dat <= dbu;
10111
                `CSR_SBL:                       dat <= sbl;
10112
                `CSR_SBU:                       dat <= sbu;
10113
                `CSR_ENU:                       dat <= en;
10114
`endif
10115
    `CSR_Q_CTR:         dat <= iq_ctr;
10116
    `CSR_BM_CTR:        dat <= bm_ctr;
10117
    `CSR_ICL_CTR:       dat <= icl_ctr;
10118
    `CSR_IRQ_CTR:       dat <= irq_ctr;
10119
    `CSR_TIME:          dat <= wc_times;
10120
    `CSR_INFO:
10121
                    case(csrno[3:0])
10122
                    4'd0:   dat <= "Finitron";  // manufacturer
10123
                    4'd1:   dat <= "        ";
10124
                    4'd2:   dat <= "64 bit  ";  // CPU class
10125
                    4'd3:   dat <= "        ";
10126
                    4'd4:   dat <= "FT64    ";  // Name
10127
                    4'd5:   dat <= "        ";
10128
                    4'd6:   dat <= 64'd1;       // model #
10129
                    4'd7:   dat <= 64'd1;       // serial number
10130
                    4'd8:   dat <= {32'd16384,32'd16384};   // cache sizes instruction,data
10131
                    4'd9:   dat <= 64'd0;
10132
                    default:    dat <= 64'd0;
10133
                    endcase
10134
    default:    begin
10135
                        $display("Unsupported CSR:%h",csrno[10:0]);
10136
                        dat <= 64'hEEEEEEEEEEEEEEEE;
10137
                        end
10138
    endcase
10139
    else
10140
        dat <= 64'h0;
10141
end
10142
endtask
10143
 
10144
task write_csr;
10145
input [13:0] csrno;
10146
input [63:0] dat;
10147
input thread;
10148
begin
10149
`ifdef SUPPORT_SMT
10150
    if (csrno[11:10] >= ol[thread])
10151
`else
10152
    if (csrno[11:10] >= ol)
10153
`endif
10154
    case(csrno[13:12])
10155
    2'd1:   // CSRRW
10156
        casez(csrno[9:0])
10157
        `CSR_CR0:       cr0 <= dat;
10158
        `CSR_PCR:       pcr <= dat[31:0];
10159
        `CSR_PCR2:      pcr2 <= dat;
10160
        `CSR_PMR:       case(`NUM_IDU)
10161
                                                0,1:     pmr[0] <= 1'b1;
10162
                                                2:
10163
                                                        begin
10164
                                                                        if (dat[1:0]==2'b00)
10165
                                                                                pmr[1:0] <= 2'b01;
10166
                                                                        else
10167
                                                                                pmr[1:0] <= dat[1:0];
10168
                                                                        pmr[63:2] <= dat[63:2];
10169
                                                                end
10170
                                                3:
10171
                                                        begin
10172
                                                                        if (dat[2:0]==3'b000)
10173
                                                                                pmr[2:0] <= 3'b001;
10174
                                                                        else
10175
                                                                                pmr[2:0] <= dat[2:0];
10176
                                                                        pmr[63:3] <= dat[63:3];
10177
                                                                end
10178
                                                default:        pmr[0] <= 1'b1;
10179
                                                endcase
10180
        `CSR_WBRCD:             wbrcd <= dat;
10181
        `CSR_SEMA:      sema <= dat;
10182
        `CSR_KEYS:      keys <= dat;
10183
        `CSR_TCB:               tcb <= dat;
10184
        `CSR_FSTAT:             fpu_csr[37:32] <= dat[37:32];
10185
        `CSR_BADADR:    badaddr[{thread,csrno[11:10]}] <= dat;
10186
        `CSR_BADINSTR:  bad_instr[{thread,csrno[11:10]}] <= dat;
10187
        `CSR_CAUSE:     cause[{thread,csrno[11:10]}] <= dat[15:0];
10188
`ifdef SUPPORT_DBG
10189
        `CSR_DBAD0:     dbg_adr0 <= dat[AMSB:0];
10190
        `CSR_DBAD1:     dbg_adr1 <= dat[AMSB:0];
10191
        `CSR_DBAD2:     dbg_adr2 <= dat[AMSB:0];
10192
        `CSR_DBAD3:     dbg_adr3 <= dat[AMSB:0];
10193
        `CSR_DBCTRL:    dbg_ctrl <= dat;
10194
`endif
10195
        `CSR_CAS:       cas <= dat;
10196
        `CSR_TVEC:      tvec[csrno[2:0]] <= dat[31:0];
10197
`ifdef SUPPORT_SMT
10198
        `CSR_IM_STACK:  im_stack[thread] <= dat[31:0];
10199 66 robfinch
        `CSR_ODL_STACK: begin
10200 60 robfinch
                                                                        ol_stack[thread] <= dat[15:0];
10201
                                                                        dl_stack[thread] <= dat[31:16];
10202
                                                                        end
10203
        `CSR_PL_STACK:  pl_stack[thread] <= dat;
10204
        `CSR_RS_STACK:  rs_stack[thread] <= dat;
10205
        `CSR_STATUS:    mstatus[thread][63:0] <= dat;
10206
        `CSR_EPC0:      epc0[thread] <= dat;
10207
        `CSR_EPC1:      epc1[thread] <= dat;
10208
        `CSR_EPC2:      epc2[thread] <= dat;
10209
        `CSR_EPC3:      epc3[thread] <= dat;
10210
        `CSR_EPC4:      epc4[thread] <= dat;
10211
        `CSR_EPC5:      epc5[thread] <= dat;
10212
        `CSR_EPC6:      epc6[thread] <= dat;
10213
        `CSR_EPC7:      epc7[thread] <= dat;
10214
`else
10215
        `CSR_IM_STACK:  im_stack <= dat[31:0];
10216 66 robfinch
        `CSR_ODL_STACK: begin
10217 60 robfinch
                                                                        ol_stack <= dat[15:0];
10218 66 robfinch
                                                                        dl_stack <= dat[47:32];
10219 60 robfinch
                                                                        end
10220
        `CSR_PL_STACK:  pl_stack <= dat;
10221
        `CSR_RS_STACK:  rs_stack <= dat;
10222
        `CSR_STATUS:    mstatus[63:0] <= dat;
10223
        `CSR_EPC0:      epc0 <= dat;
10224
        `CSR_EPC1:      epc1 <= dat;
10225
        `CSR_EPC2:      epc2 <= dat;
10226
        `CSR_EPC3:      epc3 <= dat;
10227
        `CSR_EPC4:      epc4 <= dat;
10228
        `CSR_EPC5:      epc5 <= dat;
10229
        `CSR_EPC6:      epc6 <= dat;
10230
        `CSR_EPC7:      epc7 <= dat;
10231
`endif
10232
`ifdef SUPPORT_BBMS
10233
                                `CSR_TB:                        prg_base[brgs] <= dat;
10234
                                `CSR_CBL:                       cl_barrier[brgs] <= dat;
10235
                                `CSR_CBU:                       cu_barrier[brgs] <= dat;
10236
                                `CSR_RO:                        ro_barrier[brgs] <= dat;
10237
                                `CSR_DBL:                       dl_barrier[brgs] <= dat;
10238
                                `CSR_DBU:                       du_barrier[brgs] <= dat;
10239
                                `CSR_SBL:                       sl_barrier[brgs] <= dat;
10240
                                `CSR_SBU:                       su_barrier[brgs] <= dat;
10241
                                `CSR_ENU:                       en_barrier[brgs] <= dat;
10242
`endif
10243
                                `CSR_TIME:              begin
10244
                                                ld_time <= 6'h3f;
10245
                                                wc_time_dat <= dat;
10246
                                                end
10247
        `CSR_CODEBUF:   codebuf[csrno[5:0]] <= dat;
10248
        default:    ;
10249
        endcase
10250
    2'd2:   // CSRRS
10251
        case(csrno[9:0])
10252
        `CSR_CR0:       cr0 <= cr0 | dat;
10253
        `CSR_PCR:       pcr[31:0] <= pcr[31:0] | dat[31:0];
10254
        `CSR_PCR2:      pcr2 <= pcr2 | dat;
10255
        `CSR_PMR:                               pmr <= pmr | dat;
10256
        `CSR_WBRCD:             wbrcd <= wbrcd | dat;
10257
`ifdef SUPPORT_DBG
10258
        `CSR_DBCTRL:    dbg_ctrl <= dbg_ctrl | dat;
10259
`endif
10260
        `CSR_SEMA:      sema <= sema | dat;
10261
`ifdef SUPPORT_SMT
10262
        `CSR_STATUS:    mstatus[thread][63:0] <= mstatus[thread][63:0] | dat;
10263
`else
10264
        `CSR_STATUS:    mstatus[63:0] <= mstatus[63:0] | dat;
10265
`endif
10266
        default:    ;
10267
        endcase
10268
    2'd3:   // CSRRC
10269
        case(csrno[9:0])
10270
        `CSR_CR0:       cr0 <= cr0 & ~dat;
10271
        `CSR_PCR:       pcr <= pcr & ~dat;
10272
        `CSR_PCR2:      pcr2 <= pcr2 & ~dat;
10273
        `CSR_PMR:                       begin
10274
                                                                if (dat[1:0]==2'b11)
10275
                                                                        pmr[1:0] <= 2'b01;
10276
                                                                else
10277
                                                                        pmr[1:0] <= pmr[1:0] & ~dat[1:0];
10278
                                                                pmr[63:2] <= pmr[63:2] & ~dat[63:2];
10279
                                                                end
10280
        `CSR_WBRCD:             wbrcd <= wbrcd & ~dat;
10281
`ifdef SUPPORT_DBG
10282
        `CSR_DBCTRL:    dbg_ctrl <= dbg_ctrl & ~dat;
10283
`endif
10284
        `CSR_SEMA:      sema <= sema & ~dat;
10285
`ifdef SUPPORT_SMT
10286
        `CSR_STATUS:    mstatus[thread][63:0] <= mstatus[thread][63:0] & ~dat;
10287
`else
10288
        `CSR_STATUS:    mstatus[63:0] <= mstatus[63:0] & ~dat;
10289
`endif
10290
        default:    ;
10291
        endcase
10292
    default:    ;
10293
    endcase
10294
end
10295
endtask
10296
 
10297
task tDram0Issue;
10298
input [`QBITSP1] n;
10299
begin
10300 61 robfinch
        if (iqentry_state[n]==IQS_AGEN) begin
10301 60 robfinch
//      dramA_v <= `INV;
10302 61 robfinch
                dram0           <= `DRAMSLOT_BUSY;
10303
                dram0_id        <= { 1'b1, n[`QBITS] };
10304
                dram0_instr <= iqentry_instr[n];
10305
                dram0_rmw  <= iqentry_rmw[n];
10306
                dram0_preload <= iqentry_preload[n];
10307
                dram0_tgt       <= iqentry_tgt[n];
10308
                if (iqentry_imm[n] & iqentry_push[n])
10309
                        dram0_data <= iqentry_a0[n];
10310
                else
10311
                        dram0_data <= iqentry_a2[n];
10312
                dram0_addr      <= iqentry_ma[n];
10313
                dram0_unc   <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
10314
                dram0_memsize <= iqentry_memsz[n];
10315
                dram0_load <= iqentry_load[n];
10316
                dram0_loadseg <= iqentry_loadseg[n];
10317
                dram0_store <= iqentry_store[n];
10318 60 robfinch
`ifdef SUPPORT_SMT
10319 61 robfinch
                dram0_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
10320 60 robfinch
`else
10321 61 robfinch
                dram0_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
10322 60 robfinch
`endif
10323
        // Once the memory op is issued reset the a1_v flag.
10324
        // This will cause the a1 bus to look for new data from memory (a1_s is pointed to a memory bus)
10325
        // This is used for the load and compare instructions.
10326
        // must reset the a1 source too.
10327
        //iqentry_a1_v[n] <= `INV;
10328 61 robfinch
                iqentry_state[n] <= IQS_MEM;
10329
        end
10330 60 robfinch
end
10331
endtask
10332
 
10333
task tDram1Issue;
10334
input [`QBITSP1] n;
10335
begin
10336 61 robfinch
        if (iqentry_state[n]==IQS_AGEN) begin
10337
//      dramB_v <= `INV;
10338 60 robfinch
        dram1           <= `DRAMSLOT_BUSY;
10339
        dram1_id        <= { 1'b1, n[`QBITS] };
10340
        dram1_instr <= iqentry_instr[n];
10341
        dram1_rmw  <= iqentry_rmw[n];
10342
        dram1_preload <= iqentry_preload[n];
10343
        dram1_tgt       <= iqentry_tgt[n];
10344 61 robfinch
        if (iqentry_imm[n] & iqentry_push[n])
10345
                dram1_data <= iqentry_a0[n];
10346
        else
10347
                dram1_data <= iqentry_a2[n];
10348 60 robfinch
        dram1_addr      <= iqentry_ma[n];
10349
        //                   if (ol[iqentry_thrd[n]]==`OL_USER)
10350
        //                      dram1_seg   <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
10351
        //                   else
10352
        dram1_unc   <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
10353
        dram1_memsize <= iqentry_memsz[n];
10354
        dram1_load <= iqentry_load[n];
10355 61 robfinch
        dram1_loadseg <= iqentry_loadseg[n];
10356 60 robfinch
        dram1_store <= iqentry_store[n];
10357
`ifdef SUPPORT_SMT
10358
        dram1_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
10359
`else
10360
        dram1_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
10361
`endif
10362
        //iqentry_a1_v[n] <= `INV;
10363
        iqentry_state[n] <= IQS_MEM;
10364 61 robfinch
        end
10365 60 robfinch
end
10366
endtask
10367
 
10368
task tDram2Issue;
10369
input [`QBITSP1] n;
10370
begin
10371 61 robfinch
        if (iqentry_state[n]==IQS_AGEN) begin
10372
//      dramC_v <= `INV;
10373 60 robfinch
        dram2           <= `DRAMSLOT_BUSY;
10374
        dram2_id        <= { 1'b1, n[`QBITS] };
10375
        dram2_instr     <= iqentry_instr[n];
10376
        dram2_rmw  <= iqentry_rmw[n];
10377
        dram2_preload <= iqentry_preload[n];
10378
        dram2_tgt       <= iqentry_tgt[n];
10379 61 robfinch
        if (iqentry_imm[n] & iqentry_push[n])
10380
                dram2_data <= iqentry_a0[n];
10381
        else
10382
                dram2_data <= iqentry_a2[n];
10383 60 robfinch
        dram2_addr      <= iqentry_ma[n];
10384
        //                   if (ol[iqentry_thrd[n]]==`OL_USER)
10385
        //                      dram2_seg   <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
10386
        //                   else
10387
        dram2_unc   <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
10388
        dram2_memsize <= iqentry_memsz[n];
10389
        dram2_load <= iqentry_load[n];
10390 61 robfinch
        dram2_loadseg <= iqentry_loadseg[n];
10391 60 robfinch
        dram2_store <= iqentry_store[n];
10392
`ifdef SUPPORT_SMT
10393
        dram2_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
10394
`else
10395
        dram2_ol   <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
10396
`endif
10397
        //iqentry_a1_v[n] <= `INV;
10398
        iqentry_state[n] <= IQS_MEM;
10399 61 robfinch
        end
10400 60 robfinch
end
10401
endtask
10402
 
10403
task wb_nack;
10404
begin
10405
        cti_o <= 3'b000;
10406
        bte_o <= 2'b00;
10407
        cyc <= `LOW;
10408
        stb_o <= `LOW;
10409
        we <= `LOW;
10410
        sel_o <= 8'h00;
10411 61 robfinch
//      vadr <= 32'hCCCCCCCC;
10412 60 robfinch
end
10413
endtask
10414
 
10415
endmodule
10416
 
10417
 
10418
module decoder5 (num, out);
10419
input [4:0] num;
10420
output [31:1] out;
10421
reg [31:1] out;
10422
 
10423
always @(num)
10424
case (num)
10425
    5'd0 :      out <= 31'b0000000000000000000000000000000;
10426
    5'd1 :      out <= 31'b0000000000000000000000000000001;
10427
    5'd2 :      out <= 31'b0000000000000000000000000000010;
10428
    5'd3 :      out <= 31'b0000000000000000000000000000100;
10429
    5'd4 :      out <= 31'b0000000000000000000000000001000;
10430
    5'd5 :      out <= 31'b0000000000000000000000000010000;
10431
    5'd6 :      out <= 31'b0000000000000000000000000100000;
10432
    5'd7 :      out <= 31'b0000000000000000000000001000000;
10433
    5'd8 :      out <= 31'b0000000000000000000000010000000;
10434
    5'd9 :      out <= 31'b0000000000000000000000100000000;
10435
    5'd10:      out <= 31'b0000000000000000000001000000000;
10436
    5'd11:      out <= 31'b0000000000000000000010000000000;
10437
    5'd12:      out <= 31'b0000000000000000000100000000000;
10438
    5'd13:      out <= 31'b0000000000000000001000000000000;
10439
    5'd14:      out <= 31'b0000000000000000010000000000000;
10440
    5'd15:      out <= 31'b0000000000000000100000000000000;
10441
    5'd16:      out <= 31'b0000000000000001000000000000000;
10442
    5'd17:      out <= 31'b0000000000000010000000000000000;
10443
    5'd18:      out <= 31'b0000000000000100000000000000000;
10444
    5'd19:      out <= 31'b0000000000001000000000000000000;
10445
    5'd20:      out <= 31'b0000000000010000000000000000000;
10446
    5'd21:      out <= 31'b0000000000100000000000000000000;
10447
    5'd22:      out <= 31'b0000000001000000000000000000000;
10448
    5'd23:      out <= 31'b0000000010000000000000000000000;
10449
    5'd24:      out <= 31'b0000000100000000000000000000000;
10450
    5'd25:      out <= 31'b0000001000000000000000000000000;
10451
    5'd26:      out <= 31'b0000010000000000000000000000000;
10452
    5'd27:      out <= 31'b0000100000000000000000000000000;
10453
    5'd28:      out <= 31'b0001000000000000000000000000000;
10454
    5'd29:      out <= 31'b0010000000000000000000000000000;
10455
    5'd30:      out <= 31'b0100000000000000000000000000000;
10456
    5'd31:      out <= 31'b1000000000000000000000000000000;
10457
endcase
10458
 
10459
endmodule
10460
 
10461
module decoder6 (num, out);
10462
input [5:0] num;
10463
output [63:1] out;
10464
 
10465
wire [63:0] out1;
10466
 
10467
assign out1 = 64'd1 << num;
10468
assign out = out1[63:1];
10469
 
10470
endmodule
10471
 
10472
module decoder7 (num, out);
10473
input [6:0] num;
10474
output [127:1] out;
10475
 
10476
wire [127:0] out1;
10477
 
10478
assign out1 = 128'd1 << num;
10479
assign out = out1[127:1];
10480
 
10481
endmodule
10482
 
10483
module decoder8 (num, out);
10484
input [7:0] num;
10485
output [255:1] out;
10486
 
10487
wire [255:0] out1;
10488
 
10489
assign out1 = 256'd1 << num;
10490
assign out = out1[255:1];
10491
 
10492
endmodule
10493
 

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