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[/] [uart2bus/] [trunk/] [verilog/] [bench/] [tb_bin_uart2bus_top.v] - Blame information for rev 12

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1 2 motilito
//---------------------------------------------------------------------------------------
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// uart test bench   
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//
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//---------------------------------------------------------------------------------------
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`include "timescale.v"
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module test;
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//---------------------------------------------------------------------------------------
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// include uart tasks 
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`include "uart_tasks.v"
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// define if simulation should be binary or ascii 
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parameter BINARY_MODE = 1;
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// internal signal  
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reg clock;              // global clock 
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reg reset;              // global reset 
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reg [6:0] counter;
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//---------------------------------------------------------------------------------------
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// test bench implementation 
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// global signals generation  
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initial
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begin
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        counter = 0;
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        reset = 1;
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        #40 reset = 0;
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end
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// clock generator - 40MHz clock 
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always
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begin
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        #12 clock = 0;
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        #13 clock = 1;
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end
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// test bench dump variables 
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initial
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begin
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        $dumpfile("test.vcd");
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        //$dumpall;
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        $dumpvars(0, test);
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end
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//------------------------------------------------------------------
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// test bench transmitter and receiver 
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// uart transmit - test bench control 
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integer file;           // file handler index 
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integer char;           // character read from file 
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integer file_len;       // length of binary simulation file 
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integer byte_idx;       // byte index in binary mode simulation 
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integer tx_len;
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integer rx_len;
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reg new_rx_data;
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reg [7:0] tx_byte;
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initial
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begin
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        // defualt value of serial output 
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        serial_out = 1;
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        // wait for reset to de-assert 
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        while (reset) @ (posedge clock);
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        // wait for another 100 clock cycles before starting simulation 
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        repeat (100) @ (posedge clock);
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        // check simulation mode 
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        if (BINARY_MODE > 0)
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        begin
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                // binary mode simulation 
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                $display("Starting binary mode simulation");
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                // open binary command file 
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                file=$fopen("test.bin", "rb");
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                // in binary simulation mode the first two byte contain the file length (MSB first) 
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                file_len = $fgetc(file);
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                file_len = 256*file_len + $fgetc(file);
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                $display("File length: %d", file_len);
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                // send entire file to uart 
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                byte_idx = 0;
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                while (byte_idx < file_len)
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                begin
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                        // each "record" in the binary starts with two bytes: the first is the number 
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                        // of bytes to transmit and the second is the number of received bytes to wait 
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                        // for before transmitting the next command. 
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                        tx_len = $fgetc(file);
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                        rx_len = $fgetc(file);
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                        $display("Executing command with %d tx bytes and %d rx bytes", tx_len, rx_len);
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                        byte_idx = byte_idx + 2;
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                        // transmit command 
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                        while (tx_len > 0)
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                        begin
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                                // read next byte from file and transmit it 
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                                char = $fgetc(file);
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                                tx_byte = char;
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                                byte_idx = byte_idx + 1;
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                                send_serial(tx_byte, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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                                // update tx_len 
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                                tx_len = tx_len - 1;
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                        end
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                        // wait for received bytes 
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                        while (rx_len > 0)
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                        begin
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                                // one clock delay to allow new_rx_data to update 
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                                @(posedge new_rx_data) rx_len = rx_len - 1;
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                                // check if a new byte was received 
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                                if (new_rx_data)
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                                        rx_len = rx_len - 1;
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                        end
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                        $display("Command finished");
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                end
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        end
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        else
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        begin
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                // ascii mode simulation 
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                // open UART command file 
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                file=$fopen("test.txt", "rt");
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                // transmit the byte in the command file one by one 
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                char = $fgetc(file);
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                while (char >= 0) begin
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                        // transmit byte through UART 
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                        send_serial(char, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
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                        #200000;
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                        // read next byte from file 
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                        char = $fgetc(file);
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                end
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        end
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        // close input file 
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        $fclose(file);
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        // delay and finish 
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        #500000;
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        $finish;
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end
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// uart receive 
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initial
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begin
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        // default value for serial receiver and serial input 
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        serial_in = 1;
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        get_serial_data = 0;             // data received from get_serial task 
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        get_serial_status = 0;           // status of get_serial task  
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end
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// serial sniffer loop 
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always
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begin
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        // clear new_rx_data flag 
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        new_rx_data = 0;
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        // call serial sniffer 
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        get_serial(`BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8);
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        // check serial receiver status 
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        // byte received OK 
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        if (get_serial_status & `RECEIVE_RESULT_OK)
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        begin
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                // check if not a control character (above and including space ascii code)
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                if (get_serial_data >= 8'h20)
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                        $display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, get_serial_data, $time);
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                else
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                        $display("received byte 0x%h (\"%c\") at %t ns", get_serial_data, 8'hb0, $time);
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                // sign to transmit process that a new byte was received 
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                @(posedge clock) new_rx_data = 1;
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                @(posedge clock) new_rx_data = 0;
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        end
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        // false start error 
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        if (get_serial_status & `RECEIVE_RESULT_FALSESTART)
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                $display("Error (get_char): false start condition at %t", $realtime);
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        // bad parity error             
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        if (get_serial_status & `RECEIVE_RESULT_BADPARITY)
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                $display("Error (get_char): bad parity condition at %t", $realtime);
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        // bad stop bits sequence       
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        if (get_serial_status & `RECEIVE_RESULT_BADSTOP)
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                $display("Error (get_char): bad stop bits sequence at %t", $realtime);
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end
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//------------------------------------------------------------------
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// device under test 
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// DUT interface 
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wire    [15:0]   int_address;    // address bus to register file 
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wire    [7:0]    int_wr_data;    // write data to register file 
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wire                    int_write;              // write control to register file 
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wire                    int_read;               // read control to register file 
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wire    [7:0]    int_rd_data;    // data read from register file 
194 12 motilito
wire                    int_req;                // bus access request signal 
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wire                    int_gnt;                // bus access grant signal 
196 2 motilito
wire                    ser_in;                 // DUT serial input 
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wire                    ser_out;                // DUT serial output 
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// DUT instance 
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uart2bus_top uart2bus1
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(
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        .clock(clock),
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        .reset(reset),
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        .ser_in(ser_in),
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        .ser_out(ser_out),
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        .int_address(int_address),
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        .int_wr_data(int_wr_data),
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        .int_write(int_write),
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        .int_rd_data(int_rd_data),
210 12 motilito
        .int_read(int_read),
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        .int_req(int_req),
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        .int_gnt(int_gnt)
213 2 motilito
);
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// bus grant is always active 
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assign int_gnt = 1'b1;
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// serial interface to test bench 
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assign ser_in = serial_out;
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always @ (posedge clock) serial_in = ser_out;
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// register file model 
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reg_file_model reg_file1
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(
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        .clock(clock),
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        .reset(reset),
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        .int_address(int_address[7:0]),
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        .int_wr_data(int_wr_data),
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        .int_write(int_write),
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        .int_rd_data(int_rd_data),
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        .int_read(int_read)
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);
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endmodule
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//---------------------------------------------------------------------------------------
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//                                              Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------

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