OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] [timescale.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 motilito
//---------------------------------------------------------------------------------------
2
//
3
//              Timescale definition.
4
// 
5
//---------------------------------------------------------------------------------------
6
 
7
`timescale 1ns / 1ns

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.