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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_parser.v] - Blame information for rev 12

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1 2 motilito
//---------------------------------------------------------------------------------------
2
// uart parser module  
3
//
4
//---------------------------------------------------------------------------------------
5
 
6
module uart_parser
7
(
8
        // global signals 
9
        clock, reset,
10
        // transmit and receive internal interface signals from uart interface 
11
        rx_data, new_rx_data,
12
        tx_data, new_tx_data, tx_busy,
13
        // internal bus to register file 
14
        int_address, int_wr_data, int_write,
15 12 motilito
        int_rd_data, int_read,
16
        int_req, int_gnt
17 2 motilito
);
18
//---------------------------------------------------------------------------------------
19
// parameters 
20
parameter               AW = 8;                 // address bus width parameter 
21
 
22
// modules inputs and outputs 
23
input                   clock;                  // global clock input 
24
input                   reset;                  // global reset input 
25
output  [7:0]    tx_data;                // data byte to transmit 
26
output                  new_tx_data;    // asserted to indicate that there is a new data byte for
27
                                                                // transmission 
28
input                   tx_busy;                // signs that transmitter is busy 
29
input   [7:0]    rx_data;                // data byte received 
30
input                   new_rx_data;    // signs that a new byte was received 
31
output  [AW-1:0] int_address;    // address bus to register file 
32
output  [7:0]    int_wr_data;    // write data to register file 
33
output                  int_write;              // write control to register file 
34
output                  int_read;               // read control to register file 
35
input   [7:0]    int_rd_data;    // data read from register file 
36 12 motilito
output                  int_req;                // bus access request signal 
37
input                   int_gnt;                // bus access grant signal 
38 2 motilito
 
39
// registered outputs
40
reg     [7:0] tx_data;
41
reg new_tx_data;
42
reg     [AW-1:0] int_address;
43
reg     [7:0] int_wr_data;
44 12 motilito
reg write_req, read_req, int_write, int_read;
45 2 motilito
 
46
// internal constants 
47
// define characters used by the parser 
48
`define CHAR_CR                 8'h0d
49
`define CHAR_LF                 8'h0a
50
`define CHAR_SPACE              8'h20
51
`define CHAR_TAB                8'h09
52
`define CHAR_COMMA              8'h2C
53
`define CHAR_R_UP               8'h52
54
`define CHAR_r_LO               8'h72
55
`define CHAR_W_UP               8'h57
56
`define CHAR_w_LO               8'h77
57
`define CHAR_0                  8'h30
58
`define CHAR_1                  8'h31
59
`define CHAR_2                  8'h32
60
`define CHAR_3                  8'h33
61
`define CHAR_4                  8'h34
62
`define CHAR_5                  8'h35
63
`define CHAR_6                  8'h36
64
`define CHAR_7                  8'h37
65
`define CHAR_8                  8'h38
66
`define CHAR_9                  8'h39
67
`define CHAR_A_UP               8'h41
68
`define CHAR_B_UP               8'h42
69
`define CHAR_C_UP               8'h43
70
`define CHAR_D_UP               8'h44
71
`define CHAR_E_UP               8'h45
72
`define CHAR_F_UP               8'h46
73
`define CHAR_a_LO               8'h61
74
`define CHAR_b_LO               8'h62
75
`define CHAR_c_LO               8'h63
76
`define CHAR_d_LO               8'h64
77
`define CHAR_e_LO               8'h65
78
`define CHAR_f_LO               8'h66
79
 
80
// main (receive) state machine states 
81
`define MAIN_IDLE               4'b0000
82
`define MAIN_WHITE1             4'b0001
83
`define MAIN_DATA               4'b0010
84
`define MAIN_WHITE2             4'b0011
85
`define MAIN_ADDR               4'b0100
86
`define MAIN_EOL                4'b0101
87
// binary mode extension states 
88
`define MAIN_BIN_CMD    4'b1000
89
`define MAIN_BIN_ADRH   4'b1001
90
`define MAIN_BIN_ADRL   4'b1010
91
`define MAIN_BIN_LEN    4'b1011
92
`define MAIN_BIN_DATA   4'b1100
93
 
94
// transmit state machine 
95
`define TX_IDLE                 3'b000
96
`define TX_HI_NIB               3'b001
97
`define TX_LO_NIB               3'b100
98
`define TX_CHAR_CR              3'b101
99
`define TX_CHAR_LF              3'b110
100
 
101
// binary extension mode commands - the command is indicated by bits 5:4 of the command byte 
102
`define BIN_CMD_NOP             2'b00
103
`define BIN_CMD_READ    2'b01
104
`define BIN_CMD_WRITE   2'b10
105
 
106
// internal wires and registers 
107
reg [3:0] main_sm;                       // main state machine 
108
reg read_op;                            // read operation flag 
109
reg write_op;                           // write operation flag 
110
reg data_in_hex_range;          // indicates that the received data is in the range of hex number 
111
reg [7:0] data_param;            // operation data parameter 
112
reg [15:0] addr_param;           // operation address parameter 
113
reg [3:0] data_nibble;           // data nibble from received character 
114
reg read_done;                          // internally generated read done flag 
115
reg read_done_s;                        // sampled read done 
116
reg [7:0] read_data_s;           // sampled read data 
117
reg [3:0] tx_nibble;             // nibble value for transmission 
118
reg [7:0] tx_char;                       // transmit byte from nibble to character conversion 
119
reg [2:0] tx_sm;                 // transmit state machine 
120
reg s_tx_busy;                          // sampled tx_busy for falling edge detection 
121
reg bin_read_op;                        // binary mode read operation flag 
122
reg bin_write_op;                       // binary mode write operation flag 
123
reg addr_auto_inc;                      // address auto increment mode 
124
reg send_stat_flag;                     // send status flag 
125
reg [7:0] bin_byte_count;        // binary mode byte counter 
126
wire bin_last_byte;                     // last byte flag indicates that the current byte in the command is the last 
127
wire tx_end_p;                          // transmission end pulse 
128
 
129
//---------------------------------------------------------------------------------------
130
// module implementation 
131
// main state machine 
132
always @ (posedge clock or posedge reset)
133
begin
134
        if (reset)
135
                main_sm <= `MAIN_IDLE;
136
        else if (new_rx_data)
137
        begin
138
                case (main_sm)
139
                        // wait for a read ('r') or write ('w') command 
140
                        // binary extension - an all zeros byte enabled binary commands 
141
                        `MAIN_IDLE:
142
                                // check received character 
143
                                if (rx_data == 8'h0)
144
                                        // an all zeros received byte enters binary mode 
145
                                        main_sm <= `MAIN_BIN_CMD;
146
                                else if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
147
                                        // on read wait to receive only address field 
148
                                        main_sm <= `MAIN_WHITE2;
149
                                else if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
150
                                        // on write wait to receive data and address 
151
                                        main_sm <= `MAIN_WHITE1;
152
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
153
                                        // on new line sta in idle 
154
                                        main_sm <= `MAIN_IDLE;
155
                                else
156
                                        // any other character wait to end of line (EOL)
157
                                        main_sm <= `MAIN_EOL;
158
 
159
                        // wait for white spaces till first data nibble 
160
                        `MAIN_WHITE1:
161
                                // wait in this case until any white space character is received. in any 
162
                                // valid character for data value switch to data state. a new line or carriage 
163
                                // return should reset the state machine to idle.
164
                                // any other character transitions the state machine to wait for EOL.
165
                                if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
166
                                        main_sm <= `MAIN_WHITE1;
167
                                else if (data_in_hex_range)
168
                                        main_sm <= `MAIN_DATA;
169
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
170
                                        main_sm <= `MAIN_IDLE;
171
                                else
172
                                        main_sm <= `MAIN_EOL;
173
 
174
                        // receive data field 
175
                        `MAIN_DATA:
176
                                // wait while data in hex range. white space transition to wait white 2 state.
177
                                // CR and LF resets the state machine. any other value cause state machine to 
178
                                // wait til end of line.
179
                                if (data_in_hex_range)
180
                                        main_sm <= `MAIN_DATA;
181
                                else if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
182
                                        main_sm <= `MAIN_WHITE2;
183
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
184
                                        main_sm <= `MAIN_IDLE;
185
                                else
186
                                        main_sm <= `MAIN_EOL;
187
 
188
                        // wait for white spaces till first address nibble 
189
                        `MAIN_WHITE2:
190
                                // similar to MAIN_WHITE1 
191
                                if ((rx_data == `CHAR_SPACE) | (rx_data == `CHAR_TAB))
192
                                        main_sm <= `MAIN_WHITE2;
193
                                else if (data_in_hex_range)
194
                                        main_sm <= `MAIN_ADDR;
195
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
196
                                        main_sm <= `MAIN_IDLE;
197
                                else
198
                                        main_sm <= `MAIN_EOL;
199
 
200
                        // receive address field 
201
                        `MAIN_ADDR:
202
                                // similar to MAIN_DATA 
203
                                if (data_in_hex_range)
204
                                        main_sm <= `MAIN_ADDR;
205
                                else if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
206
                                        main_sm <= `MAIN_IDLE;
207
                                else
208
                                        main_sm <= `MAIN_EOL;
209
 
210
                        // wait to EOL                          
211
                        `MAIN_EOL:
212
                                // wait for CR or LF to move back to idle 
213
                                if ((rx_data == `CHAR_CR) | (rx_data == `CHAR_LF))
214
                                        main_sm <= `MAIN_IDLE;
215
 
216
                        // binary extension 
217
                        // wait for command - one byte 
218
                        `MAIN_BIN_CMD:
219
                                // check if command is a NOP command 
220
                                if (rx_data[5:4] == `BIN_CMD_NOP)
221
                                        // if NOP command then switch back to idle state 
222
                                        main_sm <= `MAIN_IDLE;
223
                                else
224
                                        // not a NOP command, continue receiving parameters 
225
                                        main_sm <= `MAIN_BIN_ADRH;
226
 
227
                        // wait for address parameter - two bytes 
228
                        // high address byte 
229
                        `MAIN_BIN_ADRH:
230
                                // switch to next state 
231
                                main_sm <= `MAIN_BIN_ADRL;
232
 
233
                        // low address byte 
234
                        `MAIN_BIN_ADRL:
235
                                // switch to next state 
236
                                main_sm <= `MAIN_BIN_LEN;
237
 
238
                        // wait for length parameter - one byte 
239
                        `MAIN_BIN_LEN:
240
                                // check if write command else command reception ended 
241
                                if (bin_write_op)
242
                                        // wait for write data 
243
                                        main_sm <= `MAIN_BIN_DATA;
244
                                else
245
                                        // command reception has ended 
246
                                        main_sm <= `MAIN_IDLE;
247
 
248
                        // on write commands wait for data till end of buffer as specified by length parameter 
249
                        `MAIN_BIN_DATA:
250
                                // if this is the last data byte then return to idle 
251
                                if (bin_last_byte)
252
                                        main_sm <= `MAIN_IDLE;
253
 
254
                        // go to idle 
255
                        default:
256
                                main_sm <= `MAIN_IDLE;
257
                endcase
258
        end
259
end
260
 
261
// indicates that the received data is in the range of hex number 
262
always @ (rx_data)
263
begin
264
        if (((rx_data >= `CHAR_0   ) && (rx_data <= `CHAR_9   )) ||
265
            ((rx_data >= `CHAR_A_UP) && (rx_data <= `CHAR_F_UP)) ||
266
            ((rx_data >= `CHAR_a_LO) && (rx_data <= `CHAR_f_LO)))
267
                data_in_hex_range <= 1'b1;
268
        else
269
                data_in_hex_range <= 1'b0;
270
end
271
 
272
// read operation flag 
273
always @ (posedge clock or posedge reset)
274
begin
275
        if (reset)
276
                read_op <= 1'b0;
277
        else if ((main_sm == `MAIN_IDLE) && new_rx_data)
278
        begin
279
                // the read operation flag is set when a read command is received in idle state and cleared 
280
                // if any other character is received during that state.
281
                if ((rx_data == `CHAR_r_LO) | (rx_data == `CHAR_R_UP))
282
                        read_op <= 1'b1;
283
                else
284
                        read_op <= 1'b0;
285
        end
286
end
287
 
288
// write operation flag 
289
always @ (posedge clock or posedge reset)
290
begin
291
        if (reset)
292
                write_op <= 1'b0;
293
        else if ((main_sm == `MAIN_IDLE) & new_rx_data)
294
        begin
295
                // the write operation flag is set when a write command is received in idle state and cleared 
296
                // if any other character is received during that state.
297
                if ((rx_data == `CHAR_w_LO) | (rx_data == `CHAR_W_UP))
298
                        write_op <= 1'b1;
299
                else
300
                        write_op <= 1'b0;
301
        end
302
end
303
 
304
// binary mode read operation flag 
305
always @ (posedge clock or posedge reset)
306
begin
307
        if (reset)
308
                bin_read_op <= 1'b0;
309
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_READ))
310
                // read command is started on reception of a read command 
311
                bin_read_op <= 1'b1;
312
        else if (bin_read_op && tx_end_p && bin_last_byte)
313
                // read command ends on transmission of the last byte read 
314
                bin_read_op <= 1'b0;
315
end
316
 
317
// binary mode write operation flag 
318
always @ (posedge clock or posedge reset)
319
begin
320
        if (reset)
321
                bin_write_op <= 1'b0;
322
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_WRITE))
323
                // write command is started on reception of a write command 
324
                bin_write_op <= 1'b1;
325
        else if ((main_sm == `MAIN_BIN_DATA) && new_rx_data && bin_last_byte)
326
                bin_write_op <= 1'b0;
327
end
328
 
329
// send status flag - used only in binary extension mode 
330
always @ (posedge clock or posedge reset)
331
begin
332
        if (reset)
333
                send_stat_flag <= 1'b0;
334
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
335
        begin
336
                // check if a status byte should be sent at the end of the command 
337
                if (rx_data[0] == 1'b1)
338
                        send_stat_flag <= 1'b1;
339
                else
340
                        send_stat_flag <= 1'b0;
341
        end
342
end
343
 
344
// address auto increment - used only in binary extension mode 
345
always @ (posedge clock or posedge reset)
346
begin
347
        if (reset)
348
                addr_auto_inc <= 1'b0;
349
        else if ((main_sm == `MAIN_BIN_CMD) && new_rx_data)
350
        begin
351
                // check if address should be automatically incremented or not. 
352
                // Note that when rx_data[1] is set, address auto increment is disabled. 
353
                if (rx_data[1] == 1'b0)
354
                        addr_auto_inc <= 1'b1;
355
                else
356
                        addr_auto_inc <= 1'b0;
357
        end
358
end
359
 
360
// operation data parameter 
361
always @ (posedge clock or posedge reset)
362
begin
363
        if (reset)
364
                data_param <= 8'h0;
365
        else if ((main_sm == `MAIN_WHITE1) & new_rx_data & data_in_hex_range)
366
                data_param <= {4'h0, data_nibble};
367
        else if ((main_sm == `MAIN_DATA) & new_rx_data & data_in_hex_range)
368
                data_param <= {data_param[3:0], data_nibble};
369
end
370
 
371
// operation address parameter 
372
always @ (posedge clock or posedge reset)
373
begin
374
        if (reset)
375
                addr_param <= 0;
376
        else if ((main_sm == `MAIN_WHITE2) & new_rx_data & data_in_hex_range)
377
                addr_param <= {12'b0, data_nibble};
378
        else if ((main_sm == `MAIN_ADDR) & new_rx_data & data_in_hex_range)
379
                addr_param <= {addr_param[11:0], data_nibble};
380
        // binary extension 
381
        else if (main_sm == `MAIN_BIN_ADRH)
382
                addr_param[15:8] <= rx_data;
383
        else if (main_sm == `MAIN_BIN_ADRL)
384
                addr_param[7:0] <= rx_data;
385
end
386
 
387
// binary mode command byte counter is loaded with the length parameter and counts down to zero.
388
// NOTE: a value of zero for the length parameter indicates a command of 256 bytes.
389
always @ (posedge clock or posedge reset)
390
begin
391
        if (reset)
392
                bin_byte_count <= 8'b0;
393
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
394
                bin_byte_count <= rx_data;
395
        else if ((bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data) ||
396
                         (bin_read_op && tx_end_p))
397
                // byte counter is updated on every new data received in write operations and for every 
398
                // byte transmitted for read operations.
399
                bin_byte_count <= bin_byte_count - 1;
400
end
401
// last byte in command flag 
402
assign bin_last_byte = (bin_byte_count == 8'h01) ? 1'b1 : 1'b0;
403
 
404
// internal write control and data 
405
always @ (posedge clock or posedge reset)
406
begin
407
        if (reset)
408
        begin
409 12 motilito
                write_req <= 1'b0;
410 2 motilito
                int_write <= 1'b0;
411
                int_wr_data <= 0;
412
        end
413
        else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
414
        begin
415 12 motilito
                write_req <= 1'b1;
416 2 motilito
                int_wr_data <= data_param;
417
        end
418
        // binary extension mode 
419
        else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
420
        begin
421 12 motilito
                write_req <= 1'b1;
422 2 motilito
                int_wr_data <= rx_data;
423
        end
424 12 motilito
        else if (int_gnt && write_req)
425
        begin
426
                // set internal bus write and clear the write request flag 
427
                int_write <= 1'b1;
428
                write_req <= 1'b0;
429
        end
430 2 motilito
        else
431
                int_write <= 1'b0;
432
end
433
 
434
// internal read control 
435
always @ (posedge clock or posedge reset)
436
begin
437
        if (reset)
438 12 motilito
        begin
439 2 motilito
                int_read <= 1'b0;
440 12 motilito
                read_req <= 1'b0;
441
        end
442 2 motilito
        else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
443 12 motilito
                read_req <= 1'b1;
444 2 motilito
        // binary extension 
445
        else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
446
                // the first read request is issued on reception of the length byte 
447 12 motilito
                read_req <= 1'b1;
448 2 motilito
        else if (bin_read_op && tx_end_p && !bin_last_byte)
449
                // the next read requests are issued after the previous read value was transmitted and 
450
                // this is not the last byte to be read.
451 12 motilito
                read_req <= 1'b1;
452
        else if (int_gnt && read_req)
453
        begin
454
                // set internal bus read and clear the read request flag 
455 2 motilito
                int_read <= 1'b1;
456 12 motilito
                read_req <= 1'b0;
457
        end
458 2 motilito
        else
459
                int_read <= 1'b0;
460
end
461
 
462 12 motilito
// external request signal is active on read or write request 
463
assign int_req = write_req | read_req;
464
 
465 2 motilito
// internal address 
466
always @ (posedge clock or posedge reset)
467
begin
468
        if (reset)
469
                int_address <= 0;
470
        else if ((main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
471
                int_address <= addr_param[AW-1:0];
472
        // binary extension 
473
        else if ((main_sm == `MAIN_BIN_LEN) && new_rx_data)
474
                // sample address parameter on reception of length byte 
475
                int_address <= addr_param[AW-1:0];
476
        else if (addr_auto_inc &&
477
                         ((bin_read_op && tx_end_p && !bin_last_byte) ||
478
                          (bin_write_op && int_write)))
479
                // address is incremented on every read or write if enabled 
480
                int_address <= int_address + 1;
481
end
482
 
483
// read done flag and sampled data read 
484
always @ (posedge clock or posedge reset)
485
begin
486
        if (reset) begin
487
                read_done <= 1'b0;
488
                read_done_s <= 1'b0;
489
                read_data_s <= 8'h0;
490
        end
491
        else
492
        begin
493
                // read done flag 
494
                if (int_read)
495
                        read_done <= 1'b1;
496
                else
497
                        read_done <= 1'b0;
498
 
499
                // sampled read done 
500
                read_done_s <= read_done;
501
 
502
                // sampled data read 
503
                if (read_done)
504
                        read_data_s <= int_rd_data;
505
        end
506
end
507
 
508
// transmit state machine and control 
509
always @ (posedge clock or posedge reset)
510
begin
511
        if (reset) begin
512
                tx_sm <= `TX_IDLE;
513
                tx_data <= 8'h0;
514
                new_tx_data <= 1'b0;
515
        end
516
        else
517
                case (tx_sm)
518
                        // wait for read done indication 
519
                        `TX_IDLE:
520
                                // on end of every read operation check how the data read should be transmitted 
521
                                // according to read type: ascii or binary.
522
                                if (read_done_s)
523
                                        // on binary mode read transmit byte value 
524
                                        if (bin_read_op)
525
                                        begin
526
                                                // note that there is no need to change state 
527
                                                tx_data <= read_data_s;
528
                                                new_tx_data <= 1'b1;
529
                                        end
530
                                        else
531
                                        begin
532
                                                tx_sm <= `TX_HI_NIB;
533
                                                tx_data <= tx_char;
534
                                                new_tx_data <= 1'b1;
535
                                        end
536
                                // check if status byte should be transmitted 
537
                                else if ((send_stat_flag && bin_read_op && tx_end_p && bin_last_byte) ||        // end of read command 
538
                                        (send_stat_flag && bin_write_op && new_rx_data && bin_last_byte) ||     // end of write command 
539
                                        ((main_sm == `MAIN_BIN_CMD) && new_rx_data && (rx_data[5:4] == `BIN_CMD_NOP)))  // NOP 
540
                                begin
541
                                        // send status byte - currently a constant 
542
                                        tx_data <= 8'h5a;
543
                                        new_tx_data <= 1'b1;
544
                                end
545
                                else
546
                                        new_tx_data <= 1'b0;
547
 
548
                        // wait for transmit to end 
549
                        `TX_HI_NIB:
550
                                if (tx_end_p)
551
                                begin
552
                                        tx_sm <= `TX_LO_NIB;
553
                                        tx_data <= tx_char;
554
                                        new_tx_data <= 1'b1;
555
                                end
556
                                else
557
                                        new_tx_data <= 1'b0;
558
 
559
                        // wait for transmit to end 
560
                        `TX_LO_NIB:
561
                                if (tx_end_p)
562
                                begin
563
                                        tx_sm <= `TX_CHAR_CR;
564
                                        tx_data <= `CHAR_CR;
565
                                        new_tx_data <= 1'b1;
566
                                end
567
                                else
568
                                        new_tx_data <= 1'b0;
569
 
570
                        // wait for transmit to end 
571
                        `TX_CHAR_CR:
572
                                if (tx_end_p)
573
                                begin
574
                                        tx_sm <= `TX_CHAR_LF;
575
                                        tx_data <= `CHAR_LF;
576
                                        new_tx_data <= 1'b1;
577
                                end
578
                                else
579
                                        new_tx_data <= 1'b0;
580
 
581
                        // wait for transmit to end 
582
                        `TX_CHAR_LF:
583
                                begin
584
                                        if (tx_end_p)
585
                                                tx_sm <= `TX_IDLE;
586
                                        // clear tx new data flag 
587
                                        new_tx_data <= 1'b0;
588
                                end
589
 
590
                        // return to idle 
591
                        default:
592
                                tx_sm <= `TX_IDLE;
593
                endcase
594
end
595
 
596
// select the nibble to the nibble to character conversion 
597
always @ (tx_sm or read_data_s)
598
begin
599
        case (tx_sm)
600
                `TX_IDLE:               tx_nibble = read_data_s[7:4];
601
                `TX_HI_NIB:             tx_nibble = read_data_s[3:0];
602
                default:                tx_nibble = read_data_s[7:4];
603
        endcase
604
end
605
 
606
// sampled tx_busy 
607
always @ (posedge clock or posedge reset)
608
begin
609
        if (reset)
610
                s_tx_busy <= 1'b0;
611
        else
612
                s_tx_busy <= tx_busy;
613
end
614
// tx end pulse 
615
assign tx_end_p = ~tx_busy & s_tx_busy;
616
 
617
// character to nibble conversion 
618
always @ (rx_data)
619
begin
620
        case (rx_data)
621
                `CHAR_0:                                data_nibble = 4'h0;
622
                `CHAR_1:                                data_nibble = 4'h1;
623
                `CHAR_2:                                data_nibble = 4'h2;
624
                `CHAR_3:                                data_nibble = 4'h3;
625
                `CHAR_4:                                data_nibble = 4'h4;
626
                `CHAR_5:                                data_nibble = 4'h5;
627
                `CHAR_6:                                data_nibble = 4'h6;
628
                `CHAR_7:                                data_nibble = 4'h7;
629
                `CHAR_8:                                data_nibble = 4'h8;
630
                `CHAR_9:                                data_nibble = 4'h9;
631
                `CHAR_A_UP, `CHAR_a_LO: data_nibble = 4'ha;
632
                `CHAR_B_UP, `CHAR_b_LO: data_nibble = 4'hb;
633
                `CHAR_C_UP, `CHAR_c_LO: data_nibble = 4'hc;
634
                `CHAR_D_UP, `CHAR_d_LO: data_nibble = 4'hd;
635
                `CHAR_E_UP, `CHAR_e_LO: data_nibble = 4'he;
636
                `CHAR_F_UP, `CHAR_f_LO: data_nibble = 4'hf;
637
                default:                                data_nibble = 4'hf;
638
        endcase
639
end
640
 
641
// nibble to character conversion 
642
always @ (tx_nibble)
643
begin
644
        case (tx_nibble)
645
                4'h0:   tx_char = `CHAR_0;
646
                4'h1:   tx_char = `CHAR_1;
647
                4'h2:   tx_char = `CHAR_2;
648
                4'h3:   tx_char = `CHAR_3;
649
                4'h4:   tx_char = `CHAR_4;
650
                4'h5:   tx_char = `CHAR_5;
651
                4'h6:   tx_char = `CHAR_6;
652
                4'h7:   tx_char = `CHAR_7;
653
                4'h8:   tx_char = `CHAR_8;
654
                4'h9:   tx_char = `CHAR_9;
655
                4'ha:   tx_char = `CHAR_A_UP;
656
                4'hb:   tx_char = `CHAR_B_UP;
657
                4'hc:   tx_char = `CHAR_C_UP;
658
                4'hd:   tx_char = `CHAR_D_UP;
659
                4'he:   tx_char = `CHAR_E_UP;
660
                default: tx_char = `CHAR_F_UP;
661
        endcase
662
end
663
 
664
endmodule
665
//---------------------------------------------------------------------------------------
666
//                                              Th.. Th.. Th.. Thats all folks !!!
667
//---------------------------------------------------------------------------------------

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