OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [syn/] [altera/] [uart2bus_top.qsf] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 motilito
# -------------------------------------------------------------------------- #
2
#
3
# Copyright (C) 1991-2009 Altera Corporation
4
# Your use of Altera Corporation's design tools, logic functions
5
# and other software and tools, and its AMPP partner logic
6
# functions, and any output files from any of the foregoing
7
# (including device programming or simulation files), and any
8
# associated documentation or information are expressly subject
9
# to the terms and conditions of the Altera Program License
10
# Subscription Agreement, Altera MegaCore Function License
11
# Agreement, or other applicable license agreement, including,
12
# without limitation, that your use is for the sole purpose of
13
# programming logic devices manufactured by Altera and sold by
14
# Altera or its authorized distributors.  Please refer to the
15
# applicable agreement for further details.
16
#
17
# -------------------------------------------------------------------------- #
18
#
19
# Quartus II
20
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
21
# Date created = 13:37:13  February 13, 2010
22
#
23
# -------------------------------------------------------------------------- #
24
#
25
# Notes:
26
#
27
# 1) The default values for assignments are stored in the file:
28
#               uart2bus_top_assignment_defaults.qdf
29
#    If this file doesn't exist, see file:
30
#               assignment_defaults.qdf
31
#
32
# 2) Altera recommends that you do not modify this file. This
33
#    file is updated automatically by the Quartus II software
34
#    and any changes you make may be lost or overwritten.
35
#
36
# -------------------------------------------------------------------------- #
37
 
38
 
39
set_global_assignment -name FAMILY "Stratix III"
40
set_global_assignment -name DEVICE AUTO
41
set_global_assignment -name TOP_LEVEL_ENTITY uart2bus_top
42
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
43
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:37:13  FEBRUARY 13, 2010"
44
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
45
set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
46
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
47
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
48
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
49
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog/
50
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
51
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
52
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
53
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
54
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
55
set_global_assignment -name VERILOG_FILE ../../rtl/baud_gen.v
56
set_global_assignment -name VERILOG_FILE ../../rtl/uart2bus_top.v
57
set_global_assignment -name VERILOG_FILE ../../rtl/uart_parser.v
58
set_global_assignment -name VERILOG_FILE ../../rtl/uart_rx.v
59
set_global_assignment -name VERILOG_FILE ../../rtl/uart_top.v
60
set_global_assignment -name VERILOG_FILE ../../rtl/uart_tx.v
61
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
62
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.