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[/] [uart2bus/] [trunk/] [vhdl/] [bench/] [uart2BusTop_txt_tb.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 11 smuller
-----------------------------------------------------------------------------------------
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-- uart test bench   
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--
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-----------------------------------------------------------------------------------------
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use std.textio.all;
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.uart2BusTop_pkg.all;
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use work.helpers_pkg.all;
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-----------------------------------------------------------------------------------------
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-- test bench implementation 
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entity uart2BusTop_txt_tb is
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end uart2BusTop_txt_tb;
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architecture behavior of uart2BusTop_txt_tb is
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  -- Inputs
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  signal clr            : std_logic := '0';
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  signal clk            : std_logic := '0';
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  signal serIn          : std_logic := '0';
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  signal intRdData      : std_logic_vector(7 downto 0) := (others => '0');
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        -- Outputs
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  signal serOut         : std_logic;
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  signal intAddress     : std_logic_vector(7 downto 0);
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  signal intWrData      : std_logic_vector(7 downto 0);
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  signal intWrite       : std_logic;
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  signal intRead        : std_logic;
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  signal recvData       : std_logic_vector(7 downto 0);
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  signal newRxData      : std_logic;
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  signal intAccessReq   : std_logic;
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  signal intAccessGnt   : std_logic;
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  signal counter        : integer;
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  constant BAUD_115200  : real := 115200.0;
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  constant BAUD_38400   : real := 38400.0;
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  constant BAUD_28800   : real := 28800.0;
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  constant BAUD_19200   : real := 19200.0;
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  constant BAUD_9600    : real := 9600.0;
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  constant BAUD_4800    : real := 4800.0;
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  constant BAUD_2400    : real := 2400.0;
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  constant BAUD_1200    : real := 1200.0;
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  constant NSTOPS_1     : real := 1.0;
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  constant NSTOPS_1_5   : real := 1.5;
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  constant NSTOPS_2     : real := 2.0;
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  constant PARITY_NONE  : integer := 0;
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  constant PARITY_EVEN  : integer := 1;
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  constant PARITY_ODD   : integer := 2;
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  constant PARITY_MARK  : integer := 3;
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  constant PARITY_SPACE : integer := 4;
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  constant NBITS_7      : integer := 6;
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  constant NBITS_8      : integer := 7;
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  begin
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    -- Instantiate the Unit Under Test (UUT)
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    uut : uart2BusTop
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      port map
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      (
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        clr => clr,
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        clk => clk,
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        serIn => serIn,
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        serOut => serOut,
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        intAccessReq => intAccessReq,
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        intAccessGnt => intAccessGnt,
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        intRdData => intRdData,
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        intAddress => intAddress,
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        intWrData => intWrData,
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        intWrite => intWrite,
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        intRead => intRead
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      );
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    rfm : regFileModel
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    port map
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    (
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      clr => clr,
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      clk => clk,
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      intRdData => intRdData,
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      intAddress => intAddress,
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      intWrData => intWrData,
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      intWrite => intWrite,
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      intRead => intRead);
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    -- just to create a delay similar to simulate a bus arbitrer
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        intAccessGnt <= '0';
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        counter <= 0;
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      elsif (rising_edge(clk)) then
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        if (counter = 0) then
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          if ((intAccessReq = '1') and (intAccessGnt = '0')) then
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            counter <= 500;
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          end if;
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          intAccessGnt <= '0';
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        elsif (counter = 1) then
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          counter <= counter - 1;
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          intAccessGnt <= '1';
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        else
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          counter <= counter - 1;
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        end if;
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      end if;
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    end process;
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    -- clock generator - 25MHz clock 
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    process
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    begin
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      clk <= '0';
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      wait for 20 ns;
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      clk <= '1';
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      wait for 20 ns;
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    end process;
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    -- reset process definitions
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    process
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    begin
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      clr <= '1';
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      wait for 40 ns;
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      clr <= '0';
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      wait;
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    end process;
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    --------------------------------------------------------------------
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    -- test bench receiver 
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    process
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    begin
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      newRxData <= '0';
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      recvData <= (others => '0');
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      wait until (clr = '0');
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      loop
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        recvSerial(serOut, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, recvData);
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        newRxData <= '1';
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        wait for 25 ns;
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        newRxData <= '0';
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      end loop;
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    end process;
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    --------------------------------------------------------------------
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    -- uart transmit - test bench control 
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    process
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      type     dataFile is file of character;
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      file     testTextFile : dataFile open READ_MODE is "../test.txt";
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      variable charBuf      : character;
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      variable data         : integer;
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      variable tempLine     : line;
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    begin
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          -- default value of serial output 
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      serIn <= '1';
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      -- text mode simulation 
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      write(tempLine, string'("Starting text mode simulation"));
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      writeline(output, tempLine);
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      wait until (clr = '0');
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      wait until (rising_edge(clk));
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      for index in 0 to 99 loop
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        wait until (rising_edge(clk));
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      end loop;
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      while not endfile(testTextFile) loop
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        -- transmit the byte in the command file one by one 
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        read(testTextFile, charBuf);
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        data := character'pos(charBuf);
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        sendSerial(data, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, serIn);
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        wait for 800 us;
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      end loop;
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      wait;
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    end process;
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  end;

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