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[/] [uart2bus/] [trunk/] [vhdl/] [rtl/] [uartRx.vhd] - Blame information for rev 13

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-----------------------------------------------------------------------------------------
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-- uart receive module  
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--
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-----------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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entity uartRx is
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  port ( clr       : in  std_logic;                    -- global reset input
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         clk       : in  std_logic;                    -- global clock input
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         ce16      : in  std_logic;                    -- baud rate multiplyed by 16 - generated by baud module
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         serIn     : in  std_logic;                    -- serial data input
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         rxData    : out std_logic_vector(7 downto 0); -- data byte received
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         newRxData : out std_logic);                   -- signs that a new byte was received
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end uartRx;
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architecture Behavioral of uartRx is
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  signal ce1      : std_logic;                    -- clock enable at bit rate
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  signal ce1Mid   : std_logic;                    -- clock enable at the middle of each bit - used to sample data
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  signal inSync   : std_logic_vector(1 downto 0);
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  signal count16  : std_logic_vector(3 downto 0);
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  signal rxBusy   : std_logic;
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  signal bitCount : std_logic_vector(3 downto 0);
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  signal dataBuf  : std_logic_vector(7 downto 0);
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  begin
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    -- input async input is sampled twice
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        inSync <= (others => '1');
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      elsif (rising_edge(clk)) then
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        inSync <= inSync(0) & serIn;
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      end if;
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    end process;
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    -- a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
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    -- this counter is used to detect the start bit while the receiver is not receiving and
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    -- signs the sampling cycle during reception.
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        count16 <= (others => '0');
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      elsif (rising_edge(clk)) then
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        if (ce16 = '1') then
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          if ((rxBusy = '1') or (inSync(1) = '0')) then
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            count16 <= std_logic_vector(unsigned(count16) + 1);
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          else
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            count16 <= (others => '0');
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          end if;
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        end if;
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      end if;
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    end process;
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    -- receiving busy flag
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        rxBusy <= '0';
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      elsif (rising_edge(clk)) then
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        if ((rxBusy = '0') and (ce1Mid = '1')) then
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          rxBusy <= '1';
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        elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1Mid = '1')) then
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          rxBusy <= '0';
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        end if;
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      end if;
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    end process;
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    -- bit counter
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        bitCount <= (others => '0');
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      elsif (rising_edge(clk)) then
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        if (rxBusy = '0') then
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          bitCount <= (others => '0');
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        elsif ((rxBusy = '1') and (ce1Mid = '1')) then
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          bitCount <= std_logic_vector(unsigned(bitCount) + 1);
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        end if;
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      end if;
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    end process;
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    -- data buffer shift register
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        dataBuf <= (others => '0');
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      elsif (rising_edge(clk)) then
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        if ((rxBusy = '1') and (ce1Mid = '1')) then
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          dataBuf <= inSync(1) & dataBuf(7 downto 1);
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        end if;
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      end if;
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    end process;
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    -- data output and flag
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    process (clr, clk)
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    begin
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      if (clr = '1') then
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        rxData <= (others => '0');
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        newRxData <= '0';
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      elsif (rising_edge(clk)) then
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        if ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
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          rxData <= dataBuf;
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          newRxData <= '1';
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        else
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          newRxData <= '0';
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        end if;
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      end if;
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    end process;
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    -- ce_1 pulse indicating expected end of current bit
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    ce1 <= '1' when ((count16 = "1111") and (ce16 = '1')) else '0';
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    -- ce_1_mid pulse indication the sampling clock cycle of the current data bit
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    ce1Mid <= '1' when ((count16 = "0111") and (ce16 = '1')) else '0';
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  end Behavioral;

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