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pjf |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:54:32 06/04/2011
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-- Design Name:
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
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-- Project Name: ip1
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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use work.arp;
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use work.arpv2;
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ENTITY IP_av2_complete_nomac_tb IS
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END IP_av2_complete_nomac_tb;
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--configuration main of IP_av2_complete_nomac_tb is
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-- for behavior
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-- for uut : IP_complete_nomac
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-- use configuration work.IP_complete_nomac.multi_slot_arp;
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-- end for;
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-- end for;
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--end main;
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ARCHITECTURE behavior OF IP_av2_complete_nomac_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT IP_complete_nomac
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generic (
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
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);
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Port (
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-- IP Layer signals
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ip_tx_start : in std_logic;
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ip_tx : in ipv4_tx_type; -- IP tx cxns
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ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
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ip_rx_start : out std_logic; -- indicates receipt of ip frame.
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ip_rx : out ipv4_rx_type;
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-- system signals
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rx_clk : in STD_LOGIC;
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tx_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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control : in ip_control_type;
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-- status signals
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arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
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ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
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-- MAC Transmitter
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mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
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mac_tx_tvalid : out std_logic; -- tdata is valid
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mac_tx_tready : in std_logic; -- mac is ready to accept data
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mac_tx_tfirst : out std_logic; -- indicates first byte of frame
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mac_tx_tlast : out std_logic; -- indicates last byte of frame
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-- MAC Receiver
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mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
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mac_rx_tvalid : in std_logic; -- indicates tdata is valid
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mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
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mac_rx_tlast : in std_logic -- indicates last byte of the trame
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);
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END COMPONENT;
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--Inputs
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signal ip_tx_start : std_logic := '0';
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signal ip_tx : ipv4_tx_type;
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
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signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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signal mac_tx_tready : std_logic := '0';
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signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
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signal mac_rx_tvalid : std_logic := '0';
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signal mac_rx_tlast : std_logic := '0';
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signal control : ip_control_type;
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--Outputs
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signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
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signal ip_rx_start : std_logic;
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signal ip_rx : ipv4_rx_type;
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signal arp_pkt_count : std_logic_vector(7 downto 0);
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signal mac_tx_tdata : std_logic_vector(7 downto 0);
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signal mac_tx_tvalid : std_logic;
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signal mac_tx_tfirst : std_logic;
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signal mac_tx_tlast : std_logic;
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signal mac_rx_tready : std_logic;
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: IP_complete_nomac PORT MAP (
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ip_tx_start => ip_tx_start,
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ip_tx => ip_tx,
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ip_tx_result => ip_tx_result,
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ip_tx_data_out_ready => ip_tx_data_out_ready,
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ip_rx_start => ip_rx_start,
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ip_rx => ip_rx,
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rx_clk => clk,
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tx_clk => clk,
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reset => reset,
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our_ip_address => our_ip_address,
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our_mac_address => our_mac_address,
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control => control,
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arp_pkt_count => arp_pkt_count,
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mac_tx_tdata => mac_tx_tdata,
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mac_tx_tvalid => mac_tx_tvalid,
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mac_tx_tready => mac_tx_tready,
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mac_tx_tfirst => mac_tx_tfirst,
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mac_tx_tlast => mac_tx_tlast,
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mac_rx_tdata => mac_rx_tdata,
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mac_rx_tvalid => mac_rx_tvalid,
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mac_rx_tready => mac_rx_tready,
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mac_rx_tlast => mac_rx_tlast
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 80 ns;
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our_ip_address <= x"c0a80509"; -- 192.168.5.9
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our_mac_address <= x"002320212223";
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control.arp_controls.clear_cache <= '0';
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ip_tx_start <= '0';
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mac_tx_tready <= '0';
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reset <= '1';
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wait for clk_period*10;
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reset <= '0';
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wait for clk_period*5;
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-- check reset conditions
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assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
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assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
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assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
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assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
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assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
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assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
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assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
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assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
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assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
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assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
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assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
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assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
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assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
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assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
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-- insert stimulus here
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------------
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-- TEST 1 -- basic functional rx test with received ip pkt
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------------
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report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
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mac_tx_tready <= '1';
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mac_rx_tvalid <= '1';
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-- dst MAC (bc)
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"20"; wait for clk_period;
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mac_rx_tdata <= x"21"; wait for clk_period;
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mac_rx_tdata <= x"22"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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-- src MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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mac_rx_tdata <= x"29"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"7c"; wait for clk_period;
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-- type
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mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- ver & HL / service type
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mac_rx_tdata <= x"45"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- total len
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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-- ID
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- flags & frag
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- TTL
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- Protocol
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mac_rx_tdata <= x"11"; wait for clk_period;
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-- Header CKS
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- SRC IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- DST IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"09"; wait for clk_period;
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-- user data
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mac_rx_tdata <= x"24"; wait for clk_period;
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-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
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assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
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assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
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assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
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assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
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assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
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assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
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assert ip_rx_start = '1' report "T1: ip_rx_start not set";
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assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
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mac_rx_tdata <= x"25"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
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assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
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mac_rx_tdata <= x"00";
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mac_rx_tlast <= '0';
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mac_rx_tvalid <= '0';
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wait for clk_period;
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assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
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assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
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assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
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assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
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assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
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------------
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-- TEST 2 -- respond with IP TX
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------------
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report "T2: respond with IP TX";
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ip_tx.hdr.protocol <= x"35";
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ip_tx.hdr.data_length <= x"0006";
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ip_tx.hdr.dst_ip_addr <= x"c0123478";
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_last <= '0';
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wait for clk_period;
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|
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ip_tx_start <= '1'; wait for clk_period;
|
| 295 |
|
|
|
| 296 |
|
|
ip_tx_start <= '0'; wait for clk_period;
|
| 297 |
|
|
|
| 298 |
|
|
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
|
| 299 |
|
|
|
| 300 |
|
|
wait for clk_period*2;
|
| 301 |
|
|
|
| 302 |
|
|
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
|
| 303 |
|
|
|
| 304 |
|
|
-- need to wait for ARP tx to complete
|
| 305 |
|
|
|
| 306 |
|
|
wait for clk_period*50;
|
| 307 |
|
|
|
| 308 |
|
|
assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
|
| 309 |
|
|
assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
|
| 310 |
|
|
|
| 311 |
|
|
-- now create the ARP response (rx)
|
| 312 |
|
|
|
| 313 |
|
|
-- Send the reply
|
| 314 |
|
|
-- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
|
| 315 |
|
|
mac_rx_tvalid <= '1';
|
| 316 |
|
|
-- dst MAC (bc)
|
| 317 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 318 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 319 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 320 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 321 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 322 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
| 323 |
|
|
-- src MAC
|
| 324 |
|
|
mac_rx_tdata <= x"02"; wait for clk_period;
|
| 325 |
|
|
mac_rx_tdata <= x"12"; wait for clk_period;
|
| 326 |
|
|
mac_rx_tdata <= x"03"; wait for clk_period;
|
| 327 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 328 |
|
|
mac_rx_tdata <= x"04"; wait for clk_period;
|
| 329 |
|
|
mac_rx_tdata <= x"54"; wait for clk_period;
|
| 330 |
|
|
-- type
|
| 331 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period;
|
| 332 |
|
|
mac_rx_tdata <= x"06"; wait for clk_period;
|
| 333 |
|
|
-- HW type
|
| 334 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 335 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
| 336 |
|
|
-- Protocol type
|
| 337 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period;
|
| 338 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 339 |
|
|
-- HW size
|
| 340 |
|
|
mac_rx_tdata <= x"06"; wait for clk_period;
|
| 341 |
|
|
-- protocol size
|
| 342 |
|
|
mac_rx_tdata <= x"04"; wait for clk_period;
|
| 343 |
|
|
-- Opcode
|
| 344 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 345 |
|
|
mac_rx_tdata <= x"02"; wait for clk_period;
|
| 346 |
|
|
-- Sender MAC
|
| 347 |
|
|
mac_rx_tdata <= x"02"; wait for clk_period;
|
| 348 |
|
|
mac_rx_tdata <= x"12"; wait for clk_period;
|
| 349 |
|
|
mac_rx_tdata <= x"03"; wait for clk_period;
|
| 350 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 351 |
|
|
mac_rx_tdata <= x"04"; wait for clk_period;
|
| 352 |
|
|
mac_rx_tdata <= x"54"; wait for clk_period;
|
| 353 |
|
|
-- Sender IP
|
| 354 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 355 |
|
|
mac_rx_tdata <= x"12"; wait for clk_period;
|
| 356 |
|
|
mac_rx_tdata <= x"34"; wait for clk_period;
|
| 357 |
|
|
mac_rx_tdata <= x"78"; wait for clk_period;
|
| 358 |
|
|
-- Target MAC
|
| 359 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 360 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 361 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
| 362 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
| 363 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
| 364 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 365 |
|
|
-- Target IP
|
| 366 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 367 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
| 368 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
| 369 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
| 370 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 371 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 372 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 373 |
|
|
mac_rx_tlast <= '1';
|
| 374 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 375 |
|
|
mac_rx_tlast <= '0';
|
| 376 |
|
|
mac_rx_tvalid <= '0';
|
| 377 |
|
|
|
| 378 |
|
|
wait until ip_tx_data_out_ready = '1';
|
| 379 |
|
|
|
| 380 |
|
|
-- start to tx IP data
|
| 381 |
|
|
ip_tx.data.data_out_valid <= '1';
|
| 382 |
|
|
ip_tx.data.data_out <= x"56"; wait for clk_period;
|
| 383 |
|
|
ip_tx.data.data_out <= x"57"; wait for clk_period;
|
| 384 |
|
|
ip_tx.data.data_out <= x"58"; wait for clk_period;
|
| 385 |
|
|
ip_tx.data.data_out <= x"59"; wait for clk_period;
|
| 386 |
|
|
ip_tx.data.data_out <= x"5a"; wait for clk_period;
|
| 387 |
|
|
|
| 388 |
|
|
ip_tx.data.data_out <= x"5b";
|
| 389 |
|
|
ip_tx.data.data_out_last <= '1';
|
| 390 |
|
|
wait for clk_period;
|
| 391 |
|
|
|
| 392 |
|
|
assert mac_tx_tlast = '1' report "T2: mac_tx_tlast not set on last byte";
|
| 393 |
|
|
|
| 394 |
|
|
wait for clk_period;
|
| 395 |
|
|
|
| 396 |
|
|
ip_tx.data.data_out_valid <= '0';
|
| 397 |
|
|
ip_tx.data.data_out_last <= '0';
|
| 398 |
|
|
wait for clk_period*2;
|
| 399 |
|
|
|
| 400 |
|
|
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be SENT";
|
| 401 |
|
|
wait for clk_period*10;
|
| 402 |
|
|
|
| 403 |
|
|
------------
|
| 404 |
|
|
-- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached
|
| 405 |
|
|
------------
|
| 406 |
|
|
|
| 407 |
|
|
report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx";
|
| 408 |
|
|
ip_tx.hdr.protocol <= x"35";
|
| 409 |
|
|
ip_tx.hdr.data_length <= x"0006";
|
| 410 |
|
|
ip_tx.hdr.dst_ip_addr <= x"c0123478";
|
| 411 |
|
|
ip_tx.data.data_out_valid <= '0';
|
| 412 |
|
|
ip_tx.data.data_out_last <= '0';
|
| 413 |
|
|
wait for clk_period;
|
| 414 |
|
|
ip_tx_start <= '1'; wait for clk_period;
|
| 415 |
|
|
ip_tx_start <= '0'; wait for clk_period;
|
| 416 |
|
|
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
|
| 417 |
|
|
wait for clk_period*2;
|
| 418 |
|
|
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
|
| 419 |
|
|
wait until ip_tx_data_out_ready = '1';
|
| 420 |
|
|
|
| 421 |
|
|
-- start to tx IP data
|
| 422 |
|
|
ip_tx.data.data_out_valid <= '1';
|
| 423 |
|
|
ip_tx.data.data_out <= x"81"; wait for clk_period;
|
| 424 |
|
|
ip_tx.data.data_out <= x"83"; wait for clk_period;
|
| 425 |
|
|
ip_tx.data.data_out <= x"85"; wait for clk_period;
|
| 426 |
|
|
ip_tx.data.data_out <= x"87"; wait for clk_period;
|
| 427 |
|
|
ip_tx.data.data_out <= x"89"; wait for clk_period;
|
| 428 |
|
|
|
| 429 |
|
|
ip_tx.data.data_out <= x"8b";
|
| 430 |
|
|
ip_tx.data.data_out_last <= '1';
|
| 431 |
|
|
wait for clk_period;
|
| 432 |
|
|
|
| 433 |
|
|
assert mac_tx_tlast = '1' report "T3: mac_tx_tlast not set on last byte";
|
| 434 |
|
|
|
| 435 |
|
|
wait for clk_period;
|
| 436 |
|
|
|
| 437 |
|
|
ip_tx.data.data_out_valid <= '0';
|
| 438 |
|
|
ip_tx.data.data_out_last <= '0';
|
| 439 |
|
|
wait for clk_period*2;
|
| 440 |
|
|
|
| 441 |
|
|
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be SENT";
|
| 442 |
|
|
wait for clk_period*2;
|
| 443 |
|
|
|
| 444 |
|
|
|
| 445 |
|
|
|
| 446 |
|
|
report "-- end of tests --";
|
| 447 |
|
|
|
| 448 |
|
|
wait;
|
| 449 |
|
|
end process;
|
| 450 |
|
|
|
| 451 |
|
|
END;
|
