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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IPv4_TX_tb.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:
4
--
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-- Create Date:   09:35:58 06/03/2011
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-- Design Name:   
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-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
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-- Project Name:  ip1
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-- Target Device:  
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-- Tool versions:  
11
-- Description:   
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-- 
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-- VHDL Test Bench Created by ISE for module: IPv4_TX
14
-- 
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-- Dependencies:
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes: 
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation 
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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35
 
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ENTITY IPv4_TX_tb IS
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END IPv4_TX_tb;
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ARCHITECTURE behavior OF IPv4_TX_tb IS
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    -- Component Declaration for the Unit Under Test (UUT)
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43
    COMPONENT IPv4_TX
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    PORT(
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                        -- IP Layer signals
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                        ip_tx_start                             : in std_logic;
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                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
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                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
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51
                        -- system signals
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                        clk                                             : in  STD_LOGIC;                                                                        -- same clock used to clock mac data and ip data
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
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                        our_mac_address                 : in std_logic_vector (47 downto 0);
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                        -- ARP lookup signals
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                        arp_req_req                             : out arp_req_req_type;
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                        arp_req_rslt                    : in arp_req_rslt_type;
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                        -- MAC layer TX signals
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                        mac_tx_req                              : out std_logic;                                                                        -- indicates that ip wants access to channel (stays up for as long as tx)
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                        mac_tx_granted                  : in std_logic;                                                                 -- indicates that access to channel has been granted            
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                        mac_data_out_ready      : in std_logic;                                                                 -- indicates system ready to consume data
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                        mac_data_out_valid      : out std_logic;                                                                -- indicates data out is valid
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                        mac_data_out_last               : out std_logic;                                                                        -- with data out valid indicates the last byte of a frame
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                        mac_data_out                    : out std_logic_vector (7 downto 0)              -- ethernet frame (from dst mac addr through to last byte of frame)      
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        );
67
    END COMPONENT;
68
 
69
 
70
   --Inputs
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   signal ip_tx_start : std_logic := '0';
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   signal ip_tx : ipv4_tx_type;
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   signal clk : std_logic := '0';
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   signal reset : std_logic := '0';
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   signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
76
   signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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   signal mac_tx_granted : std_logic := '0';
78
   signal mac_data_out_ready : std_logic := '0';
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   signal arp_req_rslt : arp_req_rslt_type;
80
 
81
        --Outputs
82
        signal ip_tx_result : std_logic_vector (1 downto 0);                                             -- tx status (changes during transmission)
83
        signal ip_tx_data_out_ready     :  std_logic;                                                                   -- indicates IP TX is ready to take data
84
   signal mac_tx_req : std_logic;
85
   signal mac_data_out_valid : std_logic;
86
   signal mac_data_out_last : std_logic;
87
   signal mac_data_out : std_logic_vector(7 downto 0);
88
   signal arp_req_req : arp_req_req_type;
89
 
90
   -- Clock period definitions
91
   constant clk_period : time := 8 ns;
92
 
93
BEGIN
94
 
95
        -- Instantiate the Unit Under Test (UUT)
96
   uut: IPv4_TX PORT MAP (
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          ip_tx_start => ip_tx_start,
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          ip_tx => ip_tx,
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          ip_tx_result => ip_tx_result,
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          ip_tx_data_out_ready => ip_tx_data_out_ready,
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          clk => clk,
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          reset => reset,
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          our_ip_address => our_ip_address,
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          our_mac_address => our_mac_address,
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          arp_req_req => arp_req_req,
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          arp_req_rslt => arp_req_rslt,
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          mac_tx_req => mac_tx_req,
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          mac_tx_granted => mac_tx_granted,
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          mac_data_out_ready => mac_data_out_ready,
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          mac_data_out_valid => mac_data_out_valid,
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          mac_data_out_last => mac_data_out_last,
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          mac_data_out => mac_data_out
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        );
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115
   -- Clock process definitions
116
   clk_process :process
117
   begin
118
                clk <= '0';
119
                wait for clk_period/2;
120
                clk <= '1';
121
                wait for clk_period/2;
122
   end process;
123
 
124
 
125
   -- Stimulus process
126
   stim_proc: process
127
   begin
128
      -- hold reset state for 100 ns.
129
      wait for 100 ns;
130
 
131
                our_ip_address <= x"c0a80509";          -- 192.168.5.9
132
                our_mac_address <= x"002320212223";
133
                ip_tx_start <= '0';
134
      mac_tx_granted <= '0';
135
      mac_data_out_ready <= '0';
136
                ip_tx.data.data_out_valid <= '0';
137
                ip_tx.data.data_out_last <= '0';
138
 
139
                reset <= '1';
140
      wait for clk_period*10;
141
                reset <= '0';
142
      wait for clk_period*5;
143
 
144
                -- check reset conditions
145
                assert arp_req_req.lookup_req = '0'                      report "arp_req_req.lookup_req not initialised correctly on reset";
146
                assert ip_tx_result = IPTX_RESULT_NONE  report "ip_tx_result not initialised correctly on reset";
147
                assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
148
                assert mac_tx_req = '0'                                  report "mac_tx_req not initialised correctly on reset";
149
                assert mac_data_out_valid = '0'                  report "mac_data_out_valid not initialised correctly on reset";
150
                assert mac_data_out_last = '0'                   report "mac_data_out_last not initialised correctly on reset";
151
 
152
      -- insert stimulus here 
153
 
154
                ------------
155
                -- TEST 1 -- basic functional tx test with some delays for arp and chn access
156
                ------------
157
 
158
                report "T1: basic functional tx test with some delays for arp and chn access";
159
 
160
                ip_tx.hdr.protocol <= x"35";
161
                ip_tx.hdr.data_length <= x"0008";
162
                ip_tx.hdr.dst_ip_addr <= x"c0123478";
163
                ip_tx_start <= '1';
164
                wait for clk_period;
165
                ip_tx_start <= '0'; wait for clk_period;
166
                arp_req_rslt.got_mac <= '0';
167
 
168
                assert arp_req_req.lookup_req = '1'                                     report "T1: lookup_req not set on tx start";
169
                assert ip_tx_result = IPTX_RESULT_SENDING               report "T1: result should be IPTX_RESULT_SENDING";
170
 
171
                wait for clk_period*10;         -- simulate arp lookup time
172
                arp_req_rslt.mac <= x"050423271016";
173
                arp_req_rslt.got_mac <= '1';
174
 
175
                wait for clk_period*2;
176
 
177
                assert arp_req_req.lookup_req = '0'                      report "T1: lookup_req not clear after setting";
178
                assert mac_tx_req = '1'                                         report "T1: mac_tx_req not set after getting mac";
179
 
180
                wait for clk_period*10;         -- simulate mac chn access time
181
                mac_tx_granted <= '1';
182
                wait for clk_period*2;
183
      mac_data_out_ready <= '1';
184
                assert mac_data_out_valid = '0'                  report "T1: mac_data_out_valid asserted too early";
185
 
186
                wait for clk_period;
187
 
188
                assert ip_tx_data_out_ready = '0'        report "T1: IP data out ready asserted too early";
189
                wait for clk_period;
190
                assert mac_data_out_valid = '1'                 report "T1: mac_data_out_valid not asserted";
191
 
192
                -- wait until in eth hdr
193
                wait for clk_period*3;
194
                -- go mac not ready for 2 clocks
195
      mac_data_out_ready <= '0';
196
                wait for clk_period*2;
197
      mac_data_out_ready <= '1';
198
 
199
 
200
                wait until ip_tx_data_out_ready = '1';
201
 
202
                -- start to tx IP data
203
                ip_tx.data.data_out_valid <= '1';
204
                ip_tx.data.data_out <= x"56"; wait for clk_period;
205
                -- delay data in for 1 clk cycle
206
                ip_tx.data.data_out_valid <= '0';
207
                ip_tx.data.data_out <= x"57"; wait for clk_period;
208
                ip_tx.data.data_out_valid <= '1'; wait for clk_period;
209
                ip_tx.data.data_out <= x"58"; wait for clk_period;
210
                ip_tx.data.data_out <= x"59"; wait for clk_period;
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212
                -- delay mac ready for 2 clk cycles
213
                mac_data_out_ready <= '0';
214
                ip_tx.data.data_out <= x"5a"; wait for clk_period;
215
                assert ip_tx_data_out_ready = '0'                        report "T1: ip_tx_data_out_ready not cleared when mac not ready";
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217
                ip_tx.data.data_out <= x"5a"; wait for clk_period;
218
                mac_data_out_ready <= '1';
219
                wait until ip_tx_data_out_ready = '1';
220
                wait for clk_period;
221
                assert ip_tx_data_out_ready = '1'                       report "T1: ip_tx_data_out_ready not set when mac ready";
222
                ip_tx.data.data_out <= x"5b"; wait for clk_period;
223
                ip_tx.data.data_out <= x"5c"; wait for clk_period;
224
 
225
                ip_tx.data.data_out <= x"5d";
226
                ip_tx.data.data_out_last <= '1';
227
                wait for clk_period;
228
                assert mac_data_out_last = '1'                  report "T1: mac_datda_out_last not set on last byte";
229
 
230
                ip_tx.data.data_out_valid <= '0';
231
                ip_tx.data.data_out_last <= '0';
232
                wait for clk_period*2;
233
 
234
                assert ip_tx_result = IPTX_RESULT_SENT  report "T1: result should be IPTX_RESULT_SENT";
235
                assert mac_tx_req = '0'                                  report "T1: mac_tx_req held on too long after TX";
236
 
237
                mac_tx_granted <= '0';
238
                wait for clk_period*2;
239
 
240
                ------------
241
                -- TEST 2 -- basic functional tx test with no delays for arp and chn access
242
                ------------
243
 
244
                report "T2: basic functional tx test with no delays for arp and chn access";
245
 
246
                ip_tx.hdr.protocol <= x"11";
247
                ip_tx.hdr.data_length <= x"0006";
248
                ip_tx.hdr.dst_ip_addr <= x"c0123478";
249
                ip_tx_start <= '1';
250
                wait for clk_period;
251
                ip_tx_start <= '0'; wait for clk_period;
252
                arp_req_rslt.got_mac <= '0';
253
 
254
                assert arp_req_req.lookup_req = '1'                     report "T1: lookup_req not set on tx start";
255
                assert ip_tx_result = IPTX_RESULT_SENDING               report "T1: result should be IPTX_RESULT_SENDING";
256
 
257
                wait for clk_period;            -- simulate arp lookup time
258
                arp_req_rslt.mac <= x"050423271016";
259
                arp_req_rslt.got_mac <= '1';
260
 
261
                wait for clk_period*2;
262
 
263
                assert arp_req_req.lookup_req = '0'                      report "T1: lookup_req not clear after setting";
264
                assert mac_tx_req = '1'                                         report "T1: mac_tx_req not set after getting mac";
265
 
266
                wait for clk_period;            -- simulate mac chn access time
267
                mac_tx_granted <= '1';
268
                wait for clk_period*2;
269
      mac_data_out_ready <= '1';
270
 
271
                assert ip_tx_data_out_ready = '0'        report "T1: IP data out ready asserted too early";
272
 
273
                wait until ip_tx_data_out_ready = '1';
274
 
275
                -- start to tx IP data
276
                ip_tx.data.data_out_valid <= '1';
277
                ip_tx.data.data_out <= x"c1"; wait for clk_period;
278
                ip_tx.data.data_out <= x"c2"; wait for clk_period;
279
                ip_tx.data.data_out <= x"c3"; wait for clk_period;
280
                ip_tx.data.data_out <= x"c4"; wait for clk_period;
281
                ip_tx.data.data_out <= x"c5"; wait for clk_period;
282
 
283
                ip_tx.data.data_out <= x"c6";
284
                ip_tx.data.data_out_last <= '1';
285
                wait for clk_period;
286
 
287
                assert mac_data_out_last = '1'                  report "T1: mac_datda_out_last not set on last byte";
288
 
289
 
290
                ip_tx.data.data_out_valid <= '0';
291
                ip_tx.data.data_out_last <= '0';
292
                wait for clk_period*2;
293
 
294
                assert ip_tx_result = IPTX_RESULT_SENT          report "T1: result should be IPTX_RESULT_SENT";
295
                assert mac_tx_req = '0'                                  report "T1: mac_tx_req held on too long after TX";
296
 
297
                mac_tx_granted <= '0';
298
                wait for clk_period*2;
299
 
300
                report "--- end of tests ---";
301
 
302
      wait;
303
   end process;
304
 
305
END;

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