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[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [UDP_RX_tb.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
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-- Create Date:   16:53:03 06/10/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
8
-- Project Name:  ip1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: UDP_RX
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Additional Comments:
20
--
21
-- Notes: 
22
-- This testbench has been automatically generated using types std_logic and
23
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
-- that these types always be used for the top-level I/O of a design in order
25
-- to guarantee that the testbench will bind correctly to the post-implementation 
26
-- simulation model.
27
--------------------------------------------------------------------------------
28
library IEEE;
29
use IEEE.STD_LOGIC_1164.ALL;
30
use IEEE.NUMERIC_STD.ALL;
31
use work.axi.all;
32
use work.ipv4_types.all;
33
 
34
ENTITY UDP_RX_tb IS
35
END UDP_RX_tb;
36
 
37
ARCHITECTURE behavior OF UDP_RX_tb IS
38
 
39
    -- Component Declaration for the Unit Under Test (UUT)
40
 
41
    COMPONENT UDP_RX
42
    PORT(
43
                        -- UDP Layer signals
44
                        udp_rxo                                 : inout udp_rx_type;
45
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
46
                        -- system signals
47
                        clk                                             : in  STD_LOGIC;
48
                        reset                                   : in  STD_LOGIC;
49
                        -- IP layer RX signals
50
                        ip_rx_start                             : in std_logic;                                                         -- indicates receipt of ip header
51
                        ip_rx                                           : inout ipv4_rx_type
52
        );
53
    END COMPONENT;
54
 
55
 
56
   --Inputs
57
   signal clk : std_logic := '0';
58
   signal reset : std_logic := '0';
59
   signal ip_rx_start : std_logic := '0';
60
 
61
        --BiDirs
62
   signal udp_rxo : udp_rx_type;
63
   signal ip_rx : ipv4_rx_type;
64
 
65
        --Outputs
66
   signal udp_rx_start : std_logic;
67
 
68
   -- Clock period definitions
69
   constant clk_period : time := 8 ns;
70
 
71
BEGIN
72
 
73
        -- Instantiate the Unit Under Test (UUT)
74
   uut: UDP_RX PORT MAP (
75
          udp_rxo => udp_rxo,
76
          udp_rx_start => udp_rx_start,
77
          clk => clk,
78
          reset => reset,
79
          ip_rx_start => ip_rx_start,
80
          ip_rx => ip_rx
81
        );
82
 
83
   -- Clock process definitions
84
   clk_process :process
85
   begin
86
                clk <= '0';
87
                wait for clk_period/2;
88
                clk <= '1';
89
                wait for clk_period/2;
90
   end process;
91
 
92
 
93
   -- Stimulus process
94
   stim_proc: process
95
   begin
96
      -- hold reset state for 100 ns.
97
      wait for 100 ns;
98
                ip_rx_start <= '0';
99
                ip_rx.data.data_in_valid <= '0';
100
      ip_rx.data.data_in_last <= '0';
101
                ip_rx.hdr.is_valid <= '0';
102
                ip_rx.hdr.protocol <= (others => '0');
103
                ip_rx.hdr.num_frame_errors <= (others => '0');
104
                ip_rx.hdr.last_error_code <= (others => '0');
105
 
106
                reset <= '1';
107
      wait for clk_period*10;
108
                reset <= '0';
109
      wait for clk_period*5;
110
                reset <= '0';
111
 
112
                -- check reset conditions
113
                assert udp_rx_start = '0'                                                        report "udp_rx_start not initialised correctly on reset";
114
                assert udp_rxo.hdr.is_valid = '0'                                        report "udp_rxo.hdr.is_valid not initialised correctly on reset";
115
                assert udp_rxo.data.data_in = x"00"                             report "udp_rxo.data.data_in not initialised correctly on reset";
116
                assert udp_rxo.data.data_in_valid = '0'                  report "udp_rxo.data.data_in_valid not initialised correctly on reset";
117
                assert udp_rxo.data.data_in_last = '0'                   report "udp_rxo.data.data_in_last not initialised correctly on reset";
118
 
119
      -- insert stimulus here 
120
 
121
                ------------
122
                -- TEST 1 -- basic functional rx test with received ip pkt
123
                ------------
124
 
125
                report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
126
 
127
                ip_rx_start <= '1';
128
                ip_rx.data.data_in_valid <= '0';
129
      ip_rx.data.data_in_last <= '0';
130
                ip_rx.hdr.is_valid <= '1';
131
                ip_rx.hdr.protocol <= x"11";    -- UDP
132
                ip_rx.hdr.data_length <= x"000b";
133
                ip_rx.hdr.src_ip_addr<= x"c0a80501";
134
                wait for clk_period*3;
135
                -- now send the data
136
                ip_rx.data.data_in_valid <= '1';
137
                ip_rx.data.data_in <= x"14"; wait for clk_period;       -- src port
138
                ip_rx.data.data_in <= x"98"; wait for clk_period;
139
                ip_rx.data.data_in <= x"87"; wait for clk_period;       -- dst port
140
                ip_rx.data.data_in <= x"24"; wait for clk_period;
141
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- len (hdr + data)
142
                ip_rx.data.data_in <= x"0b"; wait for clk_period;
143
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- mty cks
144
                ip_rx.data.data_in <= x"00"; wait for clk_period;
145
                -- udp hdr should be valid
146
                assert udp_rxo.hdr.is_valid = '1'                                       report "T1: udp_rxo.hdr.is_valid not set";
147
 
148
                ip_rx.data.data_in <= x"41"; wait for clk_period;       -- data
149
 
150
                assert udp_rxo.hdr.src_ip_addr = x"c0a80501"    report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
151
                assert udp_rxo.hdr.src_port = x"1498"                   report "T1: udp_rxo.hdr.src_port not set correctly";
152
                assert udp_rxo.hdr.dst_port = x"8724"                   report "T1: udp_rxo.hdr.dst_port not set correctly";
153
                assert udp_rxo.hdr.data_length = x"0003"                report "T1: udp_rxo.hdr.data_length not set correctly";
154
                assert udp_rx_start = '1'                                                       report "T1: udp_rx_start not set";
155
                assert udp_rxo.data.data_in_valid = '1'         report "T1: udp_rxo.data.data_in_valid not set";
156
 
157
                ip_rx.data.data_in <= x"45"; wait for clk_period;       -- data
158
                ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
159
                assert udp_rxo.data.data_in_last = '1'                  report "T1: udp_rxo.data.data_in_last not set";
160
                ip_rx_start <= '0';
161
                ip_rx.data.data_in_valid <= '0';
162
      ip_rx.data.data_in_last <= '0';
163
                ip_rx.hdr.is_valid <= '0';
164
                wait for clk_period;
165
                assert udp_rxo.data.data_in = x"00"                             report "T1: udp_rxo.data.data_in not cleared";
166
                assert udp_rxo.data.data_in_valid = '0'                  report "T1: udp_rxo.data.data_in_valid not cleared";
167
                assert udp_rxo.data.data_in_last = '0'                   report "T1: udp_rxo.data.data_in_last not cleared";
168
 
169
                wait for clk_period;
170
 
171
                ------------
172
                -- TEST 2 -- ability to receive 2nd ip pkt
173
                ------------
174
 
175
                report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
176
 
177
                ip_rx_start <= '1';
178
                ip_rx.data.data_in_valid <= '0';
179
      ip_rx.data.data_in_last <= '0';
180
                ip_rx.hdr.is_valid <= '1';
181
                ip_rx.hdr.protocol <= x"11";    -- UDP
182
                ip_rx.hdr.data_length <= x"000b";
183
                ip_rx.hdr.src_ip_addr<= x"c0a80501";
184
                wait for clk_period*3;
185
                -- now send the data
186
                ip_rx.data.data_in_valid <= '1';
187
                ip_rx.data.data_in <= x"76"; wait for clk_period;       -- src port
188
                ip_rx.data.data_in <= x"23"; wait for clk_period;
189
                ip_rx.data.data_in <= x"03"; wait for clk_period;       -- dst port
190
                ip_rx.data.data_in <= x"65"; wait for clk_period;
191
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- len (hdr + data)
192
                ip_rx.data.data_in <= x"0d"; wait for clk_period;
193
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- mty cks
194
                ip_rx.data.data_in <= x"00"; wait for clk_period;
195
                -- udp hdr should be valid
196
                assert udp_rxo.hdr.is_valid = '1'                                       report "T2: udp_rxo.hdr.is_valid not set";
197
 
198
                ip_rx.data.data_in <= x"17"; wait for clk_period;       -- data
199
 
200
                assert udp_rxo.hdr.src_ip_addr = x"c0a80501"    report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
201
                assert udp_rxo.hdr.src_port = x"7623"                   report "T2: udp_rxo.hdr.src_port not set correctly";
202
                assert udp_rxo.hdr.dst_port = x"0365"                   report "T2: udp_rxo.hdr.dst_port not set correctly";
203
                assert udp_rxo.hdr.data_length = x"0005"                report "T2: udp_rxo.hdr.data_length not set correctly";
204
                assert udp_rx_start = '1'                                                       report "T2: udp_rx_start not set";
205
                assert udp_rxo.data.data_in_valid = '1'         report "T2: udp_rxo.data.data_in_valid not set";
206
 
207
                ip_rx.data.data_in <= x"37"; wait for clk_period;       -- data
208
                ip_rx.data.data_in <= x"57"; wait for clk_period;       -- data
209
                ip_rx.data.data_in <= x"73"; wait for clk_period;       -- data
210
                ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
211
                assert udp_rxo.data.data_in_last = '1'                  report "T2: udp_rxo.data.data_in_last not set";
212
                ip_rx_start <= '0';
213
                ip_rx.data.data_in_valid <= '0';
214
      ip_rx.data.data_in_last <= '0';
215
                ip_rx.hdr.is_valid <= '0';
216
                wait for clk_period;
217
                assert udp_rxo.data.data_in = x"00"                             report "T2: udp_rxo.data.data_in not cleared";
218
                assert udp_rxo.data.data_in_valid = '0'                  report "T2: udp_rxo.data.data_in_valid not cleared";
219
                assert udp_rxo.data.data_in_last = '0'                   report "T2: udp_rxo.data.data_in_last not cleared";
220
 
221
                ------------
222
                -- TEST 3 -- ability to reject non-udp protocols
223
                ------------
224
 
225
                report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
226
 
227
                ip_rx_start <= '1';
228
                ip_rx.data.data_in_valid <= '0';
229
      ip_rx.data.data_in_last <= '0';
230
                ip_rx.hdr.is_valid <= '1';
231
                ip_rx.hdr.protocol <= x"12";    -- non-UDP
232
                ip_rx.hdr.data_length <= x"000b";
233
                ip_rx.hdr.src_ip_addr<= x"c0a80501";
234
                wait for clk_period*3;
235
                -- now send the data
236
                ip_rx.data.data_in_valid <= '1';
237
                ip_rx.data.data_in <= x"76"; wait for clk_period;       -- src port
238
                ip_rx.data.data_in <= x"23"; wait for clk_period;
239
                ip_rx.data.data_in <= x"03"; wait for clk_period;       -- dst port
240
                ip_rx.data.data_in <= x"65"; wait for clk_period;
241
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- len (hdr + data)
242
                ip_rx.data.data_in <= x"0d"; wait for clk_period;
243
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- mty cks
244
                ip_rx.data.data_in <= x"00"; wait for clk_period;
245
                -- udp hdr should be valid
246
                assert udp_rxo.hdr.is_valid = '0'                                        report "T3: udp_rxo.hdr.is_valid incorrectly set";
247
 
248
                ip_rx.data.data_in <= x"17"; wait for clk_period;       -- data
249
 
250
                assert udp_rx_start = '0'                                                        report "T3: udp_rx_start incorrectly set";
251
                assert udp_rxo.data.data_in_valid = '0'          report "T3: udp_rxo.data.data_in_valid not set";
252
 
253
                ip_rx.data.data_in <= x"37"; wait for clk_period;       -- data
254
                ip_rx.data.data_in <= x"57"; wait for clk_period;       -- data
255
                ip_rx.data.data_in <= x"73"; wait for clk_period;       -- data
256
                ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
257
                assert udp_rxo.data.data_in_last = '0'                   report "T3: udp_rxo.data.data_in_last incorrectly set";
258
                ip_rx_start <= '0';
259
                ip_rx.data.data_in_valid <= '0';
260
      ip_rx.data.data_in_last <= '0';
261
                ip_rx.hdr.is_valid <= '0';
262
                wait for clk_period;
263
                assert udp_rxo.data.data_in = x"00"                             report "T3: udp_rxo.data.data_in not cleared";
264
                assert udp_rxo.data.data_in_valid = '0'                  report "T3: udp_rxo.data.data_in_valid not cleared";
265
                assert udp_rxo.data.data_in_last = '0'                   report "T3: udp_rxo.data.data_in_last not cleared";
266
 
267
                wait for clk_period;
268
 
269
                ------------
270
                -- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
271
                ------------
272
 
273
                report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
274
 
275
                ip_rx_start <= '1';
276
                ip_rx.data.data_in_valid <= '0';
277
      ip_rx.data.data_in_last <= '0';
278
                ip_rx.hdr.is_valid <= '1';
279
                ip_rx.hdr.protocol <= x"11";    -- UDP
280
                ip_rx.hdr.data_length <= x"000b";
281
                ip_rx.hdr.src_ip_addr<= x"c0a80501";
282
                wait for clk_period*3;
283
                -- now send the data
284
                ip_rx.data.data_in_valid <= '1';
285
                ip_rx.data.data_in <= x"14"; wait for clk_period;       -- src port
286
                ip_rx.data.data_in <= x"98"; wait for clk_period;
287
                ip_rx.data.data_in <= x"87"; wait for clk_period;       -- dst port
288
                ip_rx.data.data_in <= x"24"; wait for clk_period;
289
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- len (hdr + data)
290
                ip_rx.data.data_in <= x"0b"; wait for clk_period;
291
                ip_rx.data.data_in <= x"00"; wait for clk_period;       -- mty cks
292
                ip_rx.data.data_in <= x"00"; wait for clk_period;
293
                -- udp hdr should be valid
294
                assert udp_rxo.hdr.is_valid = '1'                                       report "T4: udp_rxo.hdr.is_valid not set";
295
 
296
                ip_rx.data.data_in <= x"41"; wait for clk_period;       -- data
297
 
298
                assert udp_rxo.hdr.src_ip_addr = x"c0a80501"    report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
299
                assert udp_rxo.hdr.src_port = x"1498"                   report "T4: udp_rxo.hdr.src_port not set correctly";
300
                assert udp_rxo.hdr.dst_port = x"8724"                   report "T4: udp_rxo.hdr.dst_port not set correctly";
301
                assert udp_rxo.hdr.data_length = x"0003"                report "T4: udp_rxo.hdr.data_length not set correctly";
302
                assert udp_rx_start = '1'                                                       report "T4: udp_rx_start not set";
303
                assert udp_rxo.data.data_in_valid = '1'         report "T4: udp_rxo.data.data_in_valid not set";
304
 
305
                ip_rx.data.data_in <= x"45"; wait for clk_period;       -- data
306
                ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
307
                assert udp_rxo.data.data_in_last = '1'                  report "T4: udp_rxo.data.data_in_last not set";
308
                ip_rx_start <= '0';
309
                ip_rx.data.data_in_valid <= '0';
310
      ip_rx.data.data_in_last <= '0';
311
                ip_rx.hdr.is_valid <= '0';
312
                wait for clk_period;
313
                assert udp_rxo.data.data_in = x"00"                             report "T4: udp_rxo.data.data_in not cleared";
314
                assert udp_rxo.data.data_in_valid = '0'                  report "T4: udp_rxo.data.data_in_valid not cleared";
315
                assert udp_rxo.data.data_in_last = '0'                   report "T4: udp_rxo.data.data_in_last not cleared";
316
 
317
                wait for clk_period;
318
 
319
                report "--- end of tests ---";
320
 
321
                wait;
322
        end process;
323
 
324
END;

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