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pjf |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09:57:01 06/13/2011
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-- Design Name:
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
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-- Project Name: udp1
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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ENTITY UDP_complete_nomac_tb IS
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END UDP_complete_nomac_tb;
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ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT UDP_Complete_nomac
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PORT(
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
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-- UDP RX signals
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rxo : out udp_rx_type;
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-- IP RX signals
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ip_rx_hdr : out ipv4_rx_header_type;
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-- system signals
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rx_clk : in STD_LOGIC;
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tx_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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-- status signals
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arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
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ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
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-- MAC Transmitter
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mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
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mac_tx_tvalid : out std_logic; -- tdata is valid
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mac_tx_tready : in std_logic; -- mac is ready to accept data
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4 |
pjf |
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
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mac_tx_tlast : out std_logic; -- indicates last byte of frame
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-- MAC Receiver
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mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
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mac_rx_tvalid : in std_logic; -- indicates tdata is valid
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mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
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mac_rx_tlast : in std_logic -- indicates last byte of the trame
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);
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END COMPONENT;
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type state_type is (IDLE, DATA_OUT);
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type count_mode_type is (RST, INCR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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--Inputs
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signal udp_tx_start_int : std_logic := '0';
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signal udp_tx_int : udp_tx_type;
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signal clk_int : std_logic := '0';
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signal reset : std_logic := '0';
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signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
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signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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signal mac_tx_tready : std_logic := '0';
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signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
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signal mac_rx_tvalid : std_logic := '0';
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signal mac_rx_tlast : std_logic := '0';
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--Outputs
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signal udp_rx_start_int : std_logic;
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signal udp_rx_int : udp_rx_type;
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signal ip_rx_hdr : ipv4_rx_header_type;
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signal udp_tx_result : std_logic_vector (1 downto 0);
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signal udp_tx_data_out_ready_int: std_logic;
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signal arp_pkt_count : std_logic_vector(7 downto 0);
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signal ip_pkt_count : std_logic_vector(7 downto 0);
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signal mac_tx_tdata : std_logic_vector(7 downto 0);
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signal mac_tx_tvalid : std_logic;
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4 |
pjf |
signal mac_tx_tfirst : std_logic;
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2 |
pjf |
signal mac_tx_tlast : std_logic;
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signal mac_rx_tready : std_logic;
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signal pbtx_led : std_logic;
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signal pbtx : std_logic := '0';
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-- state signals
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signal state : state_type;
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signal count : unsigned (7 downto 0);
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signal tx_hdr : udp_tx_header_type;
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signal tx_start_reg : std_logic;
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signal tx_started_reg : std_logic;
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signal tx_fin_reg : std_logic;
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-- control signals
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signal next_state : state_type;
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signal set_state : std_logic;
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signal set_count : count_mode_type;
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signal set_hdr : std_logic;
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signal set_tx_start : set_clr_type;
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signal tx_data : std_logic_vector (7 downto 0);
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signal set_last : std_logic;
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signal set_tx_started : set_clr_type;
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signal set_tx_fin : set_clr_type;
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: UDP_Complete_nomac PORT MAP (
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udp_tx_start => udp_tx_start_int,
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udp_txi => udp_tx_int,
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udp_tx_result => udp_tx_result,
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udp_tx_data_out_ready => udp_tx_data_out_ready_int,
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udp_rx_start => udp_rx_start_int,
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udp_rxo => udp_rx_int,
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ip_rx_hdr => ip_rx_hdr,
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rx_clk => clk_int,
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tx_clk => clk_int,
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reset => reset,
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our_ip_address => our_ip_address,
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our_mac_address => our_mac_address,
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arp_pkt_count => arp_pkt_count,
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ip_pkt_count => ip_pkt_count,
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mac_tx_tdata => mac_tx_tdata,
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mac_tx_tvalid => mac_tx_tvalid,
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mac_tx_tready => mac_tx_tready,
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4 |
pjf |
mac_tx_tfirst => mac_tx_tfirst,
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2 |
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mac_tx_tlast => mac_tx_tlast,
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mac_rx_tdata => mac_rx_tdata,
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mac_rx_tvalid => mac_rx_tvalid,
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mac_rx_tready => mac_rx_tready,
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mac_rx_tlast => mac_rx_tlast
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk_int <= '0';
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wait for clk_period/2;
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clk_int <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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our_ip_address <= x"c0a80509"; -- 192.168.5.9
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our_mac_address <= x"002320212223";
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mac_tx_tready <= '0';
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reset <= '1';
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wait for clk_period*10;
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reset <= '0';
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wait for clk_period*5;
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-- check reset conditions
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assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
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assert udp_tx_data_out_ready_int = '0' report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
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assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
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assert mac_tx_tlast = '0' report "mac_tx_tlast not initialised correctly on reset";
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assert arp_pkt_count = x"00" report "arp_pkt_count not initialised correctly on reset";
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assert ip_pkt_count = x"00" report "ip_pkt_count not initialised correctly on reset";
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assert udp_rx_start_int = '0' report "udp_rx_start not initialised correctly on reset";
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assert udp_rx_int.hdr.is_valid = '0' report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
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assert udp_rx_int.hdr.data_length = x"0000" report "udp_rx_int.hdr.data_length not initialised correctly on reset";
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assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
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assert udp_rx_int.hdr.src_port = x"0000" report "udp_rx_int.hdr.src_port not initialised correctly on reset";
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assert udp_rx_int.hdr.dst_port = x"0000" report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
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assert udp_rx_int.data.data_in = x"00" report "udp_rx_start.data.data_in not initialised correctly on reset";
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assert udp_rx_int.data.data_in_valid = '0' report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
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assert udp_rx_int.data.data_in_last = '0' report "udp_rx_start.data.data_in_last not initialised correctly on reset";
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assert ip_rx_hdr.is_valid = '0' report "ip_rx_hdr.is_valid not initialised correctly on reset";
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assert ip_rx_hdr.protocol = x"00" report "ip_rx_hdr.protocol not initialised correctly on reset";
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assert ip_rx_hdr.data_length = x"0000" report "ip_rx_hdr.data_length not initialised correctly on reset";
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assert ip_rx_hdr.src_ip_addr = x"00000000" report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
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assert ip_rx_hdr.num_frame_errors = x"00" report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
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-- insert stimulus here
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------------
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-- TEST 1 -- send ARP request
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------------
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report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
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mac_tx_tready <= '1';
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mac_rx_tvalid <= '1';
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-- dst MAC (bc)
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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-- src MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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mac_rx_tdata <= x"29"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"7c"; wait for clk_period;
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-- type
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mac_rx_tdata <= x"08"; wait for clk_period;
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mac_rx_tdata <= x"06"; wait for clk_period;
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-- HW type
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Protocol type
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mac_rx_tdata <= x"08"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- HW size
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mac_rx_tdata <= x"06"; wait for clk_period;
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-- protocol size
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mac_rx_tdata <= x"04"; wait for clk_period;
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-- Opcode
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Sender MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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mac_rx_tdata <= x"29"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"7c"; wait for clk_period;
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-- Sender IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Target MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- Target IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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| 279 |
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"09"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tlast <= '1';
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tlast <= '0';
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mac_rx_tvalid <= '0';
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-- check we got the ARP pkt
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assert arp_pkt_count = x"01" report "T1: arp_pkt_count wrong value";
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| 291 |
|
|
assert ip_pkt_count = x"00" report "T1: ip_pkt_count wrong value";
|
| 292 |
|
|
assert udp_tx_result = UDPTX_RESULT_NONE report "T1: udp_tx_result wrong value";
|
| 293 |
|
|
assert udp_tx_data_out_ready_int = '0' report "T1: ip_udp_txitx.data.data_out_ready wrong value";
|
| 294 |
|
|
assert udp_rx_start_int = '0' report "T1: udp_rx_start wrong value";
|
| 295 |
|
|
assert udp_rx_int.hdr.is_valid = '0' report "T1: udp_rx_int.hdr.is_valid wrong value";
|
| 296 |
|
|
assert ip_rx_hdr.is_valid = '0' report "T1: ip_rx_hdr.is_valid wrong value";
|
| 297 |
|
|
|
| 298 |
|
|
-- check we tx a response
|
| 299 |
|
|
|
| 300 |
|
|
wait for clk_period*25;
|
| 301 |
|
|
assert mac_tx_tvalid = '1' report "T1: not transmitting a response";
|
| 302 |
|
|
wait for clk_period*25;
|
| 303 |
|
|
assert mac_tx_tvalid = '0' report "T1: tx held on for too long";
|
| 304 |
|
|
|
| 305 |
|
|
------------
|
| 306 |
|
|
-- TEST 2 -- send UDP pkt (same as sample from Java program
|
| 307 |
|
|
------------
|
| 308 |
|
|
|
| 309 |
|
|
report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
| 310 |
|
|
|
| 311 |
|
|
mac_rx_tvalid <= '1';
|
| 312 |
|
|
-- dst MAC (bc)
|
| 313 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 314 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 315 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
| 316 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
| 317 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
| 318 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 319 |
|
|
-- src MAC
|
| 320 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 321 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 322 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
| 323 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
| 324 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
| 325 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
| 326 |
|
|
-- type
|
| 327 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
| 328 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 329 |
|
|
-- ver & HL / service type
|
| 330 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
| 331 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 332 |
|
|
-- total len
|
| 333 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 334 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
| 335 |
|
|
-- ID
|
| 336 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 337 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
| 338 |
|
|
-- flags & frag
|
| 339 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 340 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 341 |
|
|
-- TTL
|
| 342 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
| 343 |
|
|
-- Protocol
|
| 344 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
| 345 |
|
|
-- Header CKS
|
| 346 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 347 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 348 |
|
|
-- SRC IP
|
| 349 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 350 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
| 351 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
| 352 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
| 353 |
|
|
-- DST IP
|
| 354 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 355 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
| 356 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
| 357 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
| 358 |
|
|
-- SRC port
|
| 359 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
| 360 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
| 361 |
|
|
-- DST port
|
| 362 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
| 363 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
| 364 |
|
|
-- length
|
| 365 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 366 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
| 367 |
|
|
-- cks
|
| 368 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
| 369 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
| 370 |
|
|
-- user data
|
| 371 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
| 372 |
|
|
|
| 373 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
| 374 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T2: udp_rx_int.hdr.is_valid not set";
|
| 375 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T2: udp_rx_int.hdr.data_length not set correctly";
|
| 376 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
|
| 377 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T2: udp_rx_int.hdr.src_port not set correctly";
|
| 378 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T2: udp_rx_int.hdr.dst_port not set correctly";
|
| 379 |
|
|
|
| 380 |
|
|
assert udp_rx_start_int = '1' report "T2: udp_rx_start not set";
|
| 381 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T2: udp_rx_int.data.data_in_valid not set";
|
| 382 |
|
|
|
| 383 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T2: ip_rx_hdr.is_valid not set";
|
| 384 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T2: ip_rx_hdr.protocol not set correctly";
|
| 385 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
|
| 386 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
|
| 387 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
|
| 388 |
|
|
|
| 389 |
|
|
-- put the rest of the user data
|
| 390 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
| 391 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
| 392 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
| 393 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
| 394 |
|
|
|
| 395 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T2: udp_rx_int.data.data_in_last not set";
|
| 396 |
|
|
|
| 397 |
|
|
mac_rx_tdata <= x"00";
|
| 398 |
|
|
mac_rx_tlast <= '0';
|
| 399 |
|
|
mac_rx_tvalid <= '0';
|
| 400 |
|
|
wait for clk_period;
|
| 401 |
|
|
|
| 402 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T2: udp_rx_int.data.data_in_valid not cleared";
|
| 403 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T2: udp_rx_int.data.data_in_last not cleared";
|
| 404 |
|
|
assert udp_rx_start_int = '0' report "T2: udp_rx_start not cleared";
|
| 405 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
|
| 406 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
|
| 407 |
|
|
assert ip_pkt_count = x"01" report "T2: ip pkt cnt incorrect";
|
| 408 |
|
|
|
| 409 |
|
|
wait for clk_period*20;
|
| 410 |
|
|
|
| 411 |
|
|
------------
|
| 412 |
|
|
-- TEST 3 -- send UDP pkt again (same as sample from Java program
|
| 413 |
|
|
------------
|
| 414 |
|
|
|
| 415 |
|
|
report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
| 416 |
|
|
|
| 417 |
|
|
mac_rx_tvalid <= '1';
|
| 418 |
|
|
-- dst MAC (bc)
|
| 419 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 420 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 421 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
| 422 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
| 423 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
| 424 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 425 |
|
|
-- src MAC
|
| 426 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 427 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
| 428 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
| 429 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
| 430 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
| 431 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
| 432 |
|
|
-- type
|
| 433 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
| 434 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 435 |
|
|
-- ver & HL / service type
|
| 436 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
| 437 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 438 |
|
|
-- total len
|
| 439 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 440 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
| 441 |
|
|
-- ID
|
| 442 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 443 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
| 444 |
|
|
-- flags & frag
|
| 445 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 446 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 447 |
|
|
-- TTL
|
| 448 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
| 449 |
|
|
-- Protocol
|
| 450 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
| 451 |
|
|
-- Header CKS
|
| 452 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 453 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 454 |
|
|
-- SRC IP
|
| 455 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 456 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
| 457 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
| 458 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
| 459 |
|
|
-- DST IP
|
| 460 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
| 461 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
| 462 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
| 463 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
| 464 |
|
|
-- SRC port
|
| 465 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
| 466 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
| 467 |
|
|
-- DST port
|
| 468 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
| 469 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
| 470 |
|
|
-- length
|
| 471 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
| 472 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
| 473 |
|
|
-- cks
|
| 474 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
| 475 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
| 476 |
|
|
-- user data
|
| 477 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
| 478 |
|
|
|
| 479 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
| 480 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T3: udp_rx_int.hdr.is_valid not set";
|
| 481 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T3: udp_rx_int.hdr.data_length not set correctly";
|
| 482 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
|
| 483 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T3: udp_rx_int.hdr.src_port not set correctly";
|
| 484 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T3: udp_rx_int.hdr.dst_port not set correctly";
|
| 485 |
|
|
|
| 486 |
|
|
assert udp_rx_start_int = '1' report "T3: udp_rx_start not set";
|
| 487 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T3: udp_rx_int.data.data_in_valid not set";
|
| 488 |
|
|
|
| 489 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T3: ip_rx_hdr.is_valid not set";
|
| 490 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T3: ip_rx_hdr.protocol not set correctly";
|
| 491 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T3: ip_rx.hdr.src_ip_addr not set correctly";
|
| 492 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx.hdr.num_frame_errors not set correctly";
|
| 493 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx.hdr.last_error_code not set correctly";
|
| 494 |
|
|
|
| 495 |
|
|
-- put the rest of the user data
|
| 496 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
| 497 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
| 498 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
| 499 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
| 500 |
|
|
|
| 501 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T3: udp_rx_int.data.data_in_last not set";
|
| 502 |
|
|
|
| 503 |
|
|
mac_rx_tdata <= x"00";
|
| 504 |
|
|
mac_rx_tlast <= '0';
|
| 505 |
|
|
mac_rx_tvalid <= '0';
|
| 506 |
|
|
wait for clk_period;
|
| 507 |
|
|
|
| 508 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T3: udp_rx_int.data.data_in_valid not cleared";
|
| 509 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T3: udp_rx_int.data.data_in_last not cleared";
|
| 510 |
|
|
assert udp_rx_start_int = '0' report "T3: udp_rx_start not cleared";
|
| 511 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
|
| 512 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
|
| 513 |
|
|
assert ip_pkt_count = x"02" report "T3: ip pkt cnt incorrect";
|
| 514 |
|
|
|
| 515 |
|
|
report "--- end of tests ---";
|
| 516 |
|
|
wait;
|
| 517 |
|
|
end process;
|
| 518 |
|
|
|
| 519 |
|
|
-- AUTO TX process - on receipt of any UDP pkt, send a response
|
| 520 |
|
|
|
| 521 |
|
|
-- TX response process - COMB
|
| 522 |
|
|
tx_proc_combinatorial: process(
|
| 523 |
|
|
-- inputs
|
| 524 |
|
|
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX,
|
| 525 |
|
|
-- state
|
| 526 |
|
|
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
|
| 527 |
|
|
-- controls
|
| 528 |
|
|
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
|
| 529 |
|
|
set_tx_started, set_tx_fin
|
| 530 |
|
|
)
|
| 531 |
|
|
begin
|
| 532 |
|
|
-- set output_followers
|
| 533 |
|
|
udp_tx_int.hdr <= tx_hdr;
|
| 534 |
|
|
udp_tx_int.data.data_out_last <= set_last;
|
| 535 |
|
|
udp_tx_start_int <= tx_start_reg;
|
| 536 |
|
|
|
| 537 |
|
|
-- set control signal defaults
|
| 538 |
|
|
next_state <= IDLE;
|
| 539 |
|
|
set_state <= '0';
|
| 540 |
|
|
set_count <= HOLD;
|
| 541 |
|
|
set_hdr <= '0';
|
| 542 |
|
|
set_tx_start <= HOLD;
|
| 543 |
|
|
set_last <= '0';
|
| 544 |
|
|
set_tx_started <= HOLD;
|
| 545 |
|
|
set_tx_fin <= HOLD;
|
| 546 |
|
|
|
| 547 |
|
|
-- FSM
|
| 548 |
|
|
case state is
|
| 549 |
|
|
|
| 550 |
|
|
when IDLE =>
|
| 551 |
|
|
udp_tx_int.data.data_out <= (others => '0');
|
| 552 |
|
|
udp_tx_int.data.data_out_valid <= '0';
|
| 553 |
|
|
if udp_rx_start_int = '1' or PBTX = '1' then
|
| 554 |
|
|
set_tx_started <= SET;
|
| 555 |
|
|
set_hdr <= '1';
|
| 556 |
|
|
set_tx_start <= SET;
|
| 557 |
|
|
set_tx_fin <= CLR;
|
| 558 |
|
|
set_count <= RST;
|
| 559 |
|
|
next_state <= DATA_OUT;
|
| 560 |
|
|
set_state <= '1';
|
| 561 |
|
|
end if;
|
| 562 |
|
|
|
| 563 |
|
|
when DATA_OUT =>
|
| 564 |
|
|
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
|
| 565 |
|
|
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
|
| 566 |
|
|
if udp_tx_data_out_ready_int = '1' then
|
| 567 |
|
|
set_tx_start <= CLR;
|
| 568 |
|
|
if unsigned(count) = x"03" then
|
| 569 |
|
|
set_last <= '1';
|
| 570 |
|
|
set_tx_fin <= SET;
|
| 571 |
|
|
set_tx_started <= CLR;
|
| 572 |
|
|
next_state <= IDLE;
|
| 573 |
|
|
set_state <= '1';
|
| 574 |
|
|
else
|
| 575 |
|
|
set_count <= INCR;
|
| 576 |
|
|
end if;
|
| 577 |
|
|
end if;
|
| 578 |
|
|
|
| 579 |
|
|
end case;
|
| 580 |
|
|
end process;
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
|
| 584 |
|
|
-- TX response process - SEQ
|
| 585 |
|
|
tx_proc_sequential: process(clk_int)
|
| 586 |
|
|
begin
|
| 587 |
|
|
if rising_edge(clk_int) then
|
| 588 |
|
|
if reset = '1' then
|
| 589 |
|
|
-- reset state variables
|
| 590 |
|
|
state <= IDLE;
|
| 591 |
|
|
count <= x"00";
|
| 592 |
|
|
tx_start_reg <= '0';
|
| 593 |
|
|
tx_hdr.dst_ip_addr <= (others => '0');
|
| 594 |
|
|
tx_hdr.dst_port <= (others => '0');
|
| 595 |
|
|
tx_hdr.src_port <= (others => '0');
|
| 596 |
|
|
tx_hdr.data_length <= (others => '0');
|
| 597 |
|
|
tx_hdr.checksum <= (others => '0');
|
| 598 |
|
|
tx_started_reg <= '0';
|
| 599 |
|
|
tx_fin_reg <= '0';
|
| 600 |
|
|
PBTX_LED <= '0';
|
| 601 |
|
|
else
|
| 602 |
|
|
PBTX_LED <= PBTX;
|
| 603 |
|
|
|
| 604 |
|
|
-- Next rx_state processing
|
| 605 |
|
|
if set_state = '1' then
|
| 606 |
|
|
state <= next_state;
|
| 607 |
|
|
else
|
| 608 |
|
|
state <= state;
|
| 609 |
|
|
end if;
|
| 610 |
|
|
|
| 611 |
|
|
-- count processing
|
| 612 |
|
|
case set_count is
|
| 613 |
|
|
when RST => count <= x"00";
|
| 614 |
|
|
when INCR => count <= count + 1;
|
| 615 |
|
|
when HOLD => count <= count;
|
| 616 |
|
|
end case;
|
| 617 |
|
|
|
| 618 |
|
|
-- set tx hdr
|
| 619 |
|
|
if set_hdr = '1' then
|
| 620 |
|
|
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
|
| 621 |
|
|
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
|
| 622 |
|
|
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
|
| 623 |
|
|
tx_hdr.data_length <= x"0004";
|
| 624 |
|
|
tx_hdr.checksum <= x"0000";
|
| 625 |
|
|
else
|
| 626 |
|
|
tx_hdr <= tx_hdr;
|
| 627 |
|
|
end if;
|
| 628 |
|
|
|
| 629 |
|
|
-- set tx start signal
|
| 630 |
|
|
case set_tx_start is
|
| 631 |
|
|
when SET => tx_start_reg <= '1';
|
| 632 |
|
|
when CLR => tx_start_reg <= '0';
|
| 633 |
|
|
when HOLD => tx_start_reg <= tx_start_reg;
|
| 634 |
|
|
end case;
|
| 635 |
|
|
|
| 636 |
|
|
-- set tx started signal
|
| 637 |
|
|
case set_tx_started is
|
| 638 |
|
|
when SET => tx_started_reg <= '1';
|
| 639 |
|
|
when CLR => tx_started_reg <= '0';
|
| 640 |
|
|
when HOLD => tx_started_reg <= tx_started_reg;
|
| 641 |
|
|
end case;
|
| 642 |
|
|
|
| 643 |
|
|
-- set tx finished signal
|
| 644 |
|
|
case set_tx_fin is
|
| 645 |
|
|
when SET => tx_fin_reg <= '1';
|
| 646 |
|
|
when CLR => tx_fin_reg <= '0';
|
| 647 |
|
|
when HOLD => tx_fin_reg <= tx_fin_reg;
|
| 648 |
|
|
end case;
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
end if;
|
| 652 |
|
|
end if;
|
| 653 |
|
|
|
| 654 |
|
|
end process;
|
| 655 |
|
|
|
| 656 |
|
|
END;
|
