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[/] [udp_ip_stack/] [trunk/] [contrib/] [Headers sometimes have errors/] [ten_100_1g_eth_fifo.vhd] - Blame information for rev 35

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--------------------------------------------------------------------------------
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-- Title      : 10/100/1G Ethernet FIFO
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-- Version    : 1.2
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-- Project    : Tri-Mode Ethernet MAC
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--------------------------------------------------------------------------------
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-- File       : ten_100_1g_eth_fifo.vhd
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-- Author     : Xilinx Inc.
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-- Project    : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
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-- File       : ten_100_1g_eth_fifo.vhd
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-- Version    : 2.1
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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
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--              The top level wrapper consists of individual FIFOs on the
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--              transmitter path and on the receiver path.
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--
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--              Each path consists of an 8 bit local link to 8 bit client
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--              interface FIFO.
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--------------------------------------------------------------------------------
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library unisim;
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use unisim.vcomponents.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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--------------------------------------------------------------------------------
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-- The entity declaration for the FIFO
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--------------------------------------------------------------------------------
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entity ten_100_1g_eth_fifo is
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   generic (
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        FULL_DUPLEX_ONLY    : boolean := false);      -- If fifo is to be used only in full
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                                              -- duplex set to true for optimised implementation
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   port (
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        tx_fifo_aclk                : in  std_logic;
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        tx_fifo_resetn              : in  std_logic;
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        tx_axis_fifo_tdata          : in  std_logic_vector(7 downto 0);
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        tx_axis_fifo_tvalid         : in  std_logic;
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        tx_axis_fifo_tlast          : in  std_logic;
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        tx_axis_fifo_tready         : out std_logic;
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        tx_mac_aclk                 : in  std_logic;
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        tx_mac_resetn               : in  std_logic;
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        tx_axis_mac_tdata           : out std_logic_vector(7 downto 0);
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        tx_axis_mac_tvalid          : out std_logic;
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        tx_axis_mac_tlast           : out std_logic;
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        tx_axis_mac_tready          : in  std_logic;
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        tx_axis_mac_tuser           : out std_logic;
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        tx_fifo_overflow            : out std_logic;
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        tx_fifo_status              : out std_logic_vector(3 downto 0);
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        tx_collision                : in  std_logic;
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        tx_retransmit               : in  std_logic;
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        rx_fifo_aclk                : in  std_logic;
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        rx_fifo_resetn              : in  std_logic;
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        rx_axis_fifo_tdata          : out std_logic_vector(7 downto 0);
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        rx_axis_fifo_tvalid         : out std_logic;
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        rx_axis_fifo_tlast          : out std_logic;
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        rx_axis_fifo_tready         : in  std_logic;
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        rx_mac_aclk                 : in  std_logic;
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        rx_mac_resetn               : in  std_logic;
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        rx_axis_mac_tdata           : in  std_logic_vector(7 downto 0);
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        rx_axis_mac_tvalid          : in  std_logic;
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        rx_axis_mac_tlast           : in  std_logic;
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        rx_axis_mac_tready          : out std_logic;
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        rx_axis_mac_tuser           : in  std_logic;
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        rx_fifo_status              : out std_logic_vector(3 downto 0);
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        rx_fifo_overflow            : out std_logic
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  );
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end ten_100_1g_eth_fifo;
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architecture RTL of ten_100_1g_eth_fifo is
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component rx_client_fifo
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  port (
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     -- User-side (read-side) AxiStream interface
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     rx_fifo_aclk   : in  std_logic;
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     rx_fifo_resetn : in  std_logic;
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     rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
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     rx_axis_fifo_tvalid : out std_logic;
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     rx_axis_fifo_tlast : out std_logic;
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     rx_axis_fifo_tready : in  std_logic;
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     -- MAC-side (write-side) AxiStream interface
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     rx_mac_aclk    : in  std_logic;
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     rx_mac_resetn  : in  std_logic;
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     rx_axis_mac_tdata : in  std_logic_vector(7 downto 0);
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     rx_axis_mac_tvalid : in  std_logic;
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     rx_axis_mac_tlast : in  std_logic;
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     rx_axis_mac_tready : out std_logic;
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     rx_axis_mac_tuser : in  std_logic;
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     -- FIFO status and overflow indication,
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     -- synchronous to write-side (rx_mac_aclk) interface
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     fifo_status    : out std_logic_vector(3 downto 0);
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     fifo_overflow  : out std_logic
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     );
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end component;
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component tx_client_fifo
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   generic (
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      FULL_DUPLEX_ONLY : boolean := false);
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   port (
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        -- User-side (write-side) AxiStream interface
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        tx_fifo_aclk    : in  std_logic;
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        tx_fifo_resetn  : in  std_logic;
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        tx_axis_fifo_tdata : in  std_logic_vector(7 downto 0);
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        tx_axis_fifo_tvalid : in  std_logic;
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        tx_axis_fifo_tlast : in  std_logic;
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        tx_axis_fifo_tready : out std_logic;
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        -- MAC-side (read-side) AxiStream interface
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        tx_mac_aclk     : in  std_logic;
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        tx_mac_resetn   : in  std_logic;
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        tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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        tx_axis_mac_tvalid : out std_logic;
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        tx_axis_mac_tlast : out std_logic;
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        tx_axis_mac_tready : in  std_logic;
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        tx_axis_mac_tuser : out std_logic;
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        -- FIFO status and overflow indication,
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        -- synchronous to write-side (tx_user_aclk) interface
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        fifo_overflow   : out std_logic;
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        fifo_status     : out std_logic_vector(3 downto 0);
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        -- FIFO collision and retransmission requests from MAC
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        tx_collision    : in  std_logic;
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        tx_retransmit   : in  std_logic
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        );
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end component;
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begin
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  ------------------------------------------------------------------------------
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  -- Instantiate the Transmitter FIFO
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  ------------------------------------------------------------------------------
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  tx_fifo_i : tx_client_fifo
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  generic map(
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    FULL_DUPLEX_ONLY   => FULL_DUPLEX_ONLY
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  )
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  port map(
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    tx_fifo_aclk       => tx_fifo_aclk,
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    tx_fifo_resetn     => tx_fifo_resetn,
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    tx_axis_fifo_tdata => tx_axis_fifo_tdata,
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    tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
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    tx_axis_fifo_tlast => tx_axis_fifo_tlast,
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    tx_axis_fifo_tready => tx_axis_fifo_tready,
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    tx_mac_aclk        => tx_mac_aclk,
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    tx_mac_resetn      => tx_mac_resetn,
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    tx_axis_mac_tdata  => tx_axis_mac_tdata,
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    tx_axis_mac_tvalid => tx_axis_mac_tvalid,
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    tx_axis_mac_tlast  => tx_axis_mac_tlast,
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    tx_axis_mac_tready => tx_axis_mac_tready,
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    tx_axis_mac_tuser  => tx_axis_mac_tuser,
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    fifo_overflow      => tx_fifo_overflow,
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    fifo_status        => tx_fifo_status,
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    tx_collision       => tx_collision,
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    tx_retransmit      => tx_retransmit
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  );
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  ------------------------------------------------------------------------------
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  -- Instantiate the Receiver FIFO
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  ------------------------------------------------------------------------------
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  rx_fifo_i : rx_client_fifo
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  port map(
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    rx_fifo_aclk       => rx_fifo_aclk,
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    rx_fifo_resetn     => rx_fifo_resetn,
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    rx_axis_fifo_tdata => rx_axis_fifo_tdata,
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    rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
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    rx_axis_fifo_tlast => rx_axis_fifo_tlast,
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    rx_axis_fifo_tready => rx_axis_fifo_tready,
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    rx_mac_aclk        => rx_mac_aclk,
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    rx_mac_resetn      => rx_mac_resetn,
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    rx_axis_mac_tdata  => rx_axis_mac_tdata,
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    rx_axis_mac_tvalid => rx_axis_mac_tvalid,
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    rx_axis_mac_tlast  => rx_axis_mac_tlast,
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    rx_axis_mac_tready => rx_axis_mac_tready,
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    rx_axis_mac_tuser  => rx_axis_mac_tuser,
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    fifo_status        => rx_fifo_status,
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    fifo_overflow      => rx_fifo_overflow
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  );
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end RTL;

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