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CONFIG PART = xc6vlx240tff1156-1;
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########## ML605 Board ##########
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NET clk_in_p LOC = J9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
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NET clk_in_n LOC = H9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
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Net reset LOC = H10 |IOSTANDARD = LVCMOS15 |TIG;
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# downgrade the Place:1153 error in the mapper
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NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;
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#### Module LEDs_8Bit constraints
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NET "display[0]" LOC = AC22;
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NET "display[1]" LOC = AC24;
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NET "display[2]" LOC = AE22;
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NET "display[3]" LOC = AE23;
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NET "display[4]" LOC = AB23;
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NET "display[5]" LOC = AG23;
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NET "display[6]" LOC = AE24;
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NET "display[7]" LOC = AD24;
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NET PBTX_LED LOC = AD21;
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NET UDP_RX LOC = AH27;
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NET DO_SECOND_TX_LED LOC = AH28;
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NET TX_RSLT_0 LOC = AE21;
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NET TX_RSLT_1 LOC = AP24;
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#### Module Push_Buttons_4Bit constraints
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NET PBTX LOC = H17;
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NET PB_DO_SECOND_TX LOC = A18;
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NET reset_leds LOC = G26;
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#### Module DIP_Switches_4Bit constraints
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Net phy_resetn LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG;
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Net gmii_rxd<7> LOC = AC13 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<6> LOC = AC12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<5> LOC = AD11 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<4> LOC = AM12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<3> LOC = AN12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<2> LOC = AE14 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<1> LOC = AF14 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<0> LOC = AN13 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<7> LOC = AF11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<6> LOC = AE11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<5> LOC = AM10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<4> LOC = AL10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<3> LOC = AG11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<2> LOC = AG10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<1> LOC = AL11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<0> LOC = AM11 |IOSTANDARD = LVCMOS25;
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Net gmii_col LOC = AK13 |IOSTANDARD = LVCMOS25;
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Net gmii_crs LOC = AL13 |IOSTANDARD = LVCMOS25;
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Net mii_tx_clk LOC = AD12 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_en LOC = AJ10 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_er LOC = AH10 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_clk LOC = AH12 |IOSTANDARD = LVCMOS25;
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Net gmii_rx_dv LOC = AM13 |IOSTANDARD = LVCMOS25;
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Net gmii_rx_er LOC = AG12 |IOSTANDARD = LVCMOS25;
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# P20 - GCLK7
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Net gmii_rx_clk LOC = AP11 |IOSTANDARD = LVCMOS25;
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NET "clk_in_p" TNM_NET = "clk_in_p";
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TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;
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# Ethernet GTX_CLK high quality 125 MHz reference clock
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NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk";
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TIMEGRP "v6_emac_v2_1_clk_ref_gtx" = "ref_gtx_clk";
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TIMESPEC "TS_v6_emac_v2_1_clk_ref_gtx" = PERIOD "v6_emac_v2_1_clk_ref_gtx" 8 ns HIGH 50 %;
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# Multiplexed 1 Gbps, 10/100 Mbps output inherits constraint from GTX_CLK
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NET "*tx_mac_aclk*" TNM_NET = "clk_tx_mac";
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TIMEGRP "v6_emac_v2_1_clk_ref_mux" = "clk_tx_mac";
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TIMESPEC "TS_v6_emac_v2_1_clk_ref_mux" = PERIOD "v6_emac_v2_1_clk_ref_mux" TS_v6_emac_v2_1_clk_ref_gtx HIGH 50%;
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# Ethernet GMII PHY-side receive clock
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NET "gmii_rx_clk" TNM_NET = "phy_clk_rx";
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TIMEGRP "v6_emac_v2_1_clk_phy_rx" = "phy_clk_rx";
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TIMESPEC "TS_v6_emac_v2_1_clk_phy_rx" = PERIOD "v6_emac_v2_1_clk_phy_rx" 7.5 ns HIGH 50 %;
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# define TIGs between unrelated clock domains
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TIMESPEC "TS_clock_path_gtx2ref" = FROM "clock_generator_clkout0" TO "clock_generator_clkout2" TIG;
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PIN "*bufgmux_speed_clk.I1" TIG;
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PIN "*bufgmux_speed_clk.CE0" TIG;
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#
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####
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#######
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##########
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#############
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#################
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#FIFO BLOCK CONSTRAINTS
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# Group design elements around the Ethernet MAC to assist with timing
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# closure in this example design. These values may be modified or
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# removed to best suit your design.
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#INST "*user_side_FIFO?tx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y34";
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#INST "*user_side_FIFO?rx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y35";
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#INST "*user_side_FIFO?tx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y36";
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#INST "*user_side_FIFO?rx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X6Y37";
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###############################################################################
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# AXI FIFO CONSTRAINTS
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# The following constraints are necessary for proper operation of the AXI
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# FIFO. If you choose to not use the FIFO Block level of wrapper hierarchy,
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# these constraints should be removed.
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###############################################################################
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# AXI FIFO transmit-side constraints
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# -----------------------------------------------------------------------------
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# Group the clock crossing signals into timing groups
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INST "*user_side_FIFO?tx_fifo_i?rd_tran_frame_tog" TNM = "tx_fifo_rd_to_wr";
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INST "*user_side_FIFO?tx_fifo_i?rd_retran_frame_tog" TNM = "tx_fifo_rd_to_wr";
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INST "*user_side_FIFO?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr";
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INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*" TNM = "tx_fifo_rd_to_wr";
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INST "*user_side_FIFO?tx_fifo_i?rd_txfer_tog" TNM = "tx_fifo_rd_to_wr";
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INST "*user_side_FIFO?tx_fifo_i?wr_frame_in_fifo" TNM = "tx_fifo_wr_to_rd";
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TIMESPEC "TS_tx_fifo_rd_to_wr" = FROM "tx_fifo_rd_to_wr" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;
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TIMESPEC "TS_tx_fifo_wr_to_rd" = FROM "tx_fifo_wr_to_rd" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;
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# Reduce clock period to allow for metastability settling time
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INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable";
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INST "*user_side_FIFO?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable";
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TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" 5 ns DATAPATHONLY;
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# Transmit-side AXI FIFO address bus timing
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INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*" TNM = "tx_addr_rd";
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INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*" TNM = "tx_addr_wr";
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TIMESPEC "TS_tx_fifo_addr" = FROM "tx_addr_rd" TO "tx_addr_wr" 10 ns;
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# AXI FIFO receive-side constraints
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# -----------------------------------------------------------------------------
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# Group the clock crossing signals into timing groups
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INST "*user_side_FIFO?rx_fifo_i?wr_store_frame_tog" TNM = "rx_fifo_wr_to_rd";
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INST "*user_side_FIFO?rx_fifo_i?rd_addr*" TNM = "rx_fifo_rd_to_wr";
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TIMESPEC "TS_rx_fifo_wr_to_rd" = FROM "rx_fifo_wr_to_rd" TO "v6_emac_v2_1_clk_ref_mux" 8 ns DATAPATHONLY;
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TIMESPEC "TS_rx_fifo_rd_to_wr" = FROM "rx_fifo_rd_to_wr" TO "v6_emac_v2_1_clk_phy_rx" 8 ns DATAPATHONLY;
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#
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####
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#######
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##########
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#############
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#################
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#BLOCK CONSTRAINTS
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# Locate the Tri-Mode Ethernet MAC instance
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INST "*v6_emac" LOC = "TEMAC_X0Y0";
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###############################################################################
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# PHYSICAL INTERFACE CONSTRAINTS
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# The following constraints are necessary for proper operation, and are tuned
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# for this example design. They should be modified to suit your design.
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###############################################################################
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# GMII physical interface constraints
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# -----------------------------------------------------------------------------
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# Set the IDELAY values on the PHY inputs, tuned for this example design.
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# These values should be modified to suit your design.
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INST "*v6emac_block*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 22;
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INST "*v6emac_block*gmii_interface*delay_gmii_rx_er" IDELAY_VALUE = 22;
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INST "*v6emac_block*gmii_interface*delay_gmii_rxd" IDELAY_VALUE = 22;
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# Group all IDELAY-related blocks to use a single IDELAYCTRL
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INST "*dlyctrl" IODELAY_GROUP = gmii_idelay;
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INST "*v6emac_block*gmii_interface*delay_gmii_rx_dv" IODELAY_GROUP = gmii_idelay;
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INST "*v6emac_block*gmii_interface*delay_gmii_rx_er" IODELAY_GROUP = gmii_idelay;
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INST "*v6emac_block*gmii_interface*delay_gmii_rxd" IODELAY_GROUP = gmii_idelay;
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# The following constraints work in conjunction with IDELAY_VALUE settings to
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# check that the GMII receive bus remains in alignment with the rising edge of
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# GMII_RX_CLK, to within 2 ns setup time and 750 ps hold time.
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# In addition to adjusting IDELAY_VALUE settings for your system's timing
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# characteristics, you may wish to refine these constraints to match the GMII specification;
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# see Answer Record 33195 on xilinx.com for details.
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INST "gmii_rxd" TNM = "gmii_rx";
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INST "gmii_rx_dv" TNM = "gmii_rx";
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INST "gmii_rx_er" TNM = "gmii_rx";
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TIMEGRP "gmii_rx" OFFSET = IN 2 ns VALID 2.75 ns BEFORE "gmii_rx_clk" RISING;
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# Constrain the GMII physical interface flip-flops to IOBs
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INST "*v6emac_block*gmii_interface*rxd_to_mac*" IOB = force;
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INST "*v6emac_block*gmii_interface*rx_dv_to_mac" IOB = force;
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INST "*v6emac_block*gmii_interface*rx_er_to_mac" IOB = force;
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INST "*v6emac_block*gmii_interface*gmii_txd_?" IOB = force;
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INST "*v6emac_block*gmii_interface*gmii_tx_en" IOB = force;
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INST "*v6emac_block*gmii_interface*gmii_tx_er" IOB = force;
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# Location constraints are chosen for this example design.
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# These values should be modified to suit your design.
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# * Note that regional clocking imposes certain requirements
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# on the location of the physical interface pins and the TEMAC instance.
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# Please refer to the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC
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# User Guide for additional details. *
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# Locate the GMII physical interface pins
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INST "gmii_txd" LOC = "BANK36";
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INST "gmii_tx_en" LOC = "BANK36";
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INST "gmii_tx_er" LOC = "BANK36";
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INST "gmii_tx_clk" LOC = "BANK36";
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INST "gmii_rxd" LOC = "BANK36";
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INST "gmii_rx_dv" LOC = "BANK36";
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INST "gmii_rx_er" LOC = "BANK36";
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INST "gmii_rx_clk" LOC = "BANK36";
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# Locate the 125 MHz reference clock buffer
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#INST "*BUFGMUX_SPEED_CLK" LOC = "BUFGCTRL_X0Y24";
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