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[/] [udp_ip_stack/] [trunk/] [contrib/] [from_tim/] [udp_ip_stack/] [tags/] [v1.0/] [bench/] [vhdl/] [UDP_complete_nomac_tb.vhd] - Blame information for rev 35

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1 35 pjf
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   09:57:01 06/13/2011
6
-- Design Name:   
7
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
8
-- Project Name:  udp1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Additional Comments:
20
--
21
-- Notes: 
22
-- This testbench has been automatically generated using types std_logic and
23
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
-- that these types always be used for the top-level I/O of a design in order
25
-- to guarantee that the testbench will bind correctly to the post-implementation 
26
-- simulation model.
27
--------------------------------------------------------------------------------
28
library IEEE;
29
use IEEE.STD_LOGIC_1164.ALL;
30
use IEEE.NUMERIC_STD.ALL;
31
use work.axi.all;
32
use work.ipv4_types.all;
33
use work.arp_types.all;
34
 
35
ENTITY UDP_complete_nomac_tb IS
36
END UDP_complete_nomac_tb;
37
 
38
ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
39
 
40
    -- Component Declaration for the Unit Under Test (UUT)
41
 
42
    COMPONENT UDP_Complete_nomac
43
    PORT(
44
                        -- UDP TX signals
45
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
46
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
47
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
48
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
49
                        -- UDP RX signals
50
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
51
                        udp_rxo                                 : out udp_rx_type;
52
                        -- IP RX signals
53
                        ip_rx_hdr                               : out ipv4_rx_header_type;
54
                        -- system signals
55
                        rx_clk                                  : in  STD_LOGIC;
56
                        tx_clk                                  : in  STD_LOGIC;
57
                        reset                                   : in  STD_LOGIC;
58
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
59
                        our_mac_address                 : in std_logic_vector (47 downto 0);
60
                        -- status signals
61
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
62
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
63
                        -- MAC Transmitter
64
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
65
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
66
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
67
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
68
                        -- MAC Receiver
69
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
70
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
71
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
72
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
73
                        );
74
    END COMPONENT;
75
 
76
 
77
 
78
        type state_type is (IDLE, DATA_OUT);
79
        type count_mode_type is (RST, INCR, HOLD);
80
        type set_clr_type is (SET, CLR, HOLD);
81
 
82
 
83
   --Inputs
84
   signal udp_tx_start_int : std_logic := '0';
85
   signal udp_tx_int : udp_tx_type;
86
   signal clk_int : std_logic := '0';
87
   signal reset : std_logic := '0';
88
   signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
89
   signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
90
   signal mac_tx_tready : std_logic := '0';
91
   signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
92
   signal mac_rx_tvalid : std_logic := '0';
93
   signal mac_rx_tlast : std_logic := '0';
94
 
95
        --Outputs
96
   signal udp_rx_start_int : std_logic;
97
   signal udp_rx_int : udp_rx_type;
98
   signal ip_rx_hdr : ipv4_rx_header_type;
99
        signal udp_tx_result    : std_logic_vector (1 downto 0);
100
        signal udp_tx_data_out_ready_int: std_logic;
101
 
102
   signal arp_pkt_count : std_logic_vector(7 downto 0);
103
   signal ip_pkt_count : std_logic_vector(7 downto 0);
104
   signal mac_tx_tdata : std_logic_vector(7 downto 0);
105
   signal mac_tx_tvalid : std_logic;
106
   signal mac_tx_tlast : std_logic;
107
   signal mac_rx_tready : std_logic;
108
 
109
        signal pbtx_led : std_logic;
110
        signal pbtx : std_logic := '0';
111
 
112
        -- state signals
113
        signal state                    : state_type;
114
        signal count                    : unsigned (7 downto 0);
115
        signal tx_hdr                   : udp_tx_header_type;
116
        signal tx_start_reg     : std_logic;
117
        signal tx_started_reg : std_logic;
118
        signal tx_fin_reg               : std_logic;
119
 
120
 
121
        -- control signals
122
        signal next_state               : state_type;
123
        signal set_state                : std_logic;
124
        signal set_count                : count_mode_type;
125
        signal set_hdr                  : std_logic;
126
        signal set_tx_start     : set_clr_type;
127
        signal tx_data                  : std_logic_vector (7 downto 0);
128
        signal set_last         : std_logic;
129
        signal set_tx_started : set_clr_type;
130
        signal set_tx_fin       : set_clr_type;
131
 
132
 
133
 
134
   -- Clock period definitions
135
   constant clk_period : time := 8 ns;
136
 
137
BEGIN
138
 
139
        -- Instantiate the Unit Under Test (UUT)
140
   uut: UDP_Complete_nomac PORT MAP (
141
          udp_tx_start => udp_tx_start_int,
142
          udp_txi => udp_tx_int,
143
          udp_tx_result => udp_tx_result,
144
          udp_tx_data_out_ready => udp_tx_data_out_ready_int,
145
          udp_rx_start => udp_rx_start_int,
146
          udp_rxo => udp_rx_int,
147
          ip_rx_hdr => ip_rx_hdr,
148
          rx_clk => clk_int,
149
                         tx_clk => clk_int,
150
          reset => reset,
151
          our_ip_address => our_ip_address,
152
          our_mac_address => our_mac_address,
153
          arp_pkt_count => arp_pkt_count,
154
          ip_pkt_count => ip_pkt_count,
155
          mac_tx_tdata => mac_tx_tdata,
156
          mac_tx_tvalid => mac_tx_tvalid,
157
          mac_tx_tready => mac_tx_tready,
158
          mac_tx_tlast => mac_tx_tlast,
159
          mac_rx_tdata => mac_rx_tdata,
160
          mac_rx_tvalid => mac_rx_tvalid,
161
          mac_rx_tready => mac_rx_tready,
162
          mac_rx_tlast => mac_rx_tlast
163
        );
164
 
165
   -- Clock process definitions
166
   clk_process :process
167
   begin
168
                clk_int <= '0';
169
                wait for clk_period/2;
170
                clk_int <= '1';
171
                wait for clk_period/2;
172
   end process;
173
 
174
 
175
   -- Stimulus process
176
   stim_proc: process
177
   begin
178
      -- hold reset state for 100 ns.
179
      wait for 100 ns;
180
 
181
                our_ip_address <= x"c0a80509";          -- 192.168.5.9
182
                our_mac_address <= x"002320212223";
183
      mac_tx_tready <= '0';
184
 
185
                reset <= '1';
186
      wait for clk_period*10;
187
                reset <= '0';
188
      wait for clk_period*5;
189
 
190
                -- check reset conditions
191
                assert udp_tx_result = UDPTX_RESULT_NONE                report "udp_tx_result not initialised correctly on reset";
192
                assert udp_tx_data_out_ready_int = '0'           report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
193
                assert mac_tx_tvalid = '0'                                               report "mac_tx_tvalid not initialised correctly on reset";
194
                assert mac_tx_tlast = '0'                                                        report "mac_tx_tlast not initialised correctly on reset";
195
                assert arp_pkt_count = x"00"                                            report "arp_pkt_count not initialised correctly on reset";
196
                assert ip_pkt_count = x"00"                                             report "ip_pkt_count not initialised correctly on reset";
197
                assert udp_rx_start_int = '0'                                                    report "udp_rx_start not initialised correctly on reset";
198
                assert udp_rx_int.hdr.is_valid = '0'                             report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
199
                assert udp_rx_int.hdr.data_length = x"0000"             report "udp_rx_int.hdr.data_length not initialised correctly on reset";
200
                assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
201
                assert udp_rx_int.hdr.src_port = x"0000"                        report "udp_rx_int.hdr.src_port not initialised correctly on reset";
202
                assert udp_rx_int.hdr.dst_port = x"0000"                        report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
203
                assert udp_rx_int.data.data_in = x"00"                          report "udp_rx_start.data.data_in not initialised correctly on reset";
204
                assert udp_rx_int.data.data_in_valid = '0'               report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
205
                assert udp_rx_int.data.data_in_last = '0'                        report "udp_rx_start.data.data_in_last not initialised correctly on reset";
206
                assert ip_rx_hdr.is_valid = '0'                                  report "ip_rx_hdr.is_valid not initialised correctly on reset";
207
                assert ip_rx_hdr.protocol = x"00"                               report "ip_rx_hdr.protocol not initialised correctly on reset";
208
                assert ip_rx_hdr.data_length = x"0000"                  report "ip_rx_hdr.data_length not initialised correctly on reset";
209
                assert ip_rx_hdr.src_ip_addr = x"00000000"      report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
210
                assert ip_rx_hdr.num_frame_errors = x"00"               report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
211
 
212
 
213
      -- insert stimulus here 
214
 
215
                ------------
216
                -- TEST 1 -- send ARP request
217
                ------------
218
 
219
                report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
220
 
221
      mac_tx_tready <= '1';
222
 
223
                mac_rx_tvalid <= '1';
224
                -- dst MAC (bc)
225
                mac_rx_tdata <= x"ff"; wait for clk_period;
226
                mac_rx_tdata <= x"ff"; wait for clk_period;
227
                mac_rx_tdata <= x"ff"; wait for clk_period;
228
                mac_rx_tdata <= x"ff"; wait for clk_period;
229
                mac_rx_tdata <= x"ff"; wait for clk_period;
230
                mac_rx_tdata <= x"ff"; wait for clk_period;
231
                -- src MAC
232
                mac_rx_tdata <= x"00"; wait for clk_period;
233
                mac_rx_tdata <= x"23"; wait for clk_period;
234
                mac_rx_tdata <= x"18"; wait for clk_period;
235
                mac_rx_tdata <= x"29"; wait for clk_period;
236
                mac_rx_tdata <= x"26"; wait for clk_period;
237
                mac_rx_tdata <= x"7c"; wait for clk_period;
238
                -- type
239
                mac_rx_tdata <= x"08"; wait for clk_period;
240
                mac_rx_tdata <= x"06"; wait for clk_period;
241
                -- HW type
242
                mac_rx_tdata <= x"00"; wait for clk_period;
243
                mac_rx_tdata <= x"01"; wait for clk_period;
244
                -- Protocol type
245
                mac_rx_tdata <= x"08"; wait for clk_period;
246
                mac_rx_tdata <= x"00"; wait for clk_period;
247
                -- HW size
248
                mac_rx_tdata <= x"06"; wait for clk_period;
249
                -- protocol size
250
                mac_rx_tdata <= x"04"; wait for clk_period;
251
                -- Opcode
252
                mac_rx_tdata <= x"00"; wait for clk_period;
253
                mac_rx_tdata <= x"01"; wait for clk_period;
254
                -- Sender MAC
255
                mac_rx_tdata <= x"00"; wait for clk_period;
256
                mac_rx_tdata <= x"23"; wait for clk_period;
257
                mac_rx_tdata <= x"18"; wait for clk_period;
258
                mac_rx_tdata <= x"29"; wait for clk_period;
259
                mac_rx_tdata <= x"26"; wait for clk_period;
260
                mac_rx_tdata <= x"7c"; wait for clk_period;
261
                -- Sender IP
262
                mac_rx_tdata <= x"c0"; wait for clk_period;
263
                mac_rx_tdata <= x"a8"; wait for clk_period;
264
                mac_rx_tdata <= x"05"; wait for clk_period;
265
                mac_rx_tdata <= x"01"; wait for clk_period;
266
                -- Target MAC
267
                mac_rx_tdata <= x"00"; wait for clk_period;
268
                mac_rx_tdata <= x"00"; wait for clk_period;
269
                mac_rx_tdata <= x"00"; wait for clk_period;
270
                mac_rx_tdata <= x"00"; wait for clk_period;
271
                mac_rx_tdata <= x"00"; wait for clk_period;
272
                mac_rx_tdata <= x"00"; wait for clk_period;
273
                -- Target IP
274
                mac_rx_tdata <= x"c0"; wait for clk_period;
275
                mac_rx_tdata <= x"a8"; wait for clk_period;
276
                mac_rx_tdata <= x"05"; wait for clk_period;
277
                mac_rx_tdata <= x"09"; wait for clk_period;
278
                mac_rx_tdata <= x"00"; wait for clk_period;
279
                mac_rx_tdata <= x"00"; wait for clk_period;
280
                mac_rx_tdata <= x"00"; wait for clk_period;
281
                mac_rx_tlast <= '1';
282
                mac_rx_tdata <= x"00"; wait for clk_period;
283
                mac_rx_tlast <= '0';
284
                mac_rx_tvalid <= '0';
285
 
286
                -- check we got the ARP pkt
287
                assert arp_pkt_count = x"01"                                            report "T1: arp_pkt_count wrong value";
288
                assert ip_pkt_count = x"00"                                             report "T1: ip_pkt_count wrong value";
289
                assert udp_tx_result = UDPTX_RESULT_NONE                report "T1: udp_tx_result wrong value";
290
                assert udp_tx_data_out_ready_int = '0'           report "T1: ip_udp_txitx.data.data_out_ready wrong value";
291
                assert udp_rx_start_int = '0'                                                    report "T1: udp_rx_start wrong value";
292
                assert udp_rx_int.hdr.is_valid = '0'                             report "T1: udp_rx_int.hdr.is_valid wrong value";
293
                assert ip_rx_hdr.is_valid = '0'                                  report "T1: ip_rx_hdr.is_valid wrong value";
294
 
295
                -- check we tx a response
296
 
297
                wait for clk_period*25;
298
                assert mac_tx_tvalid = '1'                                                      report "T1: not transmitting a response";
299
                wait for clk_period*25;
300
                assert mac_tx_tvalid = '0'                                                       report "T1: tx held on for too long";
301
 
302
                ------------
303
                -- TEST 2 -- send UDP pkt (same as sample from Java program
304
                ------------
305
 
306
                report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
307
 
308
                mac_rx_tvalid <= '1';
309
                -- dst MAC (bc)
310
                mac_rx_tdata <= x"00"; wait for clk_period;
311
                mac_rx_tdata <= x"23"; wait for clk_period;
312
                mac_rx_tdata <= x"20"; wait for clk_period;
313
                mac_rx_tdata <= x"21"; wait for clk_period;
314
                mac_rx_tdata <= x"22"; wait for clk_period;
315
                mac_rx_tdata <= x"23"; wait for clk_period;
316
                -- src MAC
317
                mac_rx_tdata <= x"00"; wait for clk_period;
318
                mac_rx_tdata <= x"23"; wait for clk_period;
319
                mac_rx_tdata <= x"18"; wait for clk_period;
320
                mac_rx_tdata <= x"29"; wait for clk_period;
321
                mac_rx_tdata <= x"26"; wait for clk_period;
322
                mac_rx_tdata <= x"7c"; wait for clk_period;
323
                -- type
324
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
325
                mac_rx_tdata <= x"00"; wait for clk_period;
326
                -- ver & HL / service type
327
                mac_rx_tdata <= x"45"; wait for clk_period;
328
                mac_rx_tdata <= x"00"; wait for clk_period;
329
                -- total len
330
                mac_rx_tdata <= x"00"; wait for clk_period;
331
                mac_rx_tdata <= x"21"; wait for clk_period;
332
                -- ID
333
                mac_rx_tdata <= x"00"; wait for clk_period;
334
                mac_rx_tdata <= x"7a"; wait for clk_period;
335
                -- flags & frag
336
                mac_rx_tdata <= x"00"; wait for clk_period;
337
                mac_rx_tdata <= x"00"; wait for clk_period;
338
                -- TTL
339
                mac_rx_tdata <= x"80"; wait for clk_period;
340
                -- Protocol
341
                mac_rx_tdata <= x"11"; wait for clk_period;
342
                -- Header CKS
343
                mac_rx_tdata <= x"00"; wait for clk_period;
344
                mac_rx_tdata <= x"00"; wait for clk_period;
345
                -- SRC IP
346
                mac_rx_tdata <= x"c0"; wait for clk_period;
347
                mac_rx_tdata <= x"a8"; wait for clk_period;
348
                mac_rx_tdata <= x"05"; wait for clk_period;
349
                mac_rx_tdata <= x"01"; wait for clk_period;
350
                -- DST IP
351
                mac_rx_tdata <= x"c0"; wait for clk_period;
352
                mac_rx_tdata <= x"a8"; wait for clk_period;
353
                mac_rx_tdata <= x"05"; wait for clk_period;
354
                mac_rx_tdata <= x"09"; wait for clk_period;
355
                -- SRC port
356
                mac_rx_tdata <= x"f4"; wait for clk_period;
357
                mac_rx_tdata <= x"9a"; wait for clk_period;
358
                -- DST port
359
                mac_rx_tdata <= x"26"; wait for clk_period;
360
                mac_rx_tdata <= x"94"; wait for clk_period;
361
                -- length
362
                mac_rx_tdata <= x"00"; wait for clk_period;
363
                mac_rx_tdata <= x"0d"; wait for clk_period;
364
                -- cks
365
                mac_rx_tdata <= x"8b"; wait for clk_period;
366
                mac_rx_tdata <= x"79"; wait for clk_period;
367
                -- user data
368
                mac_rx_tdata <= x"68"; wait for clk_period;
369
 
370
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
371
                assert udp_rx_int.hdr.is_valid = '1'                            report "T2: udp_rx_int.hdr.is_valid not set";
372
                assert udp_rx_int.hdr.data_length = x"0005"             report "T2: udp_rx_int.hdr.data_length not set correctly";
373
                assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
374
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T2: udp_rx_int.hdr.src_port not set correctly";
375
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T2: udp_rx_int.hdr.dst_port not set correctly";
376
 
377
                assert udp_rx_start_int = '1'                                                   report "T2: udp_rx_start not set";
378
                assert udp_rx_int.data.data_in_valid = '1'              report "T2: udp_rx_int.data.data_in_valid not set";
379
 
380
                assert ip_rx_hdr.is_valid = '1'                                 report "T2: ip_rx_hdr.is_valid not set";
381
                assert ip_rx_hdr.protocol = x"11"                               report "T2: ip_rx_hdr.protocol not set correctly";
382
                assert ip_rx_hdr.src_ip_addr = x"c0a80501"      report "T2: ip_rx.hdr.src_ip_addr not set correctly";
383
                assert ip_rx_hdr.num_frame_errors = x"00"       report "T2: ip_rx.hdr.num_frame_errors not set correctly";
384
                assert ip_rx_hdr.last_error_code = x"0"          report "T2: ip_rx.hdr.last_error_code not set correctly";
385
 
386
                -- put the rest of the user data
387
                mac_rx_tdata <= x"65"; wait for clk_period;
388
                mac_rx_tdata <= x"6c"; wait for clk_period;
389
                mac_rx_tdata <= x"6c"; wait for clk_period;
390
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
391
 
392
                assert udp_rx_int.data.data_in_last = '1'                       report "T2: udp_rx_int.data.data_in_last not set";
393
 
394
                mac_rx_tdata <= x"00";
395
                mac_rx_tlast <= '0';
396
                mac_rx_tvalid <= '0';
397
                wait for clk_period;
398
 
399
                assert udp_rx_int.data.data_in_valid = '0'               report "T2: udp_rx_int.data.data_in_valid not cleared";
400
                assert udp_rx_int.data.data_in_last = '0'                        report "T2: udp_rx_int.data.data_in_last not cleared";
401
                assert udp_rx_start_int = '0'                                                    report "T2: udp_rx_start not cleared";
402
                assert ip_rx_hdr.num_frame_errors = x"00"               report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
403
                assert ip_rx_hdr.last_error_code = x"0"          report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
404
                assert ip_pkt_count = x"01"                                             report "T2: ip pkt cnt incorrect";
405
 
406
                wait for clk_period*20;
407
 
408
                ------------
409
                -- TEST 3 -- send UDP pkt again (same as sample from Java program
410
                ------------
411
 
412
                report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
413
 
414
                mac_rx_tvalid <= '1';
415
                -- dst MAC (bc)
416
                mac_rx_tdata <= x"00"; wait for clk_period;
417
                mac_rx_tdata <= x"23"; wait for clk_period;
418
                mac_rx_tdata <= x"20"; wait for clk_period;
419
                mac_rx_tdata <= x"21"; wait for clk_period;
420
                mac_rx_tdata <= x"22"; wait for clk_period;
421
                mac_rx_tdata <= x"23"; wait for clk_period;
422
                -- src MAC
423
                mac_rx_tdata <= x"00"; wait for clk_period;
424
                mac_rx_tdata <= x"23"; wait for clk_period;
425
                mac_rx_tdata <= x"18"; wait for clk_period;
426
                mac_rx_tdata <= x"29"; wait for clk_period;
427
                mac_rx_tdata <= x"26"; wait for clk_period;
428
                mac_rx_tdata <= x"7c"; wait for clk_period;
429
                -- type
430
                mac_rx_tdata <= x"08"; wait for clk_period;             -- IP pkt
431
                mac_rx_tdata <= x"00"; wait for clk_period;
432
                -- ver & HL / service type
433
                mac_rx_tdata <= x"45"; wait for clk_period;
434
                mac_rx_tdata <= x"00"; wait for clk_period;
435
                -- total len
436
                mac_rx_tdata <= x"00"; wait for clk_period;
437
                mac_rx_tdata <= x"21"; wait for clk_period;
438
                -- ID
439
                mac_rx_tdata <= x"00"; wait for clk_period;
440
                mac_rx_tdata <= x"7a"; wait for clk_period;
441
                -- flags & frag
442
                mac_rx_tdata <= x"00"; wait for clk_period;
443
                mac_rx_tdata <= x"00"; wait for clk_period;
444
                -- TTL
445
                mac_rx_tdata <= x"80"; wait for clk_period;
446
                -- Protocol
447
                mac_rx_tdata <= x"11"; wait for clk_period;
448
                -- Header CKS
449
                mac_rx_tdata <= x"00"; wait for clk_period;
450
                mac_rx_tdata <= x"00"; wait for clk_period;
451
                -- SRC IP
452
                mac_rx_tdata <= x"c0"; wait for clk_period;
453
                mac_rx_tdata <= x"a8"; wait for clk_period;
454
                mac_rx_tdata <= x"05"; wait for clk_period;
455
                mac_rx_tdata <= x"01"; wait for clk_period;
456
                -- DST IP
457
                mac_rx_tdata <= x"c0"; wait for clk_period;
458
                mac_rx_tdata <= x"a8"; wait for clk_period;
459
                mac_rx_tdata <= x"05"; wait for clk_period;
460
                mac_rx_tdata <= x"09"; wait for clk_period;
461
                -- SRC port
462
                mac_rx_tdata <= x"f4"; wait for clk_period;
463
                mac_rx_tdata <= x"9a"; wait for clk_period;
464
                -- DST port
465
                mac_rx_tdata <= x"26"; wait for clk_period;
466
                mac_rx_tdata <= x"94"; wait for clk_period;
467
                -- length
468
                mac_rx_tdata <= x"00"; wait for clk_period;
469
                mac_rx_tdata <= x"0d"; wait for clk_period;
470
                -- cks
471
                mac_rx_tdata <= x"8b"; wait for clk_period;
472
                mac_rx_tdata <= x"79"; wait for clk_period;
473
                -- user data
474
                mac_rx_tdata <= x"68"; wait for clk_period;
475
 
476
                -- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
477
                assert udp_rx_int.hdr.is_valid = '1'                            report "T3: udp_rx_int.hdr.is_valid not set";
478
                assert udp_rx_int.hdr.data_length = x"0005"             report "T3: udp_rx_int.hdr.data_length not set correctly";
479
                assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
480
                assert udp_rx_int.hdr.src_port = x"f49a"                        report "T3: udp_rx_int.hdr.src_port not set correctly";
481
                assert udp_rx_int.hdr.dst_port = x"2694"                        report "T3: udp_rx_int.hdr.dst_port not set correctly";
482
 
483
                assert udp_rx_start_int = '1'                                                   report "T3: udp_rx_start not set";
484
                assert udp_rx_int.data.data_in_valid = '1'              report "T3: udp_rx_int.data.data_in_valid not set";
485
 
486
                assert ip_rx_hdr.is_valid = '1'                                 report "T3: ip_rx_hdr.is_valid not set";
487
                assert ip_rx_hdr.protocol = x"11"                               report "T3: ip_rx_hdr.protocol not set correctly";
488
                assert ip_rx_hdr.src_ip_addr = x"c0a80501"      report "T3: ip_rx.hdr.src_ip_addr not set correctly";
489
                assert ip_rx_hdr.num_frame_errors = x"00"       report "T3: ip_rx.hdr.num_frame_errors not set correctly";
490
                assert ip_rx_hdr.last_error_code = x"0"          report "T3: ip_rx.hdr.last_error_code not set correctly";
491
 
492
                -- put the rest of the user data
493
                mac_rx_tdata <= x"65"; wait for clk_period;
494
                mac_rx_tdata <= x"6c"; wait for clk_period;
495
                mac_rx_tdata <= x"6c"; wait for clk_period;
496
                mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
497
 
498
                assert udp_rx_int.data.data_in_last = '1'                       report "T3: udp_rx_int.data.data_in_last not set";
499
 
500
                mac_rx_tdata <= x"00";
501
                mac_rx_tlast <= '0';
502
                mac_rx_tvalid <= '0';
503
                wait for clk_period;
504
 
505
                assert udp_rx_int.data.data_in_valid = '0'               report "T3: udp_rx_int.data.data_in_valid not cleared";
506
                assert udp_rx_int.data.data_in_last = '0'                        report "T3: udp_rx_int.data.data_in_last not cleared";
507
                assert udp_rx_start_int = '0'                                                    report "T3: udp_rx_start not cleared";
508
                assert ip_rx_hdr.num_frame_errors = x"00"               report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
509
                assert ip_rx_hdr.last_error_code = x"0"          report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
510
                assert ip_pkt_count = x"02"                                             report "T3: ip pkt cnt incorrect";
511
 
512
                report "--- end of tests ---";
513
      wait;
514
   end process;
515
 
516
        -- AUTO TX process - on receipt of any UDP pkt, send a response
517
 
518
                -- TX response process - COMB
519
   tx_proc_combinatorial: process(
520
                -- inputs
521
                udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX,
522
                -- state
523
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
524
                -- controls
525
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
526
                set_tx_started, set_tx_fin
527
                )
528
   begin
529
                -- set output_followers
530
                udp_tx_int.hdr <= tx_hdr;
531
                udp_tx_int.data.data_out_last <= set_last;
532
                udp_tx_start_int <= tx_start_reg;
533
 
534
                -- set control signal defaults
535
                next_state <= IDLE;
536
                set_state <= '0';
537
                set_count <= HOLD;
538
                set_hdr <= '0';
539
                set_tx_start <= HOLD;
540
                set_last <= '0';
541
                set_tx_started <= HOLD;
542
                set_tx_fin <= HOLD;
543
 
544
                -- FSM
545
                case state is
546
 
547
                        when IDLE =>
548
                                udp_tx_int.data.data_out <= (others => '0');
549
                                udp_tx_int.data.data_out_valid <= '0';
550
                                if udp_rx_start_int = '1' or PBTX = '1' then
551
                                        set_tx_started <= SET;
552
                                        set_hdr <= '1';
553
                                        set_tx_start <= SET;
554
                                        set_tx_fin <= CLR;
555
                                        set_count <= RST;
556
                                        next_state <= DATA_OUT;
557
                                        set_state <= '1';
558
                                end if;
559
 
560
                        when DATA_OUT =>
561
                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
562
                                udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
563
                                if udp_tx_data_out_ready_int = '1' then
564
                                        set_tx_start <= CLR;
565
                                        if unsigned(count) = x"03" then
566
                                                set_last <= '1';
567
                                                set_tx_fin <= SET;
568
                                                set_tx_started <= CLR;
569
                                                next_state <= IDLE;
570
                                                set_state <= '1';
571
                                        else
572
                                                set_count <= INCR;
573
                                        end if;
574
                                end if;
575
 
576
                end case;
577
        end process;
578
 
579
 
580
 
581
   -- TX response process - SEQ
582
   tx_proc_sequential: process(clk_int)
583
   begin
584
                if rising_edge(clk_int) then
585
                        if reset = '1' then
586
                                -- reset state variables
587
                                state <= IDLE;
588
                                count <= x"00";
589
                                tx_start_reg <= '0';
590
                                tx_hdr.dst_ip_addr <= (others => '0');
591
                                tx_hdr.dst_port <= (others => '0');
592
                                tx_hdr.src_port <= (others => '0');
593
                                tx_hdr.data_length <= (others => '0');
594
                                tx_hdr.checksum <= (others => '0');
595
                                tx_started_reg <= '0';
596
                                tx_fin_reg <= '0';
597
                                PBTX_LED <= '0';
598
                        else
599
                                PBTX_LED <= PBTX;
600
 
601
                                -- Next rx_state processing
602
                                if set_state = '1' then
603
                                        state <= next_state;
604
                                else
605
                                        state <= state;
606
                                end if;
607
 
608
                                -- count processing
609
                                case set_count is
610
                                        when RST =>             count <= x"00";
611
                                        when INCR =>            count <= count + 1;
612
                                        when HOLD =>            count <= count;
613
                                end case;
614
 
615
                                -- set tx hdr
616
                                if set_hdr = '1' then
617
                                        tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
618
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
619
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
620
                                        tx_hdr.data_length <= x"0004";
621
                                        tx_hdr.checksum <= x"0000";
622
                                else
623
                                        tx_hdr <= tx_hdr;
624
                                end if;
625
 
626
                                -- set tx start signal
627
                                case set_tx_start is
628
                                        when SET  => tx_start_reg <= '1';
629
                                        when CLR  => tx_start_reg <= '0';
630
                                        when HOLD => tx_start_reg <= tx_start_reg;
631
                                end case;
632
 
633
                                -- set tx started signal
634
                                case set_tx_started is
635
                                        when SET  => tx_started_reg <= '1';
636
                                        when CLR  => tx_started_reg <= '0';
637
                                        when HOLD => tx_started_reg <= tx_started_reg;
638
                                end case;
639
 
640
                                -- set tx finished signal
641
                                case set_tx_fin is
642
                                        when SET  => tx_fin_reg <= '1';
643
                                        when CLR  => tx_fin_reg <= '0';
644
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
645
                                end case;
646
 
647
 
648
                        end if;
649
                end if;
650
 
651
        end process;
652
 
653
END;

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