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Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [contrib/] [from_tim/] [udp_ip_stack/] [tags/] [v1.3/] [rtl/] [vhdl/] [ml605/] [UDP_integration_example.vhd] - Blame information for rev 35

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:01:00 06/11/2011 
-- Design Name: 
-- Module Name:    UDP_integration_example - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity UDP_integration_example is
    port (
                -- System signals
                ------------------
      reset                             : in  std_logic;                                        -- asynchronous reset
      clk_in_p                                  : in  std_logic;                                        -- 200MHz clock input from board
      clk_in_n                                  : in  std_logic;
 
                -- System controls
                ------------------
                PBTX                                                                    : in std_logic;
                UDP_RX                                                          : out std_logic;
                UDP_Start                                                       : out std_logic;
                PBTX_LED                                                                : out std_logic;
                TX_Started                                                      : out std_logic;
                TX_Completed                                            : out std_logic;
                TX_RSLT_0                                                       : out std_logic;
                TX_RSLT_1                                                       : out std_logic;
                reset_leds                                                      : in std_logic;
      display                           : out std_logic_vector(7 downto 0);
 
      -- GMII Interface
      -----------------     
      phy_resetn                                : out std_logic;
      gmii_txd                      : out std_logic_vector(7 downto 0);
      gmii_tx_en                    : out std_logic;
      gmii_tx_er                    : out std_logic;
      gmii_tx_clk                   : out std_logic;
      gmii_rxd                      : in  std_logic_vector(7 downto 0);
      gmii_rx_dv                    : in  std_logic;
      gmii_rx_er                    : in  std_logic;
      gmii_rx_clk                   : in  std_logic;
      gmii_col                      : in  std_logic;
      gmii_crs                      : in  std_logic;
      mii_tx_clk                    : in  std_logic
    );
end UDP_integration_example;
 
architecture Behavioral of UDP_integration_example is
 
  ------------------------------------------------------------------------------
  -- Component Declaration for the complete IP layer
  ------------------------------------------------------------------------------
component UDP_Complete
         generic (
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
                        );
    Port (
                        -- UDP TX signals
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
                        -- UDP RX signals
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
                        udp_rxo                                 : out udp_rx_type;
                        -- IP RX signals
                        ip_rx_hdr                               : out ipv4_rx_header_type;
                        -- system signals
                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
                        clk_in_n             : in  std_logic;
                        clk_out                                 : out std_logic;
                        reset                                   : in  STD_LOGIC;
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
                        our_mac_address                 : in std_logic_vector (47 downto 0);
                        control                                 : in udp_control_type;
                        -- status signals
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
                        -- GMII Interface
                        phy_resetn           : out std_logic;
                        gmii_txd             : out std_logic_vector(7 downto 0);
                        gmii_tx_en           : out std_logic;
                        gmii_tx_er           : out std_logic;
                        gmii_tx_clk          : out std_logic;
                        gmii_rxd             : in  std_logic_vector(7 downto 0);
                        gmii_rx_dv           : in  std_logic;
                        gmii_rx_er           : in  std_logic;
                        gmii_rx_clk          : in  std_logic;
                        gmii_col             : in  std_logic;
                        gmii_crs             : in  std_logic;
                        mii_tx_clk           : in  std_logic
                        );
end component;
 
 
        type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
        type count_mode_type is (RST, INCR, HOLD);
        type set_clr_type is (SET, CLR, HOLD);
 
        -- system signals
        signal clk_int                                                  : std_logic;
        signal our_mac                                          : STD_LOGIC_VECTOR (47 downto 0);
        signal our_ip                                                   : STD_LOGIC_VECTOR (31 downto 0);
        signal udp_tx_int                                               : udp_tx_type;
        signal udp_tx_result_int                        : std_logic_vector (1 downto 0);
        signal udp_tx_data_out_ready_int        : std_logic;
        signal udp_rx_int                                               : udp_rx_type;
        signal udp_tx_start_int                         : std_logic;
        signal udp_rx_start_int                         : std_logic;
        signal arp_pkt_count_int                        : STD_LOGIC_VECTOR(7 downto 0);
        signal ip_pkt_count_int                         : STD_LOGIC_VECTOR(7 downto 0);
        signal ip_rx_hdr_int                                    : ipv4_rx_header_type;
 
        -- state signals
        signal state                                                    : state_type;
        signal count                                                    : unsigned (7 downto 0);
        signal tx_hdr                                                   : udp_tx_header_type;
        signal tx_start_reg                                     : std_logic;
        signal tx_started_reg                           : std_logic;
        signal tx_fin_reg                                               : std_logic;
 
        -- control signals
        signal next_state                                               : state_type;
        signal set_state                                                : std_logic;
        signal set_count                                                : count_mode_type;
        signal set_hdr                                                  : std_logic;
        signal set_tx_start                                     : set_clr_type;
        signal set_last                                         : std_logic;
        signal set_tx_started                           : set_clr_type;
        signal set_tx_fin                                               : set_clr_type;
        signal first_byte_rx                                    : STD_LOGIC_VECTOR(7 downto 0);
        signal control_int                                      : udp_control_type;
 
begin
 
        process (
                our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
                udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
                reset, tx_started_reg, tx_fin_reg, tx_start_reg
                )
        begin
                -- set up our local addresses and default controls
                our_ip  <= x"c0a80509";         -- 192.168.5.9
                our_mac         <= x"002320212223";
                control_int.ip_controls.arp_controls.clear_cache <= '0';
 
                -- determine RX good and error LEDs
                if udp_rx_int.hdr.is_valid = '1' then
                        UDP_RX <= '1';
                else
                        UDP_RX <= '0';
                end if;
 
                UDP_Start <= udp_rx_start_int;
                TX_Started <= tx_start_reg; --tx_started_reg;
                TX_Completed <= tx_fin_reg;
                TX_RSLT_0 <= udp_tx_result_int(0);
                TX_RSLT_1 <= udp_tx_result_int(1);
 
                -- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
                display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
 
--              display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
                case state is
                        when IDLE                       => display (3 downto 0) <= "0001";
                        when WAIT_RX_DONE => display (3 downto 0) <= "0010";
                        when DATA_OUT           => display (3 downto 0) <= "0011";
                end case;
 
        end process;
 
        -- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
 
                -- TX response process - COMB
   tx_proc_combinatorial: process(
                -- inputs
                udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
                udp_tx_int.data.data_out_valid, PBTX,
                -- state
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
                -- controls
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
                set_tx_started, set_tx_fin, first_byte_rx
                )
   begin
                -- set output_followers
                udp_tx_int.hdr <= tx_hdr;
                udp_tx_int.data.data_out_last <= set_last;
                udp_tx_start_int <= tx_start_reg;
 
                -- set control signal defaults
                next_state <= IDLE;
                set_state <= '0';
                set_count <= HOLD;
                set_hdr <= '0';
                set_tx_start <= HOLD;
                set_last <= '0';
                set_tx_started <= HOLD;
                set_tx_fin <= HOLD;
                first_byte_rx <= (others => '0');
                udp_tx_int.data.data_out <= (others => '0');
                udp_tx_int.data.data_out_valid <= '0';
 
                -- FSM
                case state is
 
                        when IDLE =>
                                udp_tx_int.data.data_out_valid <= '0';
                                if udp_rx_start_int = '1' or PBTX = '1' then
                                        if udp_rx_start_int = '1' then
                                                first_byte_rx <= udp_rx_int.data.data_in;
                                        else
                                                first_byte_rx <= x"00";
                                        end if;
                                        set_tx_fin <= CLR;
                                        set_count <= RST;
                                        set_hdr <= '1';
                                        if udp_rx_int.data.data_in_last = '1' then
                                                set_tx_started <= SET;
                                                set_tx_start <= SET;
                                                next_state <= DATA_OUT;
                                                set_state <= '1';
                                        else
                                                next_state <= WAIT_RX_DONE;
                                                set_state <= '1';
                                        end if;
                                end if;
 
                        when WAIT_RX_DONE =>
                                -- wait until RX pkt fully received
                                if udp_rx_int.data.data_in_last = '1' then
                                        set_tx_started <= SET;
                                        set_tx_start <= SET;
                                        next_state <= DATA_OUT;
                                        set_state <= '1';
                                end if;
 
                        when DATA_OUT =>
                                if udp_tx_result_int = UDPTX_RESULT_ERR then
                                        -- have an error from the IP TX layer, clear down the TX
                                        set_tx_start <= CLR;
                                        set_tx_fin <= SET;
                                        set_tx_started <= CLR;
                                        next_state <= IDLE;
                                        set_state <= '1';
                                else
                                        if udp_tx_result_int = UDPTX_RESULT_SENDING then
                                                set_tx_start <= CLR;            -- reset out start req as soon as we know we are sending
                                        end if;
                                        if ip_rx_hdr_int.is_broadcast = '1' then
                                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
                                        else
                                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
                                        end if;
                                        udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
                                        if udp_tx_data_out_ready_int = '1' then
                                                if unsigned(count) = x"03" then
                                                        set_last <= '1';
                                                        set_tx_fin <= SET;
                                                        set_tx_started <= CLR;
                                                        next_state <= IDLE;
                                                        set_state <= '1';
                                                else
                                                        set_count <= INCR;
                                                end if;
                                        end if;
                                end if;
 
                end case;
        end process;
 
 
 
   -- TX response process - SEQ
   tx_proc_sequential: process(clk_int)
   begin
                if rising_edge(clk_int) then
                        if reset = '1' then
                                -- reset state variables
                                state <= IDLE;
                                count <= x"00";
                                tx_start_reg <= '0';
                                tx_hdr.dst_ip_addr <= (others => '0');
                                tx_hdr.dst_port <= (others => '0');
                                tx_hdr.src_port <= (others => '0');
                                tx_hdr.data_length <= (others => '0');
                                tx_hdr.checksum <= (others => '0');
                                tx_started_reg <= '0';
                                tx_fin_reg <= '0';
                                PBTX_LED <= '0';
                        else
                                PBTX_LED <= PBTX;
 
                                -- Next rx_state processing
                                if set_state = '1' then
                                        state <= next_state;
                                else
                                        state <= state;
                                end if;
 
                                -- count processing
                                case set_count is
                                        when RST =>             count <= x"00";
                                        when INCR =>            count <= count + 1;
                                        when HOLD =>            count <= count;
                                end case;
 
                                -- set tx hdr
                                if set_hdr = '1' then
                                        -- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
                                        if first_byte_rx = x"42" then
                                                tx_hdr.dst_ip_addr <= IP_BC_ADDR;       -- send to Broadcast addr
                                        elsif first_byte_rx = x"43" then
                                                tx_hdr.dst_ip_addr <= x"c0bbccdd";      -- set dst unknown so get ARP timeout
                                        else
                                                tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;       -- reply to sender
                                        end if;
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
                                        tx_hdr.data_length <= x"0004";
                                        tx_hdr.checksum <= x"0000";
                                else
                                        tx_hdr <= tx_hdr;
                                end if;
 
                                -- set tx start signal
                                case set_tx_start is
                                        when SET  => tx_start_reg <= '1';
                                        when CLR  => tx_start_reg <= '0';
                                        when HOLD => tx_start_reg <= tx_start_reg;
                                end case;
 
                                -- set tx started signal
                                case set_tx_started is
                                        when SET  => tx_started_reg <= '1';
                                        when CLR  => tx_started_reg <= '0';
                                        when HOLD => tx_started_reg <= tx_started_reg;
                                end case;
 
                                -- set tx finished signal
                                case set_tx_fin is
                                        when SET  => tx_fin_reg <= '1';
                                        when CLR  => tx_fin_reg <= '0';
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
                                end case;
 
 
                        end if;
                end if;
 
        end process;
 
 
 
   ------------------------------------------------------------------------------
   -- Instantiate the UDP layer
   ------------------------------------------------------------------------------
    UDP_block : UDP_Complete
                generic map (
                                ARP_TIMEOUT             => 30           -- timeout in seconds
                         )
                PORT MAP (
                                -- UDP interface
                                udp_tx_start                    => udp_tx_start_int,
                                udp_txi                                         => udp_tx_int,
                                udp_tx_result                   => udp_tx_result_int,
                                udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
                                udp_rx_start                    => udp_rx_start_int,
                                udp_rxo                                         => udp_rx_int,
                                -- IP RX signals
                                ip_rx_hdr                               => ip_rx_hdr_int,
                                -- System interface
                                clk_in_p             => clk_in_p,
                                clk_in_n             => clk_in_n,
                                clk_out                                 => clk_int,
                                reset                                   => reset,
                                our_ip_address          => our_ip,
                                our_mac_address                 => our_mac,
                                control                                 => control_int,
                                -- status signals
                                arp_pkt_count                   => arp_pkt_count_int,
                                ip_pkt_count                    => ip_pkt_count_int,
                                -- GMII Interface
                                -----------------     
                                phy_resetn        => phy_resetn,
                                gmii_txd                => gmii_txd,
                                gmii_tx_en        => gmii_tx_en,
                                gmii_tx_er        => gmii_tx_er,
                                gmii_tx_clk       => gmii_tx_clk,
                                gmii_rxd                => gmii_rxd,
                                gmii_rx_dv        => gmii_rx_dv,
                                gmii_rx_er        => gmii_rx_er,
                                gmii_rx_clk       => gmii_rx_clk,
                                gmii_col        => gmii_col,
                                gmii_crs                => gmii_crs,
                                mii_tx_clk        => mii_tx_clk
        );
 
 
end Behavioral;
 

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Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [contrib/] [from_tim/] [udp_ip_stack/] [tags/] [v1.3/] [rtl/] [vhdl/] [ml605/] [UDP_integration_example.vhd] - Blame information for rev 35

Line No.	Rev	Author	Line
1	35	pjf	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 11:01:00 06/11/2011`
6			`-- Design Name:`
7			`-- Module Name: UDP_integration_example - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.NUMERIC_STD.ALL;`
23			`use work.axi.all;`
24			`use work.ipv4_types.all;`
25			`use work.arp_types.all;`
26
27			`entity UDP_integration_example is`
28			`port (`
29			`-- System signals`
30			`------------------`
31			`reset : in std_logic; -- asynchronous reset`
32			`clk_in_p : in std_logic; -- 200MHz clock input from board`
33			`clk_in_n : in std_logic;`
34
35			`-- System controls`
36			`------------------`
37			`PBTX : in std_logic;`
38			`UDP_RX : out std_logic;`
39			`UDP_Start : out std_logic;`
40			`PBTX_LED : out std_logic;`
41			`TX_Started : out std_logic;`
42			`TX_Completed : out std_logic;`
43			`TX_RSLT_0 : out std_logic;`
44			`TX_RSLT_1 : out std_logic;`
45			`reset_leds : in std_logic;`
46			`display : out std_logic_vector(7 downto 0);`
47
48			`-- GMII Interface`
49			`-----------------`
50			`phy_resetn : out std_logic;`
51			`gmii_txd : out std_logic_vector(7 downto 0);`
52			`gmii_tx_en : out std_logic;`
53			`gmii_tx_er : out std_logic;`
54			`gmii_tx_clk : out std_logic;`
55			`gmii_rxd : in std_logic_vector(7 downto 0);`
56			`gmii_rx_dv : in std_logic;`
57			`gmii_rx_er : in std_logic;`
58			`gmii_rx_clk : in std_logic;`
59			`gmii_col : in std_logic;`
60			`gmii_crs : in std_logic;`
61			`mii_tx_clk : in std_logic`
62			`);`
63			`end UDP_integration_example;`
64
65			`architecture Behavioral of UDP_integration_example is`
66
67			`------------------------------------------------------------------------------`
68			`-- Component Declaration for the complete IP layer`
69			`------------------------------------------------------------------------------`
70			`component UDP_Complete`
71			`generic (`
72			`CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr`
73			`ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)`
74			`);`
75			`Port (`
76			`-- UDP TX signals`
77			`udp_tx_start : in std_logic; -- indicates req to tx UDP`
78			`udp_txi : in udp_tx_type; -- UDP tx cxns`
79			`udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)`
80			`udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data`
81			`-- UDP RX signals`
82			`udp_rx_start : out std_logic; -- indicates receipt of udp header`
83			`udp_rxo : out udp_rx_type;`
84			`-- IP RX signals`
85			`ip_rx_hdr : out ipv4_rx_header_type;`
86			`-- system signals`
87			`clk_in_p : in std_logic; -- 200MHz clock input from board`
88			`clk_in_n : in std_logic;`
89			`clk_out : out std_logic;`
90			`reset : in STD_LOGIC;`
91			`our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);`
92			`our_mac_address : in std_logic_vector (47 downto 0);`
93			`control : in udp_control_type;`
94			`-- status signals`
95			`arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received`
96			`ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us`
97			`-- GMII Interface`
98			`phy_resetn : out std_logic;`
99			`gmii_txd : out std_logic_vector(7 downto 0);`
100			`gmii_tx_en : out std_logic;`
101			`gmii_tx_er : out std_logic;`
102			`gmii_tx_clk : out std_logic;`
103			`gmii_rxd : in std_logic_vector(7 downto 0);`
104			`gmii_rx_dv : in std_logic;`
105			`gmii_rx_er : in std_logic;`
106			`gmii_rx_clk : in std_logic;`
107			`gmii_col : in std_logic;`
108			`gmii_crs : in std_logic;`
109			`mii_tx_clk : in std_logic`
110			`);`
111			`end component;`
112
113
114			`type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);`
115			`type count_mode_type is (RST, INCR, HOLD);`
116			`type set_clr_type is (SET, CLR, HOLD);`
117
118			`-- system signals`
119			`signal clk_int : std_logic;`
120			`signal our_mac : STD_LOGIC_VECTOR (47 downto 0);`
121			`signal our_ip : STD_LOGIC_VECTOR (31 downto 0);`
122			`signal udp_tx_int : udp_tx_type;`
123			`signal udp_tx_result_int : std_logic_vector (1 downto 0);`
124			`signal udp_tx_data_out_ready_int : std_logic;`
125			`signal udp_rx_int : udp_rx_type;`
126			`signal udp_tx_start_int : std_logic;`
127			`signal udp_rx_start_int : std_logic;`
128			`signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);`
129			`signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);`
130			`signal ip_rx_hdr_int : ipv4_rx_header_type;`
131
132			`-- state signals`
133			`signal state : state_type;`
134			`signal count : unsigned (7 downto 0);`
135			`signal tx_hdr : udp_tx_header_type;`
136			`signal tx_start_reg : std_logic;`
137			`signal tx_started_reg : std_logic;`
138			`signal tx_fin_reg : std_logic;`
139
140			`-- control signals`
141			`signal next_state : state_type;`
142			`signal set_state : std_logic;`
143			`signal set_count : count_mode_type;`
144			`signal set_hdr : std_logic;`
145			`signal set_tx_start : set_clr_type;`
146			`signal set_last : std_logic;`
147			`signal set_tx_started : set_clr_type;`
148			`signal set_tx_fin : set_clr_type;`
149			`signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);`
150			`signal control_int : udp_control_type;`
151
152			`begin`
153
154			`process (`
155			`our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,`
156			`udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,`
157			`reset, tx_started_reg, tx_fin_reg, tx_start_reg`
158			`)`
159			`begin`
160			`-- set up our local addresses and default controls`
161			`our_ip <= x"c0a80509"; -- 192.168.5.9`
162			`our_mac <= x"002320212223";`
163			`control_int.ip_controls.arp_controls.clear_cache <= '0';`
164
165			`-- determine RX good and error LEDs`
166			`if udp_rx_int.hdr.is_valid = '1' then`
167			`UDP_RX <= '1';`
168			`else`
169			`UDP_RX <= '0';`
170			`end if;`
171
172			`UDP_Start <= udp_rx_start_int;`
173			`TX_Started <= tx_start_reg; --tx_started_reg;`
174			`TX_Completed <= tx_fin_reg;`
175			`TX_RSLT_0 <= udp_tx_result_int(0);`
176			`TX_RSLT_1 <= udp_tx_result_int(1);`
177
178			`-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0`
179			`display (7 downto 4) <= ip_pkt_count_int (3 downto 0);`
180
181			`-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);`
182			`case state is`
183			`when IDLE => display (3 downto 0) <= "0001";`
184			`when WAIT_RX_DONE => display (3 downto 0) <= "0010";`
185			`when DATA_OUT => display (3 downto 0) <= "0011";`
186			`end case;`
187
188			`end process;`
189
190			`-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.`
191
192			`-- TX response process - COMB`
193			`tx_proc_combinatorial: process(`
194			`-- inputs`
195			`udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,`
196			`udp_tx_int.data.data_out_valid, PBTX,`
197			`-- state`
198			`state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,`
199			`-- controls`
200			`next_state, set_state, set_count, set_hdr, set_tx_start, set_last,`
201			`set_tx_started, set_tx_fin, first_byte_rx`
202			`)`
203			`begin`
204			`-- set output_followers`
205			`udp_tx_int.hdr <= tx_hdr;`
206			`udp_tx_int.data.data_out_last <= set_last;`
207			`udp_tx_start_int <= tx_start_reg;`
208
209			`-- set control signal defaults`
210			`next_state <= IDLE;`
211			`set_state <= '0';`
212			`set_count <= HOLD;`
213			`set_hdr <= '0';`
214			`set_tx_start <= HOLD;`
215			`set_last <= '0';`
216			`set_tx_started <= HOLD;`
217			`set_tx_fin <= HOLD;`
218			`first_byte_rx <= (others => '0');`
219			`udp_tx_int.data.data_out <= (others => '0');`
220			`udp_tx_int.data.data_out_valid <= '0';`
221
222			`-- FSM`
223			`case state is`
224
225			`when IDLE =>`
226			`udp_tx_int.data.data_out_valid <= '0';`
227			`if udp_rx_start_int = '1' or PBTX = '1' then`
228			`if udp_rx_start_int = '1' then`
229			`first_byte_rx <= udp_rx_int.data.data_in;`
230			`else`
231			`first_byte_rx <= x"00";`
232			`end if;`
233			`set_tx_fin <= CLR;`
234			`set_count <= RST;`
235			`set_hdr <= '1';`
236			`if udp_rx_int.data.data_in_last = '1' then`
237			`set_tx_started <= SET;`
238			`set_tx_start <= SET;`
239			`next_state <= DATA_OUT;`
240			`set_state <= '1';`
241			`else`
242			`next_state <= WAIT_RX_DONE;`
243			`set_state <= '1';`
244			`end if;`
245			`end if;`
246
247			`when WAIT_RX_DONE =>`
248			`-- wait until RX pkt fully received`
249			`if udp_rx_int.data.data_in_last = '1' then`
250			`set_tx_started <= SET;`
251			`set_tx_start <= SET;`
252			`next_state <= DATA_OUT;`
253			`set_state <= '1';`
254			`end if;`
255
256			`when DATA_OUT =>`
257			`if udp_tx_result_int = UDPTX_RESULT_ERR then`
258			`-- have an error from the IP TX layer, clear down the TX`
259			`set_tx_start <= CLR;`
260			`set_tx_fin <= SET;`
261			`set_tx_started <= CLR;`
262			`next_state <= IDLE;`
263			`set_state <= '1';`
264			`else`
265			`if udp_tx_result_int = UDPTX_RESULT_SENDING then`
266			`set_tx_start <= CLR; -- reset out start req as soon as we know we are sending`
267			`end if;`
268			`if ip_rx_hdr_int.is_broadcast = '1' then`
269			`udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";`
270			`else`
271			`udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";`
272			`end if;`
273			`udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;`
274			`if udp_tx_data_out_ready_int = '1' then`
275			`if unsigned(count) = x"03" then`
276			`set_last <= '1';`
277			`set_tx_fin <= SET;`
278			`set_tx_started <= CLR;`
279			`next_state <= IDLE;`
280			`set_state <= '1';`
281			`else`
282			`set_count <= INCR;`
283			`end if;`
284			`end if;`
285			`end if;`
286
287			`end case;`
288			`end process;`
289
290
291
292			`-- TX response process - SEQ`
293			`tx_proc_sequential: process(clk_int)`
294			`begin`
295			`if rising_edge(clk_int) then`
296			`if reset = '1' then`
297			`-- reset state variables`
298			`state <= IDLE;`
299			`count <= x"00";`
300			`tx_start_reg <= '0';`
301			`tx_hdr.dst_ip_addr <= (others => '0');`
302			`tx_hdr.dst_port <= (others => '0');`
303			`tx_hdr.src_port <= (others => '0');`
304			`tx_hdr.data_length <= (others => '0');`
305			`tx_hdr.checksum <= (others => '0');`
306			`tx_started_reg <= '0';`
307			`tx_fin_reg <= '0';`
308			`PBTX_LED <= '0';`
309			`else`
310			`PBTX_LED <= PBTX;`
311
312			`-- Next rx_state processing`
313			`if set_state = '1' then`
314			`state <= next_state;`
315			`else`
316			`state <= state;`
317			`end if;`
318
319			`-- count processing`
320			`case set_count is`
321			`when RST => count <= x"00";`
322			`when INCR => count <= count + 1;`
323			`when HOLD => count <= count;`
324			`end case;`
325
326			`-- set tx hdr`
327			`if set_hdr = '1' then`
328			`-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP`
329			`if first_byte_rx = x"42" then`
330			`tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr`
331			`elsif first_byte_rx = x"43" then`
332			`tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout`
333			`else`
334			`tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender`
335			`end if;`
336			`tx_hdr.dst_port <= udp_rx_int.hdr.src_port;`
337			`tx_hdr.src_port <= udp_rx_int.hdr.dst_port;`
338			`tx_hdr.data_length <= x"0004";`
339			`tx_hdr.checksum <= x"0000";`
340			`else`
341			`tx_hdr <= tx_hdr;`
342			`end if;`
343
344			`-- set tx start signal`
345			`case set_tx_start is`
346			`when SET => tx_start_reg <= '1';`
347			`when CLR => tx_start_reg <= '0';`
348			`when HOLD => tx_start_reg <= tx_start_reg;`
349			`end case;`
350
351			`-- set tx started signal`
352			`case set_tx_started is`
353			`when SET => tx_started_reg <= '1';`
354			`when CLR => tx_started_reg <= '0';`
355			`when HOLD => tx_started_reg <= tx_started_reg;`
356			`end case;`
357
358			`-- set tx finished signal`
359			`case set_tx_fin is`
360			`when SET => tx_fin_reg <= '1';`
361			`when CLR => tx_fin_reg <= '0';`
362			`when HOLD => tx_fin_reg <= tx_fin_reg;`
363			`end case;`
364
365
366			`end if;`
367			`end if;`
368
369			`end process;`
370
371
372
373			`------------------------------------------------------------------------------`
374			`-- Instantiate the UDP layer`
375			`------------------------------------------------------------------------------`
376			`UDP_block : UDP_Complete`
377			`generic map (`
378			`ARP_TIMEOUT => 30 -- timeout in seconds`
379			`)`
380			`PORT MAP (`
381			`-- UDP interface`
382			`udp_tx_start => udp_tx_start_int,`
383			`udp_txi => udp_tx_int,`
384			`udp_tx_result => udp_tx_result_int,`
385			`udp_tx_data_out_ready=> udp_tx_data_out_ready_int,`
386			`udp_rx_start => udp_rx_start_int,`
387			`udp_rxo => udp_rx_int,`
388			`-- IP RX signals`
389			`ip_rx_hdr => ip_rx_hdr_int,`
390			`-- System interface`
391			`clk_in_p => clk_in_p,`
392			`clk_in_n => clk_in_n,`
393			`clk_out => clk_int,`
394			`reset => reset,`
395			`our_ip_address => our_ip,`
396			`our_mac_address => our_mac,`
397			`control => control_int,`
398			`-- status signals`
399			`arp_pkt_count => arp_pkt_count_int,`
400			`ip_pkt_count => ip_pkt_count_int,`
401			`-- GMII Interface`
402			`-----------------`
403			`phy_resetn => phy_resetn,`
404			`gmii_txd => gmii_txd,`
405			`gmii_tx_en => gmii_tx_en,`
406			`gmii_tx_er => gmii_tx_er,`
407			`gmii_tx_clk => gmii_tx_clk,`
408			`gmii_rxd => gmii_rxd,`
409			`gmii_rx_dv => gmii_rx_dv,`
410			`gmii_rx_er => gmii_rx_er,`
411			`gmii_rx_clk => gmii_rx_clk,`
412			`gmii_col => gmii_col,`
413			`gmii_crs => gmii_crs,`
414			`mii_tx_clk => mii_tx_clk`
415			`);`
416
417
418			`end Behavioral;`
419