OpenCores
URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [contrib/] [from_tim/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [arp_SYNC.vhd] - Blame information for rev 35

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 35 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    14:09:01 02/20/2012 
6
-- Design Name: 
7
-- Module Name:    arp_SYNC - Behavioral - synchronises between rx and tx clock domains
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
----------------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.all;
22
use IEEE.NUMERIC_STD.all;
23
use work.arp_types.all;
24
 
25
entity arp_SYNC is
26
  port (
27
    -- REQ to TX
28
    arp_nwk_req           : in  arp_nwk_request_t;  -- request for a translation from IP to MAC
29
    send_who_has          : out std_logic;
30
    ip_entry              : out std_logic_vector (31 downto 0);
31
    -- RX to TX
32
    recv_who_has          : in  std_logic;          -- this is for us, we will respond
33
    arp_entry_for_who_has : in  arp_entry_t;
34
    send_I_have           : out std_logic;
35
    arp_entry             : out arp_entry_t;
36
    -- RX to REQ
37
    I_have_received       : in  std_logic;
38
    nwk_result_status     : out arp_nwk_rslt_t;
39
    -- System Signals
40
    rx_clk                : in  std_logic;
41
    tx_clk                : in  std_logic;
42
    reset                 : in  std_logic
43
    );
44
end arp_SYNC;
45
 
46
architecture Behavioral of arp_SYNC is
47
 
48
  type sync_state_t is (IDLE, HOLD1, HOLD2);
49
 
50
  -- state registers
51
  signal ip_entry_state  : sync_state_t;
52
  signal arp_entry_state : sync_state_t;
53
  signal ip_entry_reg    : std_logic_vector (31 downto 0);
54
  signal arp_entry_reg   : arp_entry_t;
55
 
56
  -- synchronisation registers  
57
  signal send_who_has_r1 : std_logic;
58
  signal send_who_has_r2 : std_logic;
59
  signal send_I_have_r1  : std_logic;
60
  signal send_I_have_r2  : std_logic;
61
 
62
begin
63
 
64
  combinatorial : process (
65
    -- input signals
66
    arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
67
    -- state
68
    ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
69
    -- synchronisation registers
70
    send_who_has_r1, send_who_has_r2,
71
    send_I_have_r1, send_I_have_r2
72
    )
73
  begin
74
    -- set output followers
75
    send_who_has <= send_who_has_r2;
76
    ip_entry     <= ip_entry_reg;
77
    send_I_have  <= send_I_have_r2;
78
    arp_entry    <= arp_entry_reg;
79
 
80
    -- combinaltorial outputs
81
    if I_have_received = '1' then
82
      nwk_result_status <= RECEIVED;
83
    else
84
      nwk_result_status <= IDLE;
85
    end if;
86
  end process;
87
 
88
  -- process for stablisising RX clock domain data registers
89
  -- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
90
  -- during transfer to TX clk domain
91
  rx_sequential : process (tx_clk)
92
  begin
93
    if rising_edge(tx_clk) then
94
      if reset = '1' then
95
        -- reset state variables
96
        ip_entry_reg      <= (others => '0');
97
        arp_entry_reg.ip  <= (others => '0');
98
        arp_entry_reg.mac <= (others => '0');
99
      else
100
        -- normal (non reset) processing
101
        case ip_entry_state is
102
          when IDLE =>
103
            if arp_nwk_req.req = '1' then
104
              ip_entry_reg   <= arp_nwk_req.ip;
105
              ip_entry_state <= HOLD1;
106
            else
107
              ip_entry_reg   <= ip_entry_reg;
108
              ip_entry_state <= IDLE;
109
            end if;
110
          when HOLD1 =>
111
            ip_entry_reg   <= ip_entry_reg;
112
            ip_entry_state <= HOLD2;
113
          when HOLD2 =>
114
            ip_entry_reg   <= ip_entry_reg;
115
            ip_entry_state <= IDLE;
116
        end case;
117
 
118
        case arp_entry_state is
119
          when IDLE =>
120
            if recv_who_has = '1' then
121
              arp_entry_reg   <= arp_entry_for_who_has;
122
              arp_entry_state <= HOLD1;
123
            else
124
              arp_entry_reg   <= arp_entry_reg;
125
              arp_entry_state <= IDLE;
126
            end if;
127
          when HOLD1 =>
128
            arp_entry_reg   <= arp_entry_reg;
129
            arp_entry_state <= HOLD2;
130
          when HOLD2 =>
131
            arp_entry_reg   <= arp_entry_reg;
132
            arp_entry_state <= IDLE;
133
        end case;
134
      end if;
135
    end if;
136
  end process;
137
 
138
  -- process for syncing to the TX clock domain
139
  -- clocks control signals through 2 layers of tx clocking
140
  tx_sequential : process (tx_clk)
141
  begin
142
    if rising_edge(tx_clk) then
143
      if reset = '1' then
144
        -- reset state variables
145
        send_who_has_r1 <= '0';
146
        send_who_has_r2 <= '0';
147
        send_I_have_r1  <= '0';
148
        send_I_have_r2  <= '0';
149
      else
150
        -- normal (non reset) processing
151
 
152
        send_who_has_r1 <= arp_nwk_req.req;
153
        send_who_has_r2 <= send_who_has_r1;
154
 
155
        send_I_have_r1 <= recv_who_has;
156
        send_I_have_r2 <= send_I_have_r1;
157
      end if;
158
    end if;
159
  end process;
160
 
161
 
162
end Behavioral;
163
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.